Commit d0f48074dbc21248f3b0a9fb48126cb0d95991b5
1 parent
89fc88da
Update TODO.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3383 c046a42c-6fe2-441c-8c8c-71466251a162
Showing
1 changed file
with
26 additions
and
1 deletions
target-mips/TODO
| ... | ... | @@ -3,7 +3,32 @@ Unsolved issues/bugs in the mips/mipsel backend |
| 3 | 3 | |
| 4 | 4 | General |
| 5 | 5 | ------- |
| 6 | -- [ls][dw][lr] report broken (aligned) BadVAddr | |
| 6 | +- Unimplemented ASEs: | |
| 7 | + - MIPS16 | |
| 8 | + - MDMX | |
| 9 | + - SmartMIPS | |
| 10 | + - DSP r1 | |
| 11 | + - DSP r2 | |
| 12 | +- MT ASE only partially implemented and not functional | |
| 13 | +- Shadow register support only partially implemented, | |
| 14 | + lacks set switching on interrupt/exception. | |
| 15 | +- 34K ITC not implemented. | |
| 16 | +- A general lack of documentation, especially for technical internals. | |
| 17 | + Existing documentation is x86-centric. | |
| 18 | +- Reverse endianness bit not implemented | |
| 19 | +- The TLB emulation is very inefficient: | |
| 20 | + Qemu's softmmu implements a x86-style MMU, with separate entries | |
| 21 | + for read/write/execute, a TLB index which is just a modulo of the | |
| 22 | + virtual address, and a set of TLBs for each user/kernel/supervisor | |
| 23 | + MMU mode. | |
| 24 | + MIPS has a single entry for read/write/execute and only one MMU mode. | |
| 25 | + But it is fully associative with randomized entry indices, and uses | |
| 26 | + up to 256 ASID tags as additional matching criterion (which roughly | |
| 27 | + equates to 256 MMU modes). It also has a global flag which causes | |
| 28 | + entries to match regardless of ASID. | |
| 29 | + To cope with these differences, Qemu currently flushes the TLB at | |
| 30 | + each ASID change. Using the MMU modes to implement ASIDs hinges on | |
| 31 | + implementing the global bit efficiently. | |
| 7 | 32 | |
| 8 | 33 | MIPS64 |
| 9 | 34 | ------ | ... | ... |