Commit d0ef528a3ecf8d554052ed6e3799b53c6c935300
1 parent
1e5459a3
SH: Don't subtract bases from access addresses in PCIC.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5928 c046a42c-6fe2-441c-8c8c-71466251a162
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1 changed file
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3 additions
and
5 deletions
hw/sh_pci.c
| @@ -40,7 +40,6 @@ typedef struct { | @@ -40,7 +40,6 @@ typedef struct { | ||
| 40 | static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) | 40 | static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) |
| 41 | { | 41 | { |
| 42 | SHPCIC *pcic = p; | 42 | SHPCIC *pcic = p; |
| 43 | - addr -= pcic->regbase; | ||
| 44 | switch(addr) { | 43 | switch(addr) { |
| 45 | case 0 ... 0xfc: | 44 | case 0 ... 0xfc: |
| 46 | cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); | 45 | cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); |
| @@ -63,7 +62,6 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) | @@ -63,7 +62,6 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) | ||
| 63 | static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) | 62 | static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) |
| 64 | { | 63 | { |
| 65 | SHPCIC *pcic = p; | 64 | SHPCIC *pcic = p; |
| 66 | - addr -= pcic->regbase; | ||
| 67 | switch(addr) { | 65 | switch(addr) { |
| 68 | case 0 ... 0xfc: | 66 | case 0 ... 0xfc: |
| 69 | return le32_to_cpup((uint32_t*)(pcic->dev->config + addr)); | 67 | return le32_to_cpup((uint32_t*)(pcic->dev->config + addr)); |
| @@ -78,13 +76,13 @@ static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) | @@ -78,13 +76,13 @@ static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) | ||
| 78 | static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr, | 76 | static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr, |
| 79 | uint32_t val, int size) | 77 | uint32_t val, int size) |
| 80 | { | 78 | { |
| 81 | - pci_data_write(pcic->bus, addr - pcic->membase + pcic->mbr, val, size); | 79 | + pci_data_write(pcic->bus, addr + pcic->mbr, val, size); |
| 82 | } | 80 | } |
| 83 | 81 | ||
| 84 | static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr, | 82 | static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr, |
| 85 | int size) | 83 | int size) |
| 86 | { | 84 | { |
| 87 | - return pci_data_read(pcic->bus, addr - pcic->membase + pcic->mbr, size); | 85 | + return pci_data_read(pcic->bus, addr + pcic->mbr, size); |
| 88 | } | 86 | } |
| 89 | 87 | ||
| 90 | static void sh_pci_writeb (void *p, target_phys_addr_t addr, uint32_t val) | 88 | static void sh_pci_writeb (void *p, target_phys_addr_t addr, uint32_t val) |
| @@ -119,7 +117,7 @@ static uint32_t sh_pci_readl (void *p, target_phys_addr_t addr) | @@ -119,7 +117,7 @@ static uint32_t sh_pci_readl (void *p, target_phys_addr_t addr) | ||
| 119 | 117 | ||
| 120 | static int sh_pci_addr2port(SHPCIC *pcic, target_phys_addr_t addr) | 118 | static int sh_pci_addr2port(SHPCIC *pcic, target_phys_addr_t addr) |
| 121 | { | 119 | { |
| 122 | - return addr - pcic->iopbase + pcic->iobr; | 120 | + return addr + pcic->iobr; |
| 123 | } | 121 | } |
| 124 | 122 | ||
| 125 | static void sh_pci_outb (void *p, target_phys_addr_t addr, uint32_t val) | 123 | static void sh_pci_outb (void *p, target_phys_addr_t addr, uint32_t val) |