gwj / at91sam9263 · Commits

Commit d084469ca0a0fb7c7f51dbe9062092c6983dfa02

Authored by Blue Swirl
1 parent 6c78ea32

Convert mulscc 

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Inline Side-by-side
Showing 1 changed file with 2 additions and 131 deletions
target-sparc/translate.c
  View file @d084469
... ... @@ -274,130 +274,6 @@ static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
274 274 tcg_gen_andi_tl(reg, reg, 0x1);
275 275 }
276 276  
277   -static inline void gen_cc_clear_icc(void)
278   -{
279   - tcg_gen_movi_i32(cpu_psr, 0);
280   -}
281   -
282   -#ifdef TARGET_SPARC64
283   -static inline void gen_cc_clear_xcc(void)
284   -{
285   - tcg_gen_movi_i32(cpu_xcc, 0);
286   -}
287   -#endif
288   -
289   -/* old op:
290   - if (!T0)
291   - env->psr |= PSR_ZERO;
292   - if ((int32_t) T0 < 0)
293   - env->psr |= PSR_NEG;
294   -*/
295   -static inline void gen_cc_NZ_icc(TCGv dst)
296   -{
297   - TCGv r_temp;
298   - int l1, l2;
299   -
300   - l1 = gen_new_label();
301   - l2 = gen_new_label();
302   - r_temp = tcg_temp_new();
303   - tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
304   - tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
305   - tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
306   - gen_set_label(l1);
307   - tcg_gen_ext32s_tl(r_temp, dst);
308   - tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
309   - tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
310   - gen_set_label(l2);
311   - tcg_temp_free(r_temp);
312   -}
313   -
314   -#ifdef TARGET_SPARC64
315   -static inline void gen_cc_NZ_xcc(TCGv dst)
316   -{
317   - int l1, l2;
318   -
319   - l1 = gen_new_label();
320   - l2 = gen_new_label();
321   - tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
322   - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
323   - gen_set_label(l1);
324   - tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
325   - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
326   - gen_set_label(l2);
327   -}
328   -#endif
329   -
330   -/* old op:
331   - if (T0 < src1)
332   - env->psr |= PSR_CARRY;
333   -*/
334   -static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
335   -{
336   - TCGv r_temp1, r_temp2;
337   - int l1;
338   -
339   - l1 = gen_new_label();
340   - r_temp1 = tcg_temp_new();
341   - r_temp2 = tcg_temp_new();
342   - tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL);
343   - tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL);
344   - tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
345   - tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
346   - gen_set_label(l1);
347   - tcg_temp_free(r_temp1);
348   - tcg_temp_free(r_temp2);
349   -}
350   -
351   -#ifdef TARGET_SPARC64
352   -static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
353   -{
354   - int l1;
355   -
356   - l1 = gen_new_label();
357   - tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
358   - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
359   - gen_set_label(l1);
360   -}
361   -#endif
362   -
363   -/* old op:
364   - if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
365   - env->psr |= PSR_OVF;
366   -*/
367   -static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
368   -{
369   - TCGv r_temp;
370   -
371   - r_temp = tcg_temp_new();
372   - tcg_gen_xor_tl(r_temp, src1, src2);
373   - tcg_gen_not_tl(r_temp, r_temp);
374   - tcg_gen_xor_tl(cpu_tmp0, src1, dst);
375   - tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
376   - tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
377   - tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
378   - tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
379   - tcg_temp_free(r_temp);
380   - tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
381   -}
382   -
383   -#ifdef TARGET_SPARC64
384   -static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
385   -{
386   - TCGv r_temp;
387   -
388   - r_temp = tcg_temp_new();
389   - tcg_gen_xor_tl(r_temp, src1, src2);
390   - tcg_gen_not_tl(r_temp, r_temp);
391   - tcg_gen_xor_tl(cpu_tmp0, src1, dst);
392   - tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
393   - tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
394   - tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
395   - tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
396   - tcg_temp_free(r_temp);
397   - tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
398   -}
399   -#endif
400   -
401 277 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
402 278 {
403 279 TCGv r_temp;
... ... @@ -612,13 +488,8 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
612 488 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
613 489 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
614 490  
615   - /* do addition and update flags */
616 491 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
617 492  
618   - gen_cc_clear_icc();
619   - gen_cc_NZ_icc(cpu_cc_dst);
620   - gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
621   - gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
622 493 tcg_gen_mov_tl(dst, cpu_cc_dst);
623 494 }
624 495  
... ... @@ -3190,8 +3061,8 @@ static void disas_sparc_insn(DisasContext * dc)
3190 3061 gen_helper_compute_psr();
3191 3062 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3192 3063 gen_movl_TN_reg(rd, cpu_dst);
3193   - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3194   - dc->cc_op = CC_OP_FLAGS;
  3064 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
  3065 + dc->cc_op = CC_OP_ADD;
3195 3066 break;
3196 3067 #ifndef TARGET_SPARC64
3197 3068 case 0x25: /* sll */
... ...