gwj / at91sam9263 · Commits

Commit cf965d24064671ce2d5a874e532b8189fdb6e863

Authored by balrog
1 parent 51a65271

Add register mappings in DSP space (must be accessible for MPU too). 

Don't set microwire CSR-busy bit too early.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3530 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 4 changed files with 66 additions and 22 deletions
hw/omap.c
  View file @cf965d2
... ... @@ -1401,7 +1401,7 @@ struct omap_32khz_timer_s {
1401 1401 static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
1402 1402 {
1403 1403 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
1404   - int offset = addr - s->timer.base;
  1404 + int offset = addr & OMAP_MPUI_REG_MASK;
1405 1405  
1406 1406 switch (offset) {
1407 1407 case 0x00: /* TVR */
... ... @@ -1424,7 +1424,7 @@ static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
1424 1424 uint32_t value)
1425 1425 {
1426 1426 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
1427   - int offset = addr - s->timer.base;
  1427 + int offset = addr & OMAP_MPUI_REG_MASK;
1428 1428  
1429 1429 switch (offset) {
1430 1430 case 0x00: /* TVR */
... ... @@ -2894,7 +2894,7 @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
2894 2894 static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
2895 2895 {
2896 2896 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2897   - int offset = addr - s->base;
  2897 + int offset = addr & OMAP_MPUI_REG_MASK;
2898 2898 uint16_t ret;
2899 2899  
2900 2900 switch (offset) {
... ... @@ -2950,7 +2950,7 @@ static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
2950 2950 uint32_t value)
2951 2951 {
2952 2952 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2953   - int offset = addr - s->base;
  2953 + int offset = addr & OMAP_MPUI_REG_MASK;
2954 2954 uint16_t diff;
2955 2955 int ln;
2956 2956  
... ... @@ -3142,7 +3142,7 @@ static void omap_gpio_set(void *opaque, int line, int level)
3142 3142 static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
3143 3143 {
3144 3144 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
3145   - int offset = addr - s->base;
  3145 + int offset = addr & OMAP_MPUI_REG_MASK;
3146 3146  
3147 3147 switch (offset) {
3148 3148 case 0x00: /* DATA_INPUT */
... ... @@ -3172,7 +3172,7 @@ static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
3172 3172 uint32_t value)
3173 3173 {
3174 3174 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
3175   - int offset = addr - s->base;
  3175 + int offset = addr & OMAP_MPUI_REG_MASK;
3176 3176 uint16_t diff;
3177 3177 int ln;
3178 3178  
... ... @@ -3322,7 +3322,7 @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s)
3322 3322 static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
3323 3323 {
3324 3324 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
3325   - int offset = addr - s->base;
  3325 + int offset = addr & OMAP_MPUI_REG_MASK;
3326 3326  
3327 3327 switch (offset) {
3328 3328 case 0x00: /* RDR */
... ... @@ -3352,16 +3352,17 @@ static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
3352 3352 uint32_t value)
3353 3353 {
3354 3354 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
3355   - int offset = addr - s->base;
  3355 + int offset = addr & OMAP_MPUI_REG_MASK;
3356 3356  
3357 3357 switch (offset) {
3358 3358 case 0x00: /* TDR */
3359 3359 s->txbuf = value; /* TD */
3360   - s->control |= 1 << 14; /* CSRB */
3361 3360 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
3362 3361 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
3363   - (s->control & (1 << 12)))) /* CS_CMD */
  3362 + (s->control & (1 << 12)))) { /* CS_CMD */
  3363 + s->control |= 1 << 14; /* CSRB */
3364 3364 omap_uwire_transfer_start(s);
  3365 + }
3365 3366 break;
3366 3367  
3367 3368 case 0x04: /* CSR */
... ... @@ -3462,7 +3463,7 @@ void omap_pwl_update(struct omap_mpu_state_s *s)
3462 3463 static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
3463 3464 {
3464 3465 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3465   - int offset = addr - s->pwl.base;
  3466 + int offset = addr & OMAP_MPUI_REG_MASK;
3466 3467  
3467 3468 switch (offset) {
3468 3469 case 0x00: /* PWL_LEVEL */
... ... @@ -3478,7 +3479,7 @@ static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
3478 3479 uint32_t value)
3479 3480 {
3480 3481 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3481   - int offset = addr - s->pwl.base;
  3482 + int offset = addr & OMAP_MPUI_REG_MASK;
3482 3483  
3483 3484 switch (offset) {
3484 3485 case 0x00: /* PWL_LEVEL */
... ... @@ -3542,7 +3543,7 @@ static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
3542 3543 static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
3543 3544 {
3544 3545 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3545   - int offset = addr - s->pwt.base;
  3546 + int offset = addr & OMAP_MPUI_REG_MASK;
3546 3547  
3547 3548 switch (offset) {
3548 3549 case 0x00: /* FRC */
... ... @@ -3560,7 +3561,7 @@ static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
3560 3561 uint32_t value)
3561 3562 {
3562 3563 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3563   - int offset = addr - s->pwt.base;
  3564 + int offset = addr & OMAP_MPUI_REG_MASK;
3564 3565  
3565 3566 switch (offset) {
3566 3567 case 0x00: /* FRC */
... ... @@ -3679,7 +3680,7 @@ static inline int omap_rtc_bin(uint8_t num)
3679 3680 static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
3680 3681 {
3681 3682 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
3682   - int offset = addr - s->base;
  3683 + int offset = addr & OMAP_MPUI_REG_MASK;
3683 3684 uint8_t i;
3684 3685  
3685 3686 switch (offset) {
... ... @@ -3757,7 +3758,7 @@ static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
3757 3758 uint32_t value)
3758 3759 {
3759 3760 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
3760   - int offset = addr - s->base;
  3761 + int offset = addr & OMAP_MPUI_REG_MASK;
3761 3762 struct tm new_tm;
3762 3763 time_t ti[2];
3763 3764  
... ... @@ -4094,6 +4095,47 @@ static void omap_mpu_reset(void *opaque)
4094 4095 cpu_reset(mpu->env);
4095 4096 }
4096 4097  
  4098 +static const struct omap_map_s {
  4099 + target_phys_addr_t phys_dsp;
  4100 + target_phys_addr_t phys_mpu;
  4101 + uint32_t size;
  4102 + const char *name;
  4103 +} omap15xx_dsp_mm[] = {
  4104 + /* Strobe 0 */
  4105 + { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
  4106 + { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
  4107 + { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
  4108 + { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
  4109 + { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
  4110 + { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
  4111 + { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
  4112 + { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
  4113 + { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
  4114 + { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
  4115 + { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
  4116 + { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
  4117 + { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
  4118 + { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
  4119 + { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
  4120 + { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
  4121 + { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
  4122 + /* Strobe 1 */
  4123 + { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
  4124 +
  4125 + { 0 }
  4126 +};
  4127 +
  4128 +static void omap_setup_dsp_mapping(const struct omap_map_s *map)
  4129 +{
  4130 + int io;
  4131 +
  4132 + for (; map->phys_dsp; map ++) {
  4133 + io = cpu_get_physical_page_desc(map->phys_mpu);
  4134 +
  4135 + cpu_register_physical_memory(map->phys_dsp, map->size, io);
  4136 + }
  4137 +}
  4138 +
4097 4139 static void omap_mpu_wakeup(void *opaque, int irq, int req)
4098 4140 {
4099 4141 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
... ... @@ -4241,6 +4283,8 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
4241 4283 * DSP MMU fffed200 - fffed2ff
4242 4284 */
4243 4285  
  4286 + omap_setup_dsp_mapping(omap15xx_dsp_mm);
  4287 +
4244 4288 qemu_register_reset(omap_mpu_reset, s);
4245 4289  
4246 4290 return s;
... ...
hw/omap.h
  View file @cf965d2
... ... @@ -546,7 +546,6 @@ struct omap_mpu_state_s {
546 546 struct omap_uwire_s *microwire;
547 547  
548 548 struct {
549   - target_phys_addr_t base;
550 549 uint8_t output;
551 550 uint8_t level;
552 551 uint8_t enable;
... ... @@ -554,7 +553,6 @@ struct omap_mpu_state_s {
554 553 } pwl;
555 554  
556 555 struct {
557   - target_phys_addr_t base;
558 556 uint8_t frc;
559 557 uint8_t vrc;
560 558 uint8_t gcr;
... ... @@ -665,4 +663,6 @@ void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
665 663 # define OMAP_32B_REG(paddr)
666 664 # endif
667 665  
  666 +# define OMAP_MPUI_REG_MASK 0x000007ff
  667 +
668 668 #endif /* hw_omap_h */
... ...
hw/omap_i2c.c
  View file @cf965d2
... ... @@ -194,7 +194,7 @@ void omap_i2c_reset(struct omap_i2c_s *s)
194 194 static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
195 195 {
196 196 struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
197   - int offset = addr - s->base;
  197 + int offset = addr & OMAP_MPUI_REG_MASK;
198 198 uint16_t ret;
199 199  
200 200 switch (offset) {
... ... @@ -286,7 +286,7 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
286 286 uint32_t value)
287 287 {
288 288 struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
289   - int offset = addr - s->base;
  289 + int offset = addr & OMAP_MPUI_REG_MASK;
290 290 int nack;
291 291  
292 292 switch (offset) {
... ...
hw/omap_mmc.c
  View file @cf965d2
... ... @@ -269,7 +269,7 @@ static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
269 269 {
270 270 uint16_t i;
271 271 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
272   - offset -= s->base;
  272 + offset &= OMAP_MPUI_REG_MASK;
273 273  
274 274 switch (offset) {
275 275 case 0x00: /* MMC_CMD */
... ... @@ -351,7 +351,7 @@ static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
351 351 {
352 352 int i;
353 353 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
354   - offset -= s->base;
  354 + offset &= OMAP_MPUI_REG_MASK;
355 355  
356 356 switch (offset) {
357 357 case 0x00: /* MMC_CMD */
... ...