Commit cf960816f90559ddf26cb8445e55e9dffeaf5174

Authored by aurel32
1 parent 1b581c44

target-ppc: use the new TCG logical operations

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5503 c046a42c-6fe2-441c-8c8c-71466251a162
Showing 1 changed file with 10 additions and 55 deletions
target-ppc/translate.c
@@ -5730,7 +5730,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -5730,7 +5730,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
5730 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \ 5730 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
5731 } 5731 }
5732 5732
5733 -#define GEN_SPEOP_TCG_ARITH2(name) \ 5733 +#define GEN_SPEOP_TCG_ARITH2(name, tcg_op) \
5734 static always_inline void gen_##name (DisasContext *ctx) \ 5734 static always_inline void gen_##name (DisasContext *ctx) \
5735 { \ 5735 { \
5736 if (unlikely(!ctx->spe_enabled)) { \ 5736 if (unlikely(!ctx->spe_enabled)) { \
@@ -5741,7 +5741,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -5741,7 +5741,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
5741 TCGv t1 = tcg_temp_new(TCG_TYPE_I64); \ 5741 TCGv t1 = tcg_temp_new(TCG_TYPE_I64); \
5742 gen_load_gpr64(t0, rA(ctx->opcode)); \ 5742 gen_load_gpr64(t0, rA(ctx->opcode)); \
5743 gen_load_gpr64(t1, rB(ctx->opcode)); \ 5743 gen_load_gpr64(t1, rB(ctx->opcode)); \
5744 - gen_op_##name(t0, t1); \ 5744 + tcg_op(t0, t0, t1); \
5745 gen_store_gpr64(rD(ctx->opcode), t0); \ 5745 gen_store_gpr64(rD(ctx->opcode), t0); \
5746 tcg_temp_free(t0); \ 5746 tcg_temp_free(t0); \
5747 tcg_temp_free(t1); \ 5747 tcg_temp_free(t1); \
@@ -5773,59 +5773,14 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -5773,59 +5773,14 @@ static always_inline void gen_##name (DisasContext *ctx) \
5773 } 5773 }
5774 5774
5775 /* Logical */ 5775 /* Logical */
5776 -static always_inline void gen_op_evand (TCGv t0, TCGv t1)  
5777 -{  
5778 - tcg_gen_and_i64(t0, t0, t1);  
5779 -}  
5780 -  
5781 -static always_inline void gen_op_evandc (TCGv t0, TCGv t1)  
5782 -{  
5783 - tcg_gen_not_i64(t1, t1);  
5784 - tcg_gen_and_i64(t0, t0, t1);  
5785 -}  
5786 -  
5787 -static always_inline void gen_op_evxor (TCGv t0, TCGv t1)  
5788 -{  
5789 - tcg_gen_xor_i64(t0, t0, t1);  
5790 -}  
5791 -  
5792 -static always_inline void gen_op_evor (TCGv t0, TCGv t1)  
5793 -{  
5794 - tcg_gen_or_i64(t0, t0, t1);  
5795 -}  
5796 -  
5797 -static always_inline void gen_op_evnor (TCGv t0, TCGv t1)  
5798 -{  
5799 - tcg_gen_or_i64(t0, t0, t1);  
5800 - tcg_gen_not_i64(t0, t0);  
5801 -}  
5802 -  
5803 -static always_inline void gen_op_eveqv (TCGv t0, TCGv t1)  
5804 -{  
5805 - tcg_gen_xor_i64(t0, t0, t1);  
5806 - tcg_gen_not_i64(t0, t0);  
5807 -}  
5808 -  
5809 -static always_inline void gen_op_evorc (TCGv t0, TCGv t1)  
5810 -{  
5811 - tcg_gen_not_i64(t1, t1);  
5812 - tcg_gen_or_i64(t0, t0, t1);  
5813 -}  
5814 -  
5815 -static always_inline void gen_op_evnand (TCGv t0, TCGv t1)  
5816 -{  
5817 - tcg_gen_and_i64(t0, t0, t1);  
5818 - tcg_gen_not_i64(t0, t0);  
5819 -}  
5820 -  
5821 -GEN_SPEOP_TCG_ARITH2(evand);  
5822 -GEN_SPEOP_TCG_ARITH2(evandc);  
5823 -GEN_SPEOP_TCG_ARITH2(evxor);  
5824 -GEN_SPEOP_TCG_ARITH2(evor);  
5825 -GEN_SPEOP_TCG_ARITH2(evnor);  
5826 -GEN_SPEOP_TCG_ARITH2(eveqv);  
5827 -GEN_SPEOP_TCG_ARITH2(evorc);  
5828 -GEN_SPEOP_TCG_ARITH2(evnand); 5776 +GEN_SPEOP_TCG_ARITH2(evand, tcg_gen_and_i64);
  5777 +GEN_SPEOP_TCG_ARITH2(evandc, tcg_gen_andc_i64);
  5778 +GEN_SPEOP_TCG_ARITH2(evxor, tcg_gen_xor_i64);
  5779 +GEN_SPEOP_TCG_ARITH2(evor, tcg_gen_or_i64);
  5780 +GEN_SPEOP_TCG_ARITH2(evnor, tcg_gen_nor_i64);
  5781 +GEN_SPEOP_TCG_ARITH2(eveqv, tcg_gen_eqv_i64);
  5782 +GEN_SPEOP_TCG_ARITH2(evorc, tcg_gen_orc_i64);
  5783 +GEN_SPEOP_TCG_ARITH2(evnand, tcg_gen_nand_i64);
5829 GEN_SPEOP_ARITH2(evsrwu); 5784 GEN_SPEOP_ARITH2(evsrwu);
5830 GEN_SPEOP_ARITH2(evsrws); 5785 GEN_SPEOP_ARITH2(evsrws);
5831 GEN_SPEOP_ARITH2(evslw); 5786 GEN_SPEOP_ARITH2(evslw);