gwj / at91sam9263 · Commits

Commit cef3017cd7c0d63a12ff743e1e72caf49779c493

Authored by aliguori
1 parent 81f099ad

Clean some PCI defines (Stefan Weil) 

this patch adds some more defines from linux/pci_regs.h to
hw/pci.h. There is now no longer a need to define them in
eepro100.c, so they were removed there.

Some defines from linux/pci_regs.h had similar, but not
the same defines in hw/pci.h (PCI_REVISION_ID / PCI_REVISION,
PCI_SUBSYSTEM_VENDOR_ID / PCI_SUBVENDOR_ID,
PCI_SUBSYSTEM_ID / PCI_SUBDEVICE_ID).

I suggest to use the "standard" from linux/pci_regs.h and
replace the "old" Qemu ones. To facilitate the migration,
my patch does not remove the old defines but marks them
as obsolete. After a migration to the "standard" defines,
pci.h could use linux/pci_regs.h which is far more complete.

The patch is needed for an updated maintainer version of
hw/eepro100.c which I'd like to see in Qemu stable.

 * Remove declarations already declared in header file from eepro100.c
 * Add missing declarations from pci_regs.h to pci.h
 * Mark "non-standard" declarations in pci.h as obsolete

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6901 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 11 additions and 10 deletions
hw/eepro100.c
  View file @cef3017
@@ -47,12 +47,6 @@ @@ -47,12 +47,6 @@
47 47
48 /* Common declarations for all PCI devices. */ 48 /* Common declarations for all PCI devices. */
49 49
50 -#define PCI_DEVICE_ID 0x02 /* 16 bits */  
51 -#define PCI_COMMAND 0x04 /* 16 bits */  
52 -#define PCI_STATUS 0x06 /* 16 bits */  
53 -  
54 -#define PCI_REVISION_ID 0x08 /* 8 bits */  
55 -  
56 #define PCI_CONFIG_8(offset, value) \ 50 #define PCI_CONFIG_8(offset, value) \
57 (pci_conf[offset] = (value)) 51 (pci_conf[offset] = (value))
58 #define PCI_CONFIG_16(offset, value) \ 52 #define PCI_CONFIG_16(offset, value) \
hw/pci.h
  View file @cef3017
@@ -55,7 +55,7 @@ extern target_phys_addr_t pci_mem_base; @@ -55,7 +55,7 @@ extern target_phys_addr_t pci_mem_base;
55 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 55 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
56 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 56 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
57 57
58 -#define PCI_VENDOR_ID_INTEL 0x8086 58 +/* Intel (0x8086) */
59 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 59 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
60 60
61 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 61 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
@@ -92,20 +92,27 @@ typedef struct PCIIORegion { @@ -92,20 +92,27 @@ typedef struct PCIIORegion {
92 92
93 #define PCI_DEVICES_MAX 64 93 #define PCI_DEVICES_MAX 64
94 94
  95 +/* Declarations from linux/pci_regs.h */
95 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 96 #define PCI_VENDOR_ID 0x00 /* 16 bits */
96 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 97 #define PCI_DEVICE_ID 0x02 /* 16 bits */
97 #define PCI_COMMAND 0x04 /* 16 bits */ 98 #define PCI_COMMAND 0x04 /* 16 bits */
98 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 99 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
99 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 100 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
100 -#define PCI_REVISION 0x08 101 +#define PCI_STATUS 0x06 /* 16 bits */
  102 +#define PCI_REVISION_ID 0x08 /* 8 bits */
101 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 103 #define PCI_CLASS_DEVICE 0x0a /* Device class */
102 -#define PCI_SUBVENDOR_ID 0x2c /* 16 bits */  
103 -#define PCI_SUBDEVICE_ID 0x2e /* 16 bits */ 104 +#define PCI_HEADER_TYPE 0x0e /* 8 bits */
  105 +#define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */
  106 +#define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */
104 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 107 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
105 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 108 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
106 #define PCI_MIN_GNT 0x3e /* 8 bits */ 109 #define PCI_MIN_GNT 0x3e /* 8 bits */
107 #define PCI_MAX_LAT 0x3f /* 8 bits */ 110 #define PCI_MAX_LAT 0x3f /* 8 bits */
108 111
  112 +#define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */
  113 +#define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
  114 +#define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */
  115 +
109 /* Bits in the PCI Status Register (PCI 2.3 spec) */ 116 /* Bits in the PCI Status Register (PCI 2.3 spec) */
110 #define PCI_STATUS_RESERVED1 0x007 117 #define PCI_STATUS_RESERVED1 0x007
111 #define PCI_STATUS_INT_STATUS 0x008 118 #define PCI_STATUS_INT_STATUS 0x008