moved halted field to CPU_COMMON

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162

moved halted field to CPU_COMMON
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
bellard
1 parent d377440d
Showing 16 changed files with 11 additions and 28 deletions
cpu-defs.h
hw/apic.c
hw/pc.c
monitor.c
target-alpha/cpu.h
target-arm/cpu.h
target-cris/cpu.h
target-i386/cpu.h
target-i386/exec.h
target-i386/helper.c
target-i386/op_helper.c
target-m68k/cpu.h
target-mips/cpu.h
target-ppc/cpu.h
target-sh4/cpu.h
target-sparc/cpu.h
@@ -140,6 +140,7 @@ typedef struct CPUTLBEntry {
                                    written */                           \
     target_ulong mem_write_vaddr; /* target virtual addr at which the   \
                                      memory was written */              \
+    int halted; /* TRUE if the CPU is in suspend state */               \
     /* The meaning of the MMU modes is defined in the target code. */   \
     CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
@@ -443,12 +443,12 @@ static void apic_init_ipi(APICState *s)
 static void apic_startup(APICState *s, int vector_num)
 {
     CPUState *env = s->cpu_env;
-    if (!(env->hflags & HF_HALTED_MASK))
+    if (!env->halted)
         return;
     env->eip = 0;
     cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
                            0xffff, 0);
-    env->hflags &= ~HF_HALTED_MASK;
+    env->halted = 0;
 }
 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
@@ -761,7 +761,7 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
             exit(1);
         }
         if (i != 0)
-            env->hflags |= HF_HALTED_MASK;
+            env->halted = 1;
         if (smp_cpus > 1) {
             /* XXX: enable it in all cases */
             env->cpuid_features |= CPUID_APIC;
@@ -314,21 +314,15 @@ static void do_info_cpus(void)
                     env->cpu_index);
 #if defined(TARGET_I386)
         term_printf(" pc=0x" TARGET_FMT_lx, env->eip + env->segs[R_CS].base);
-        if (env->hflags & HF_HALTED_MASK)
-            term_printf(" (halted)");
 #elif defined(TARGET_PPC)
         term_printf(" nip=0x" TARGET_FMT_lx, env->nip);
-        if (env->halted)
-            term_printf(" (halted)");
 #elif defined(TARGET_SPARC)
         term_printf(" pc=0x" TARGET_FMT_lx " npc=0x" TARGET_FMT_lx, env->pc, env->npc);
-        if (env->halted)
-            term_printf(" (halted)");
 #elif defined(TARGET_MIPS)
         term_printf(" PC=0x" TARGET_FMT_lx, env->PC[env->current_tc]);
+#endif
         if (env->halted)
             term_printf(" (halted)");
-#endif
         term_printf("\n");
     }
 }
@@ -285,7 +285,6 @@ struct CPUAlphaState {
     jmp_buf jmp_env;
     int user_mode_only; /* user mode only simulation */
     uint32_t hflags;
-    int halted;
     int exception_index;
     int error_code;
@@ -160,7 +160,6 @@ typedef struct CPUARMState {
     int exception_index;
     int interrupt_request;
     int user_mode_only;
-    int halted;
     /* VFP coprocessor state.  */
     struct {
@@ -157,7 +157,6 @@ typedef struct CPUCRISState {
 	int features;
 	int user_mode_only;
-	int halted;
 	jmp_buf jmp_env;
 	CPU_COMMON
@@ -119,7 +119,7 @@
 #define ID_MASK                 0x00200000
 /* hidden flags - used internally by qemu to represent additional cpu
-   states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
+   states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
    using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
    with eflags. */
 /* current cpl */
@@ -144,7 +144,6 @@
 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 #define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
 #define HF_VM_SHIFT         17 /* must be same as eflags */
-#define HF_HALTED_SHIFT     18 /* CPU halted */
 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 #define HF_GIF_SHIFT        20 /* if set CPU takes interrupts */
 #define HF_HIF_SHIFT        21 /* shadow copy of IF_MASK when in SVM */
@@ -166,7 +165,6 @@
 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
-#define HF_HALTED_MASK       (1 << HF_HALTED_SHIFT)
 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 #define HF_GIF_MASK          (1 << HF_GIF_SHIFT)
 #define HF_HIF_MASK          (1 << HF_HIF_SHIFT)
@@ -385,13 +385,13 @@ static inline void regs_to_env(void)
 static inline int cpu_halted(CPUState *env) {
     /* handle exit of HALTED state */
-    if (!(env->hflags & HF_HALTED_MASK))
+    if (!env->halted)
         return 0;
     /* disable halt condition */
     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
          (env->eflags & IF_MASK)) ||
         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
-        env->hflags &= ~HF_HALTED_MASK;
+        env->halted = 0;
         return 0;
     }
     return EXCP_HALTED;
@@ -515,7 +515,7 @@ void cpu_dump_state(CPUState *env, FILE *f,
                     (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
                     (int)(env->a20_mask >> 20) & 1,
                     (env->hflags >> HF_SMM_SHIFT) & 1,
-                    (env->hflags >> HF_HALTED_SHIFT) & 1);
+                    env->halted);
     } else
 #endif
     {
@@ -542,7 +542,7 @@ void cpu_dump_state(CPUState *env, FILE *f,
                     (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
                     (int)(env->a20_mask >> 20) & 1,
                     (env->hflags >> HF_SMM_SHIFT) & 1,
-                    (env->hflags >> HF_HALTED_SHIFT) & 1);
+                    env->halted);
     }
 #ifdef TARGET_X86_64
@@ -4546,7 +4546,7 @@ void helper_hlt(void)
     helper_svm_check_intercept_param(SVM_EXIT_HLT, 0);
     env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
-    env->hflags |= HF_HALTED_MASK;
+    env->halted = 1;
     env->exception_index = EXCP_HLT;
     cpu_loop_exit();
 }
@@ -108,7 +108,6 @@ typedef struct CPUM68KState {
     int exception_index;
     int interrupt_request;
     int user_mode_only;
-    uint32_t halted;
     int pending_vector;
     int pending_level;
@@ -449,8 +449,6 @@ struct CPUMIPSState {
     target_ulong btarget;        /* Jump / branch target               */
     int bcond;                   /* Branch condition (if needed)       */
-    int halted; /* TRUE if the CPU is in suspend state */
-
     int SYNCI_Step; /* Address step size for SYNCI */
     int CCRes; /* Cycle count resolution/divisor */
     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
@@ -586,8 +586,6 @@ struct CPUPPCState {
     CPU_COMMON
-    int halted; /* TRUE if the CPU is in suspend state */
-
     int access_type; /* when a memory exception occurs, the access
                         type is stored here */
@@ -117,7 +117,6 @@ typedef struct CPUSH4State {
     jmp_buf jmp_env;
     int user_mode_only;
     int interrupt_request;
-    int halted;
     int exception_index;
      CPU_COMMON tlb_t utlb[UTLB_SIZE];	/* unified translation table */
     tlb_t itlb[ITLB_SIZE];	/* instruction translation table */
@@ -219,7 +219,6 @@ typedef struct CPUSPARCState {
     int exception_index;
     int interrupt_index;
     int interrupt_request;
-    int halted;
     uint32_t mmu_bm;
     uint32_t mmu_ctpr_mask;
     uint32_t mmu_cxr_mask;