gwj / at91sam9263 · Commits

Commit cc4ba6a9826d94bb46f13856927f7883fd6b9d51

Authored by aurel32
1 parent 105a1f04

SH4: convert floating-point ops to TCG 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5124 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 421 additions and 420 deletions
target-sh4/helper.h
  View file @cc4ba6a
@@ -19,3 +19,27 @@ DEF_HELPER(void, helper_macl, (uint32_t, uint32_t)) @@ -19,3 +19,27 @@ DEF_HELPER(void, helper_macl, (uint32_t, uint32_t))
19 DEF_HELPER(void, helper_macw, (uint32_t, uint32_t)) 19 DEF_HELPER(void, helper_macw, (uint32_t, uint32_t))
20 20
21 DEF_HELPER(void, helper_ld_fpscr, (uint32_t)) 21 DEF_HELPER(void, helper_ld_fpscr, (uint32_t))
  22 +
  23 +DEF_HELPER(uint32_t, helper_fabs_FT, (uint32_t))
  24 +DEF_HELPER(uint64_t, helper_fabs_DT, (uint64_t))
  25 +DEF_HELPER(uint32_t, helper_fadd_FT, (uint32_t, uint32_t))
  26 +DEF_HELPER(uint64_t, helper_fadd_DT, (uint64_t, uint64_t))
  27 +DEF_HELPER(uint64_t, helper_fcnvsd_FT_DT, (uint32_t))
  28 +DEF_HELPER(uint32_t, helper_fcnvds_DT_FT, (uint64_t))
  29 +
  30 +DEF_HELPER(void, helper_fcmp_eq_FT, (uint32_t, uint32_t))
  31 +DEF_HELPER(void, helper_fcmp_eq_DT, (uint64_t, uint64_t))
  32 +DEF_HELPER(void, helper_fcmp_gt_FT, (uint32_t, uint32_t))
  33 +DEF_HELPER(void, helper_fcmp_gt_DT, (uint64_t, uint64_t))
  34 +DEF_HELPER(uint32_t, helper_fdiv_FT, (uint32_t, uint32_t))
  35 +DEF_HELPER(uint64_t, helper_fdiv_DT, (uint64_t, uint64_t))
  36 +DEF_HELPER(uint32_t, helper_float_FT, (uint32_t))
  37 +DEF_HELPER(uint64_t, helper_float_DT, (uint32_t))
  38 +DEF_HELPER(uint32_t, helper_fmul_FT, (uint32_t, uint32_t))
  39 +DEF_HELPER(uint64_t, helper_fmul_DT, (uint64_t, uint64_t))
  40 +DEF_HELPER(uint32_t, helper_fsub_FT, (uint32_t, uint32_t))
  41 +DEF_HELPER(uint64_t, helper_fsub_DT, (uint64_t, uint64_t))
  42 +DEF_HELPER(uint32_t, helper_fsqrt_FT, (uint32_t))
  43 +DEF_HELPER(uint64_t, helper_fsqrt_DT, (uint64_t))
  44 +DEF_HELPER(uint32_t, helper_ftrc_FT, (uint32_t))
  45 +DEF_HELPER(uint32_t, helper_ftrc_DT, (uint64_t))
target-sh4/op.c
  View file @cc4ba6a
@@ -19,238 +19,9 @@ @@ -19,238 +19,9 @@
19 */ 19 */
20 #include "exec.h" 20 #include "exec.h"
21 21
22 -static inline void set_t(void)  
23 -{  
24 - env->sr |= SR_T;  
25 -}  
26 -  
27 -static inline void clr_t(void)  
28 -{  
29 - env->sr &= ~SR_T;  
30 -}  
31 -  
32 -static inline void cond_t(int cond)  
33 -{  
34 - if (cond)  
35 - set_t();  
36 - else  
37 - clr_t();  
38 -}  
39 -  
40 -void OPPROTO op_fmov_frN_FT0(void)  
41 -{  
42 - FT0 = env->fregs[PARAM1];  
43 - RETURN();  
44 -}  
45 -  
46 -void OPPROTO op_fmov_drN_DT0(void)  
47 -{  
48 - CPU_DoubleU d;  
49 -  
50 - d.l.upper = *(uint32_t *)&env->fregs[PARAM1];  
51 - d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];  
52 - DT0 = d.d;  
53 - RETURN();  
54 -}  
55 -  
56 -void OPPROTO op_fmov_frN_FT1(void)  
57 -{  
58 - FT1 = env->fregs[PARAM1];  
59 - RETURN();  
60 -}  
61 -  
62 -void OPPROTO op_fmov_drN_DT1(void)  
63 -{  
64 - CPU_DoubleU d;  
65 -  
66 - d.l.upper = *(uint32_t *)&env->fregs[PARAM1];  
67 - d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];  
68 - DT1 = d.d;  
69 - RETURN();  
70 -}  
71 -  
72 -void OPPROTO op_fmov_FT0_frN(void)  
73 -{  
74 - env->fregs[PARAM1] = FT0;  
75 - RETURN();  
76 -}  
77 -  
78 -void OPPROTO op_fmov_DT0_drN(void)  
79 -{  
80 - CPU_DoubleU d;  
81 -  
82 - d.d = DT0;  
83 - *(uint32_t *)&env->fregs[PARAM1] = d.l.upper;  
84 - *(uint32_t *)&env->fregs[PARAM1 + 1] = d.l.lower;  
85 - RETURN();  
86 -}  
87 -  
88 -void OPPROTO op_fadd_FT(void)  
89 -{  
90 - FT0 = float32_add(FT0, FT1, &env->fp_status);  
91 - RETURN();  
92 -}  
93 -  
94 -void OPPROTO op_fadd_DT(void)  
95 -{  
96 - DT0 = float64_add(DT0, DT1, &env->fp_status);  
97 - RETURN();  
98 -}  
99 -  
100 -void OPPROTO op_fsub_FT(void)  
101 -{  
102 - FT0 = float32_sub(FT0, FT1, &env->fp_status);  
103 - RETURN();  
104 -}  
105 -  
106 -void OPPROTO op_fsub_DT(void)  
107 -{  
108 - DT0 = float64_sub(DT0, DT1, &env->fp_status);  
109 - RETURN();  
110 -}  
111 -  
112 -void OPPROTO op_fmul_FT(void)  
113 -{  
114 - FT0 = float32_mul(FT0, FT1, &env->fp_status);  
115 - RETURN();  
116 -}  
117 -  
118 -void OPPROTO op_fmul_DT(void)  
119 -{  
120 - DT0 = float64_mul(DT0, DT1, &env->fp_status);  
121 - RETURN();  
122 -}  
123 -  
124 -void OPPROTO op_fdiv_FT(void)  
125 -{  
126 - FT0 = float32_div(FT0, FT1, &env->fp_status);  
127 - RETURN();  
128 -}  
129 -  
130 -void OPPROTO op_fdiv_DT(void)  
131 -{  
132 - DT0 = float64_div(DT0, DT1, &env->fp_status);  
133 - RETURN();  
134 -}  
135 -  
136 -void OPPROTO op_fcmp_eq_FT(void)  
137 -{  
138 - cond_t(float32_compare(FT0, FT1, &env->fp_status) == 0);  
139 - RETURN();  
140 -}  
141 -  
142 -void OPPROTO op_fcmp_eq_DT(void)  
143 -{  
144 - cond_t(float64_compare(DT0, DT1, &env->fp_status) == 0);  
145 - RETURN();  
146 -}  
147 -  
148 -void OPPROTO op_fcmp_gt_FT(void)  
149 -{  
150 - cond_t(float32_compare(FT0, FT1, &env->fp_status) == 1);  
151 - RETURN();  
152 -}  
153 -  
154 -void OPPROTO op_fcmp_gt_DT(void)  
155 -{  
156 - cond_t(float64_compare(DT0, DT1, &env->fp_status) == 1);  
157 - RETURN();  
158 -}  
159 -  
160 -void OPPROTO op_float_FT(void)  
161 -{  
162 - FT0 = int32_to_float32(env->fpul, &env->fp_status);  
163 - RETURN();  
164 -}  
165 -  
166 -void OPPROTO op_float_DT(void)  
167 -{  
168 - DT0 = int32_to_float64(env->fpul, &env->fp_status);  
169 - RETURN();  
170 -}  
171 -  
172 -void OPPROTO op_ftrc_FT(void)  
173 -{  
174 - env->fpul = float32_to_int32_round_to_zero(FT0, &env->fp_status);  
175 - RETURN();  
176 -}  
177 -  
178 -void OPPROTO op_ftrc_DT(void)  
179 -{  
180 - env->fpul = float64_to_int32_round_to_zero(DT0, &env->fp_status);  
181 - RETURN();  
182 -}  
183 -  
184 void OPPROTO op_fneg_frN(void) 22 void OPPROTO op_fneg_frN(void)
185 { 23 {
186 env->fregs[PARAM1] = float32_chs(env->fregs[PARAM1]); 24 env->fregs[PARAM1] = float32_chs(env->fregs[PARAM1]);
187 RETURN(); 25 RETURN();
188 } 26 }
189 27
190 -void OPPROTO op_fabs_FT(void)  
191 -{  
192 - FT0 = float32_abs(FT0);  
193 - RETURN();  
194 -}  
195 -  
196 -void OPPROTO op_fabs_DT(void)  
197 -{  
198 - DT0 = float64_abs(DT0);  
199 - RETURN();  
200 -}  
201 -  
202 -void OPPROTO op_fcnvsd_FT_DT(void)  
203 -{  
204 - DT0 = float32_to_float64(FT0, &env->fp_status);  
205 - RETURN();  
206 -}  
207 -  
208 -void OPPROTO op_fcnvds_DT_FT(void)  
209 -{  
210 - FT0 = float64_to_float32(DT0, &env->fp_status);  
211 - RETURN();  
212 -}  
213 -  
214 -void OPPROTO op_fsqrt_FT(void)  
215 -{  
216 - FT0 = float32_sqrt(FT0, &env->fp_status);  
217 - RETURN();  
218 -}  
219 -  
220 -void OPPROTO op_fsqrt_DT(void)  
221 -{  
222 - DT0 = float64_sqrt(DT0, &env->fp_status);  
223 - RETURN();  
224 -}  
225 -  
226 -void OPPROTO op_fmov_T0_frN(void)  
227 -{  
228 - *(uint32_t *)&env->fregs[PARAM1] = T0;  
229 - RETURN();  
230 -}  
231 -  
232 -void OPPROTO op_movl_fpul_FT0(void)  
233 -{  
234 - FT0 = *(float32 *)&env->fpul;  
235 - RETURN();  
236 -}  
237 -  
238 -void OPPROTO op_movl_FT0_fpul(void)  
239 -{  
240 - *(float32 *)&env->fpul = FT0;  
241 - RETURN();  
242 -}  
243 -  
244 -/* Load and store */  
245 -#define MEMSUFFIX _raw  
246 -#include "op_mem.c"  
247 -#undef MEMSUFFIX  
248 -#if !defined(CONFIG_USER_ONLY)  
249 -#define MEMSUFFIX _user  
250 -#include "op_mem.c"  
251 -#undef MEMSUFFIX  
252 -  
253 -#define MEMSUFFIX _kernel  
254 -#include "op_mem.c"  
255 -#undef MEMSUFFIX  
256 -#endif  
target-sh4/op_helper.c
  View file @cc4ba6a
@@ -366,6 +366,16 @@ uint32_t helper_subv(uint32_t arg0, uint32_t arg1) @@ -366,6 +366,16 @@ uint32_t helper_subv(uint32_t arg0, uint32_t arg1)
366 return arg1; 366 return arg1;
367 } 367 }
368 368
  369 +static inline void set_t(void)
  370 +{
  371 + env->sr |= SR_T;
  372 +}
  373 +
  374 +static inline void clr_t(void)
  375 +{
  376 + env->sr &= ~SR_T;
  377 +}
  378 +
369 void helper_ld_fpscr(uint32_t val) 379 void helper_ld_fpscr(uint32_t val)
370 { 380 {
371 env->fpscr = val & 0x003fffff; 381 env->fpscr = val & 0x003fffff;
@@ -374,3 +384,141 @@ void helper_ld_fpscr(uint32_t val) @@ -374,3 +384,141 @@ void helper_ld_fpscr(uint32_t val)
374 else 384 else
375 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); 385 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
376 } 386 }
  387 +
  388 +uint32_t helper_fabs_FT(uint32_t t0)
  389 +{
  390 + float32 ret = float32_abs(*(float32*)&t0);
  391 + return *(uint32_t*)(&ret);
  392 +}
  393 +
  394 +uint64_t helper_fabs_DT(uint64_t t0)
  395 +{
  396 + float64 ret = float64_abs(*(float64*)&t0);
  397 + return *(uint64_t*)(&ret);
  398 +}
  399 +
  400 +uint32_t helper_fadd_FT(uint32_t t0, uint32_t t1)
  401 +{
  402 + float32 ret = float32_add(*(float32*)&t0, *(float32*)&t1, &env->fp_status);
  403 + return *(uint32_t*)(&ret);
  404 +}
  405 +
  406 +uint64_t helper_fadd_DT(uint64_t t0, uint64_t t1)
  407 +{
  408 + float64 ret = float64_add(*(float64*)&t0, *(float64*)&t1, &env->fp_status);
  409 + return *(uint64_t*)(&ret);
  410 +}
  411 +
  412 +void helper_fcmp_eq_FT(uint32_t t0, uint32_t t1)
  413 +{
  414 + if (float32_compare(*(float32*)&t0, *(float32*)&t1, &env->fp_status) == 0)
  415 + set_t();
  416 + else
  417 + clr_t();
  418 +}
  419 +
  420 +void helper_fcmp_eq_DT(uint64_t t0, uint64_t t1)
  421 +{
  422 + if (float64_compare(*(float64*)&t0, *(float64*)&t1, &env->fp_status) == 0)
  423 + set_t();
  424 + else
  425 + clr_t();
  426 +}
  427 +
  428 +void helper_fcmp_gt_FT(uint32_t t0, uint32_t t1)
  429 +{
  430 + if (float32_compare(*(float32*)&t0, *(float32*)&t1, &env->fp_status) == 1)
  431 + set_t();
  432 + else
  433 + clr_t();
  434 +}
  435 +
  436 +void helper_fcmp_gt_DT(uint64_t t0, uint64_t t1)
  437 +{
  438 + if (float64_compare(*(float64*)&t0, *(float64*)&t1, &env->fp_status) == 1)
  439 + set_t();
  440 + else
  441 + clr_t();
  442 +}
  443 +
  444 +uint64_t helper_fcnvsd_FT_DT(uint32_t t0)
  445 +{
  446 + float64 ret = float32_to_float64(*(float32*)&t0, &env->fp_status);
  447 + return *(uint64_t*)(&ret);
  448 +}
  449 +
  450 +uint32_t helper_fcnvds_DT_FT(uint64_t t0)
  451 +{
  452 + float32 ret = float64_to_float32(*(float64*)&t0, &env->fp_status);
  453 + return *(uint32_t*)(&ret);
  454 +}
  455 +
  456 +uint32_t helper_fdiv_FT(uint32_t t0, uint32_t t1)
  457 +{
  458 + float32 ret = float32_div(*(float32*)&t0, *(float32*)&t1, &env->fp_status);
  459 + return *(uint32_t*)(&ret);
  460 +}
  461 +
  462 +uint64_t helper_fdiv_DT(uint64_t t0, uint64_t t1)
  463 +{
  464 + float64 ret = float64_div(*(float64*)&t0, *(float64*)&t1, &env->fp_status);
  465 + return *(uint64_t*)(&ret);
  466 +}
  467 +
  468 +uint32_t helper_float_FT(uint32_t t0)
  469 +{
  470 + float32 ret = int32_to_float32(t0, &env->fp_status);
  471 + return *(uint32_t*)(&ret);
  472 +}
  473 +
  474 +uint64_t helper_float_DT(uint32_t t0)
  475 +{
  476 + float64 ret = int32_to_float64(t0, &env->fp_status);
  477 + return *(uint64_t*)(&ret);
  478 +}
  479 +
  480 +uint32_t helper_fmul_FT(uint32_t t0, uint32_t t1)
  481 +{
  482 + float32 ret = float32_mul(*(float32*)&t0, *(float32*)&t1, &env->fp_status);
  483 + return *(uint32_t*)(&ret);
  484 +}
  485 +
  486 +uint64_t helper_fmul_DT(uint64_t t0, uint64_t t1)
  487 +{
  488 + float64 ret = float64_mul(*(float64*)&t0, *(float64*)&t1, &env->fp_status);
  489 + return *(uint64_t*)(&ret);
  490 +}
  491 +
  492 +uint32_t helper_fsqrt_FT(uint32_t t0)
  493 +{
  494 + float32 ret = float32_sqrt(*(float32*)&t0, &env->fp_status);
  495 + return *(uint32_t*)(&ret);
  496 +}
  497 +
  498 +uint64_t helper_fsqrt_DT(uint64_t t0)
  499 +{
  500 + float64 ret = float64_sqrt(*(float64*)&t0, &env->fp_status);
  501 + return *(uint64_t*)(&ret);
  502 +}
  503 +
  504 +uint32_t helper_fsub_FT(uint32_t t0, uint32_t t1)
  505 +{
  506 + float32 ret = float32_sub(*(float32*)&t0, *(float32*)&t1, &env->fp_status);
  507 + return *(uint32_t*)(&ret);
  508 +}
  509 +
  510 +uint64_t helper_fsub_DT(uint64_t t0, uint64_t t1)
  511 +{
  512 + float64 ret = float64_sub(*(float64*)&t0, *(float64*)&t1, &env->fp_status);
  513 + return *(uint64_t*)(&ret);
  514 +}
  515 +
  516 +uint32_t helper_ftrc_FT(uint32_t t0)
  517 +{
  518 + return float32_to_int32_round_to_zero(*(float32*)&t0, &env->fp_status);
  519 +}
  520 +
  521 +uint32_t helper_ftrc_DT(uint64_t t0)
  522 +{
  523 + return float64_to_int32_round_to_zero(*(float64*)&t0, &env->fp_status);
  524 +}
target-sh4/op_mem.c deleted 100644 → 0
  View file @105a1f0
1 -/*  
2 - * SH4 emulation  
3 - *  
4 - * Copyright (c) 2005 Samuel Tardieu  
5 - *  
6 - * This library is free software; you can redistribute it and/or  
7 - * modify it under the terms of the GNU Lesser General Public  
8 - * License as published by the Free Software Foundation; either  
9 - * version 2 of the License, or (at your option) any later version.  
10 - *  
11 - * This library is distributed in the hope that it will be useful,  
12 - * but WITHOUT ANY WARRANTY; without even the implied warranty of  
13 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU  
14 - * Lesser General Public License for more details.  
15 - *  
16 - * You should have received a copy of the GNU Lesser General Public  
17 - * License along with this library; if not, write to the Free Software  
18 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  
19 - */  
20 -void glue(op_ldfl_T0_FT0, MEMSUFFIX) (void) {  
21 - FT0 = glue(ldfl, MEMSUFFIX) (T0);  
22 - RETURN();  
23 -}  
24 -  
25 -void glue(op_stfl_FT0_T1, MEMSUFFIX) (void) {  
26 - glue(stfl, MEMSUFFIX) (T1, FT0);  
27 - RETURN();  
28 -}  
29 -  
30 -void glue(op_ldfq_T0_DT0, MEMSUFFIX) (void) {  
31 - DT0 = glue(ldfq, MEMSUFFIX) (T0);  
32 - RETURN();  
33 -}  
34 -  
35 -void glue(op_stfq_DT0_T1, MEMSUFFIX) (void) {  
36 - glue(stfq, MEMSUFFIX) (T1, DT0);  
37 - RETURN();  
38 -}  
target-sh4/translate.c
  View file @cc4ba6a
@@ -137,37 +137,6 @@ static void sh4_translate_init(void) @@ -137,37 +137,6 @@ static void sh4_translate_init(void)
137 done_init = 1; 137 done_init = 1;
138 } 138 }
139 139
140 -#ifdef CONFIG_USER_ONLY  
141 -  
142 -#define GEN_OP_LD(width, reg) \  
143 - void gen_op_ld##width##_T0_##reg (DisasContext *ctx) { \  
144 - gen_op_ld##width##_T0_##reg##_raw(); \  
145 - }  
146 -#define GEN_OP_ST(width, reg) \  
147 - void gen_op_st##width##_##reg##_T1 (DisasContext *ctx) { \  
148 - gen_op_st##width##_##reg##_T1_raw(); \  
149 - }  
150 -  
151 -#else  
152 -  
153 -#define GEN_OP_LD(width, reg) \  
154 - void gen_op_ld##width##_T0_##reg (DisasContext *ctx) { \  
155 - if (ctx->memidx) gen_op_ld##width##_T0_##reg##_kernel(); \  
156 - else gen_op_ld##width##_T0_##reg##_user();\  
157 - }  
158 -#define GEN_OP_ST(width, reg) \  
159 - void gen_op_st##width##_##reg##_T1 (DisasContext *ctx) { \  
160 - if (ctx->memidx) gen_op_st##width##_##reg##_T1_kernel(); \  
161 - else gen_op_st##width##_##reg##_T1_user();\  
162 - }  
163 -  
164 -#endif  
165 -  
166 -GEN_OP_LD(fl, FT0)  
167 -GEN_OP_ST(fl, FT0)  
168 -GEN_OP_LD(fq, DT0)  
169 -GEN_OP_ST(fq, DT0)  
170 -  
171 void cpu_dump_state(CPUState * env, FILE * f, 140 void cpu_dump_state(CPUState * env, FILE * f,
172 int (*cpu_fprintf) (FILE * f, const char *fmt, ...), 141 int (*cpu_fprintf) (FILE * f, const char *fmt, ...),
173 int flags) 142 int flags)
@@ -361,6 +330,44 @@ static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1) @@ -361,6 +330,44 @@ static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1)
361 tcg_temp_free(tmp); 330 tcg_temp_free(tmp);
362 } 331 }
363 332
  333 +
  334 +static inline void gen_load_fpr32(TCGv t, int reg)
  335 +{
  336 + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
  337 +}
  338 +
  339 +static inline void gen_load_fpr64(TCGv t, int reg)
  340 +{
  341 + TCGv tmp1 = tcg_temp_new(TCG_TYPE_I32);
  342 + TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);
  343 +
  344 + tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg]));
  345 + tcg_gen_extu_i32_i64(t, tmp1);
  346 + tcg_gen_shli_i64(t, t, 32);
  347 + tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg + 1]));
  348 + tcg_gen_extu_i32_i64(tmp2, tmp1);
  349 + tcg_temp_free(tmp1);
  350 + tcg_gen_or_i64(t, t, tmp2);
  351 + tcg_temp_free(tmp2);
  352 +}
  353 +
  354 +static inline void gen_store_fpr32(TCGv t, int reg)
  355 +{
  356 + tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
  357 +}
  358 +
  359 +static inline void gen_store_fpr64 (TCGv t, int reg)
  360 +{
  361 + TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
  362 +
  363 + tcg_gen_trunc_i64_i32(tmp, t);
  364 + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg + 1]));
  365 + tcg_gen_shri_i64(t, t, 32);
  366 + tcg_gen_trunc_i64_i32(tmp, t);
  367 + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg]));
  368 + tcg_temp_free(tmp);
  369 +}
  370 +
364 #define B3_0 (ctx->opcode & 0xf) 371 #define B3_0 (ctx->opcode & 0xf)
365 #define B6_4 ((ctx->opcode >> 4) & 0x7) 372 #define B6_4 ((ctx->opcode >> 4) & 0x7)
366 #define B7_4 ((ctx->opcode >> 4) & 0xf) 373 #define B7_4 ((ctx->opcode >> 4) & 0xf)
@@ -913,88 +920,115 @@ void _decode_opc(DisasContext * ctx) @@ -913,88 +920,115 @@ void _decode_opc(DisasContext * ctx)
913 return; 920 return;
914 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ 921 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
915 if (ctx->fpscr & FPSCR_SZ) { 922 if (ctx->fpscr & FPSCR_SZ) {
916 - gen_op_fmov_drN_DT0(XREG(B7_4));  
917 - gen_op_fmov_DT0_drN(XREG(B11_8)); 923 + TCGv fp = tcg_temp_new(TCG_TYPE_I64);
  924 + gen_load_fpr64(fp, XREG(B7_4));
  925 + gen_store_fpr64(fp, XREG(B11_8));
  926 + tcg_temp_free(fp);
918 } else { 927 } else {
919 - gen_op_fmov_frN_FT0(FREG(B7_4));  
920 - gen_op_fmov_FT0_frN(FREG(B11_8)); 928 + TCGv fp = tcg_temp_new(TCG_TYPE_I32);
  929 + gen_load_fpr32(fp, FREG(B7_4));
  930 + gen_store_fpr32(fp, FREG(B11_8));
  931 + tcg_temp_free(fp);
921 } 932 }
922 return; 933 return;
923 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ 934 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
924 if (ctx->fpscr & FPSCR_SZ) { 935 if (ctx->fpscr & FPSCR_SZ) {
925 - gen_op_fmov_drN_DT0(XREG(B7_4));  
926 - tcg_gen_mov_i32(cpu_T[1], REG(B11_8));  
927 - gen_op_stfq_DT0_T1(ctx); 936 + TCGv fp = tcg_temp_new(TCG_TYPE_I64);
  937 + gen_load_fpr64(fp, XREG(B7_4));
  938 + tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
  939 + tcg_temp_free(fp);
928 } else { 940 } else {
929 - gen_op_fmov_frN_FT0(FREG(B7_4));  
930 - tcg_gen_mov_i32(cpu_T[1], REG(B11_8));  
931 - gen_op_stfl_FT0_T1(ctx); 941 + TCGv fp = tcg_temp_new(TCG_TYPE_I32);
  942 + gen_load_fpr32(fp, FREG(B7_4));
  943 + tcg_gen_qemu_st32(fp, REG(B11_8), ctx->memidx);
  944 + tcg_temp_free(fp);
932 } 945 }
933 return; 946 return;
934 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ 947 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
935 if (ctx->fpscr & FPSCR_SZ) { 948 if (ctx->fpscr & FPSCR_SZ) {
936 - tcg_gen_mov_i32(cpu_T[0], REG(B7_4));  
937 - gen_op_ldfq_T0_DT0(ctx);  
938 - gen_op_fmov_DT0_drN(XREG(B11_8)); 949 + TCGv fp = tcg_temp_new(TCG_TYPE_I64);
  950 + tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
  951 + gen_store_fpr64(fp, XREG(B11_8));
  952 + tcg_temp_free(fp);
939 } else { 953 } else {
940 - tcg_gen_mov_i32(cpu_T[0], REG(B7_4));  
941 - gen_op_ldfl_T0_FT0(ctx);  
942 - gen_op_fmov_FT0_frN(FREG(B11_8)); 954 + TCGv fp = tcg_temp_new(TCG_TYPE_I32);
  955 + tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
  956 + gen_store_fpr32(fp, FREG(B11_8));
  957 + tcg_temp_free(fp);
943 } 958 }
944 return; 959 return;
945 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ 960 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
946 if (ctx->fpscr & FPSCR_SZ) { 961 if (ctx->fpscr & FPSCR_SZ) {
947 - tcg_gen_mov_i32(cpu_T[0], REG(B7_4));  
948 - gen_op_ldfq_T0_DT0(ctx);  
949 - gen_op_fmov_DT0_drN(XREG(B11_8));  
950 - tcg_gen_addi_i32(REG(B7_4),  
951 - REG(B7_4), 8); 962 + TCGv fp = tcg_temp_new(TCG_TYPE_I64);
  963 + tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
  964 + gen_store_fpr64(fp, XREG(B11_8));
  965 + tcg_temp_free(fp);
  966 + tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
952 } else { 967 } else {
953 - tcg_gen_mov_i32(cpu_T[0], REG(B7_4));  
954 - gen_op_ldfl_T0_FT0(ctx);  
955 - gen_op_fmov_FT0_frN(FREG(B11_8));  
956 - tcg_gen_addi_i32(REG(B7_4),  
957 - REG(B7_4), 4); 968 + TCGv fp = tcg_temp_new(TCG_TYPE_I32);
  969 + tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
  970 + gen_store_fpr32(fp, FREG(B11_8));
  971 + tcg_temp_free(fp);
  972 + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
958 } 973 }
959 return; 974 return;
960 case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ 975 case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
961 if (ctx->fpscr & FPSCR_SZ) { 976 if (ctx->fpscr & FPSCR_SZ) {
962 - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);  
963 - gen_op_fmov_drN_DT0(XREG(B7_4));  
964 - tcg_gen_mov_i32(cpu_T[1], REG(B11_8));  
965 - tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 8);  
966 - gen_op_stfq_DT0_T1(ctx); 977 + TCGv addr, fp;
  978 + addr = tcg_temp_new(TCG_TYPE_I32);
  979 + tcg_gen_subi_i32(addr, REG(B11_8), 8);
  980 + fp = tcg_temp_new(TCG_TYPE_I64);
  981 + gen_load_fpr64(fp, XREG(B7_4));
  982 + tcg_gen_qemu_st64(fp, addr, ctx->memidx);
  983 + tcg_temp_free(fp);
  984 + tcg_temp_free(addr);
967 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8); 985 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
968 } else { 986 } else {
969 - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);  
970 - gen_op_fmov_frN_FT0(FREG(B7_4));  
971 - tcg_gen_mov_i32(cpu_T[1], REG(B11_8));  
972 - tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);  
973 - gen_op_stfl_FT0_T1(ctx); 987 + TCGv addr, fp;
  988 + addr = tcg_temp_new(TCG_TYPE_I32);
  989 + tcg_gen_subi_i32(addr, REG(B11_8), 4);
  990 + fp = tcg_temp_new(TCG_TYPE_I32);
  991 + gen_load_fpr32(fp, FREG(B7_4));
  992 + tcg_gen_qemu_st32(fp, addr, ctx->memidx);
  993 + tcg_temp_free(fp);
  994 + tcg_temp_free(addr);
974 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); 995 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
975 } 996 }
976 return; 997 return;
977 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ 998 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
978 - tcg_gen_add_i32(cpu_T[0], REG(B7_4), REG(0));  
979 - if (ctx->fpscr & FPSCR_SZ) {  
980 - gen_op_ldfq_T0_DT0(ctx);  
981 - gen_op_fmov_DT0_drN(XREG(B11_8));  
982 - } else {  
983 - gen_op_ldfl_T0_FT0(ctx);  
984 - gen_op_fmov_FT0_frN(FREG(B11_8)); 999 + {
  1000 + TCGv addr = tcg_temp_new(TCG_TYPE_I32);
  1001 + tcg_gen_add_i32(addr, REG(B7_4), REG(0));
  1002 + if (ctx->fpscr & FPSCR_SZ) {
  1003 + TCGv fp = tcg_temp_new(TCG_TYPE_I64);
  1004 + tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
  1005 + gen_store_fpr64(fp, XREG(B11_8));
  1006 + tcg_temp_free(fp);
  1007 + } else {
  1008 + TCGv fp = tcg_temp_new(TCG_TYPE_I32);
  1009 + tcg_gen_qemu_ld32u(fp, addr, ctx->memidx);
  1010 + gen_store_fpr32(fp, FREG(B11_8));
  1011 + tcg_temp_free(fp);
  1012 + }
  1013 + tcg_temp_free(addr);
985 } 1014 }
986 return; 1015 return;
987 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ 1016 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
988 - if (ctx->fpscr & FPSCR_SZ) {  
989 - gen_op_fmov_drN_DT0(XREG(B7_4));  
990 - tcg_gen_mov_i32(cpu_T[1], REG(B11_8));  
991 - tcg_gen_add_i32(cpu_T[1], cpu_T[1], REG(0));  
992 - gen_op_stfq_DT0_T1(ctx);  
993 - } else {  
994 - gen_op_fmov_frN_FT0(FREG(B7_4));  
995 - tcg_gen_mov_i32(cpu_T[1], REG(B11_8));  
996 - tcg_gen_add_i32(cpu_T[1], cpu_T[1], REG(0));  
997 - gen_op_stfl_FT0_T1(ctx); 1017 + {
  1018 + TCGv addr = tcg_temp_new(TCG_TYPE_I32);
  1019 + tcg_gen_add_i32(addr, REG(B11_8), REG(0));
  1020 + if (ctx->fpscr & FPSCR_SZ) {
  1021 + TCGv fp = tcg_temp_new(TCG_TYPE_I64);
  1022 + gen_load_fpr64(fp, XREG(B7_4));
  1023 + tcg_gen_qemu_st64(fp, addr, ctx->memidx);
  1024 + tcg_temp_free(fp);
  1025 + } else {
  1026 + TCGv fp = tcg_temp_new(TCG_TYPE_I32);
  1027 + gen_load_fpr32(fp, FREG(B7_4));
  1028 + tcg_gen_qemu_st32(fp, addr, ctx->memidx);
  1029 + tcg_temp_free(fp);
  1030 + }
  1031 + tcg_temp_free(addr);
998 } 1032 }
999 return; 1033 return;
1000 case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ 1034 case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
@@ -1003,43 +1037,71 @@ void _decode_opc(DisasContext * ctx) @@ -1003,43 +1037,71 @@ void _decode_opc(DisasContext * ctx)
1003 case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ 1037 case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1004 case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ 1038 case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1005 case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ 1039 case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1006 - if (ctx->fpscr & FPSCR_PR) {  
1007 - if (ctx->opcode & 0x0110)  
1008 - break; /* illegal instruction */  
1009 - gen_op_fmov_drN_DT1(DREG(B7_4));  
1010 - gen_op_fmov_drN_DT0(DREG(B11_8));  
1011 - }  
1012 - else {  
1013 - gen_op_fmov_frN_FT1(FREG(B7_4));  
1014 - gen_op_fmov_frN_FT0(FREG(B11_8));  
1015 - } 1040 + {
  1041 + TCGv fp0, fp1;
  1042 +
  1043 + if (ctx->fpscr & FPSCR_PR) {
  1044 + if (ctx->opcode & 0x0110)
  1045 + break; /* illegal instruction */
  1046 + fp0 = tcg_temp_new(TCG_TYPE_I64);
  1047 + fp1 = tcg_temp_new(TCG_TYPE_I64);
  1048 + gen_load_fpr64(fp0, DREG(B11_8));
  1049 + gen_load_fpr64(fp1, DREG(B7_4));
  1050 + }
  1051 + else {
  1052 + fp0 = tcg_temp_new(TCG_TYPE_I32);
  1053 + fp1 = tcg_temp_new(TCG_TYPE_I32);
  1054 + gen_load_fpr32(fp0, FREG(B11_8));
  1055 + gen_load_fpr32(fp1, FREG(B7_4));
  1056 + }
1016 1057
1017 - switch (ctx->opcode & 0xf00f) {  
1018 - case 0xf000: /* fadd Rm,Rn */  
1019 - ctx->fpscr & FPSCR_PR ? gen_op_fadd_DT() : gen_op_fadd_FT();  
1020 - break;  
1021 - case 0xf001: /* fsub Rm,Rn */  
1022 - ctx->fpscr & FPSCR_PR ? gen_op_fsub_DT() : gen_op_fsub_FT();  
1023 - break;  
1024 - case 0xf002: /* fmul Rm,Rn */  
1025 - ctx->fpscr & FPSCR_PR ? gen_op_fmul_DT() : gen_op_fmul_FT();  
1026 - break;  
1027 - case 0xf003: /* fdiv Rm,Rn */  
1028 - ctx->fpscr & FPSCR_PR ? gen_op_fdiv_DT() : gen_op_fdiv_FT();  
1029 - break;  
1030 - case 0xf004: /* fcmp/eq Rm,Rn */  
1031 - ctx->fpscr & FPSCR_PR ? gen_op_fcmp_eq_DT() : gen_op_fcmp_eq_FT();  
1032 - return;  
1033 - case 0xf005: /* fcmp/gt Rm,Rn */  
1034 - ctx->fpscr & FPSCR_PR ? gen_op_fcmp_gt_DT() : gen_op_fcmp_gt_FT();  
1035 - return;  
1036 - } 1058 + switch (ctx->opcode & 0xf00f) {
  1059 + case 0xf000: /* fadd Rm,Rn */
  1060 + if (ctx->fpscr & FPSCR_PR)
  1061 + tcg_gen_helper_1_2(helper_fadd_DT, fp0, fp0, fp1);
  1062 + else
  1063 + tcg_gen_helper_1_2(helper_fadd_FT, fp0, fp0, fp1);
  1064 + break;
  1065 + case 0xf001: /* fsub Rm,Rn */
  1066 + if (ctx->fpscr & FPSCR_PR)
  1067 + tcg_gen_helper_1_2(helper_fsub_DT, fp0, fp0, fp1);
  1068 + else
  1069 + tcg_gen_helper_1_2(helper_fsub_FT, fp0, fp0, fp1);
  1070 + break;
  1071 + case 0xf002: /* fmul Rm,Rn */
  1072 + if (ctx->fpscr & FPSCR_PR)
  1073 + tcg_gen_helper_1_2(helper_fmul_DT, fp0, fp0, fp1);
  1074 + else
  1075 + tcg_gen_helper_1_2(helper_fmul_FT, fp0, fp0, fp1);
  1076 + break;
  1077 + case 0xf003: /* fdiv Rm,Rn */
  1078 + if (ctx->fpscr & FPSCR_PR)
  1079 + tcg_gen_helper_1_2(helper_fdiv_DT, fp0, fp0, fp1);
  1080 + else
  1081 + tcg_gen_helper_1_2(helper_fdiv_FT, fp0, fp0, fp1);
  1082 + break;
  1083 + case 0xf004: /* fcmp/eq Rm,Rn */
  1084 + if (ctx->fpscr & FPSCR_PR)
  1085 + tcg_gen_helper_0_2(helper_fcmp_eq_DT, fp0, fp1);
  1086 + else
  1087 + tcg_gen_helper_0_2(helper_fcmp_eq_FT, fp0, fp1);
  1088 + return;
  1089 + case 0xf005: /* fcmp/gt Rm,Rn */
  1090 + if (ctx->fpscr & FPSCR_PR)
  1091 + tcg_gen_helper_0_2(helper_fcmp_gt_DT, fp0, fp1);
  1092 + else
  1093 + tcg_gen_helper_0_2(helper_fcmp_gt_FT, fp0, fp1);
  1094 + return;
  1095 + }
1037 1096
1038 - if (ctx->fpscr & FPSCR_PR) {  
1039 - gen_op_fmov_DT0_drN(DREG(B11_8));  
1040 - }  
1041 - else {  
1042 - gen_op_fmov_FT0_frN(FREG(B11_8)); 1097 + if (ctx->fpscr & FPSCR_PR) {
  1098 + gen_store_fpr64(fp0, DREG(B11_8));
  1099 + }
  1100 + else {
  1101 + gen_store_fpr32(fp0, FREG(B11_8));
  1102 + }
  1103 + tcg_temp_free(fp1);
  1104 + tcg_temp_free(fp0);
1043 } 1105 }
1044 return; 1106 return;
1045 } 1107 }
@@ -1481,35 +1543,53 @@ void _decode_opc(DisasContext * ctx) @@ -1481,35 +1543,53 @@ void _decode_opc(DisasContext * ctx)
1481 } 1543 }
1482 return; 1544 return;
1483 case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ 1545 case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
1484 - gen_op_movl_fpul_FT0();  
1485 - gen_op_fmov_FT0_frN(FREG(B11_8)); 1546 + {
  1547 + TCGv fp = tcg_temp_new(TCG_TYPE_I32);
  1548 + tcg_gen_mov_i32(fp, cpu_fpul);
  1549 + gen_store_fpr32(fp, FREG(B11_8));
  1550 + tcg_temp_free(fp);
  1551 + }
1486 return; 1552 return;
1487 case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ 1553 case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
1488 - gen_op_fmov_frN_FT0(FREG(B11_8));  
1489 - gen_op_movl_FT0_fpul(); 1554 + {
  1555 + TCGv fp = tcg_temp_new(TCG_TYPE_I32);
  1556 + gen_load_fpr32(fp, FREG(B11_8));
  1557 + tcg_gen_mov_i32(cpu_fpul, fp);
  1558 + tcg_temp_free(fp);
  1559 + }
1490 return; 1560 return;
1491 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ 1561 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
1492 if (ctx->fpscr & FPSCR_PR) { 1562 if (ctx->fpscr & FPSCR_PR) {
  1563 + TCGv fp;
1493 if (ctx->opcode & 0x0100) 1564 if (ctx->opcode & 0x0100)
1494 break; /* illegal instruction */ 1565 break; /* illegal instruction */
1495 - gen_op_float_DT();  
1496 - gen_op_fmov_DT0_drN(DREG(B11_8)); 1566 + fp = tcg_temp_new(TCG_TYPE_I64);
  1567 + tcg_gen_helper_1_1(helper_float_DT, fp, cpu_fpul);
  1568 + gen_store_fpr64(fp, DREG(B11_8));
  1569 + tcg_temp_free(fp);
1497 } 1570 }
1498 else { 1571 else {
1499 - gen_op_float_FT();  
1500 - gen_op_fmov_FT0_frN(FREG(B11_8)); 1572 + TCGv fp = tcg_temp_new(TCG_TYPE_I32);
  1573 + tcg_gen_helper_1_1(helper_float_FT, fp, cpu_fpul);
  1574 + gen_store_fpr32(fp, FREG(B11_8));
  1575 + tcg_temp_free(fp);
1501 } 1576 }
1502 return; 1577 return;
1503 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ 1578 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1504 if (ctx->fpscr & FPSCR_PR) { 1579 if (ctx->fpscr & FPSCR_PR) {
  1580 + TCGv fp;
1505 if (ctx->opcode & 0x0100) 1581 if (ctx->opcode & 0x0100)
1506 break; /* illegal instruction */ 1582 break; /* illegal instruction */
1507 - gen_op_fmov_drN_DT0(DREG(B11_8));  
1508 - gen_op_ftrc_DT(); 1583 + fp = tcg_temp_new(TCG_TYPE_I64);
  1584 + gen_load_fpr64(fp, DREG(B11_8));
  1585 + tcg_gen_helper_1_1(helper_ftrc_DT, cpu_fpul, fp);
  1586 + tcg_temp_free(fp);
1509 } 1587 }
1510 else { 1588 else {
1511 - gen_op_fmov_frN_FT0(FREG(B11_8));  
1512 - gen_op_ftrc_FT(); 1589 + TCGv fp = tcg_temp_new(TCG_TYPE_I32);
  1590 + gen_load_fpr32(fp, FREG(B11_8));
  1591 + tcg_gen_helper_1_1(helper_ftrc_FT, cpu_fpul, fp);
  1592 + tcg_temp_free(fp);
1513 } 1593 }
1514 return; 1594 return;
1515 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ 1595 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
@@ -1519,53 +1599,69 @@ void _decode_opc(DisasContext * ctx) @@ -1519,53 +1599,69 @@ void _decode_opc(DisasContext * ctx)
1519 if (ctx->fpscr & FPSCR_PR) { 1599 if (ctx->fpscr & FPSCR_PR) {
1520 if (ctx->opcode & 0x0100) 1600 if (ctx->opcode & 0x0100)
1521 break; /* illegal instruction */ 1601 break; /* illegal instruction */
1522 - gen_op_fmov_drN_DT0(DREG(B11_8));  
1523 - gen_op_fabs_DT();  
1524 - gen_op_fmov_DT0_drN(DREG(B11_8)); 1602 + TCGv fp = tcg_temp_new(TCG_TYPE_I64);
  1603 + gen_load_fpr64(fp, DREG(B11_8));
  1604 + tcg_gen_helper_1_1(helper_fabs_DT, fp, fp);
  1605 + gen_store_fpr64(fp, DREG(B11_8));
  1606 + tcg_temp_free(fp);
1525 } else { 1607 } else {
1526 - gen_op_fmov_frN_FT0(FREG(B11_8));  
1527 - gen_op_fabs_FT();  
1528 - gen_op_fmov_FT0_frN(FREG(B11_8)); 1608 + TCGv fp = tcg_temp_new(TCG_TYPE_I32);
  1609 + gen_load_fpr32(fp, FREG(B11_8));
  1610 + tcg_gen_helper_1_1(helper_fabs_FT, fp, fp);
  1611 + gen_store_fpr32(fp, FREG(B11_8));
  1612 + tcg_temp_free(fp);
1529 } 1613 }
1530 return; 1614 return;
1531 case 0xf06d: /* fsqrt FRn */ 1615 case 0xf06d: /* fsqrt FRn */
1532 if (ctx->fpscr & FPSCR_PR) { 1616 if (ctx->fpscr & FPSCR_PR) {
1533 if (ctx->opcode & 0x0100) 1617 if (ctx->opcode & 0x0100)
1534 break; /* illegal instruction */ 1618 break; /* illegal instruction */
1535 - gen_op_fmov_drN_DT0(FREG(B11_8));  
1536 - gen_op_fsqrt_DT();  
1537 - gen_op_fmov_DT0_drN(FREG(B11_8)); 1619 + TCGv fp = tcg_temp_new(TCG_TYPE_I64);
  1620 + gen_load_fpr64(fp, DREG(B11_8));
  1621 + tcg_gen_helper_1_1(helper_fsqrt_DT, fp, fp);
  1622 + gen_store_fpr64(fp, DREG(B11_8));
  1623 + tcg_temp_free(fp);
1538 } else { 1624 } else {
1539 - gen_op_fmov_frN_FT0(FREG(B11_8));  
1540 - gen_op_fsqrt_FT();  
1541 - gen_op_fmov_FT0_frN(FREG(B11_8)); 1625 + TCGv fp = tcg_temp_new(TCG_TYPE_I32);
  1626 + gen_load_fpr32(fp, FREG(B11_8));
  1627 + tcg_gen_helper_1_1(helper_fsqrt_FT, fp, fp);
  1628 + gen_store_fpr32(fp, FREG(B11_8));
  1629 + tcg_temp_free(fp);
1542 } 1630 }
1543 return; 1631 return;
1544 case 0xf07d: /* fsrra FRn */ 1632 case 0xf07d: /* fsrra FRn */
1545 break; 1633 break;
1546 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ 1634 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1547 if (!(ctx->fpscr & FPSCR_PR)) { 1635 if (!(ctx->fpscr & FPSCR_PR)) {
1548 - tcg_gen_movi_i32(cpu_T[0], 0);  
1549 - gen_op_fmov_T0_frN(FREG(B11_8)); 1636 + TCGv val = tcg_const_i32(0);
  1637 + gen_load_fpr32(val, FREG(B11_8));
  1638 + tcg_temp_free(val);
1550 return; 1639 return;
1551 } 1640 }
1552 break; 1641 break;
1553 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ 1642 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1554 if (!(ctx->fpscr & FPSCR_PR)) { 1643 if (!(ctx->fpscr & FPSCR_PR)) {
1555 - tcg_gen_movi_i32(cpu_T[0], 0x3f800000);  
1556 - gen_op_fmov_T0_frN(FREG(B11_8)); 1644 + TCGv val = tcg_const_i32(0x3f800000);
  1645 + gen_load_fpr32(val, FREG(B11_8));
  1646 + tcg_temp_free(val);
1557 return; 1647 return;
1558 } 1648 }
1559 break; 1649 break;
1560 case 0xf0ad: /* fcnvsd FPUL,DRn */ 1650 case 0xf0ad: /* fcnvsd FPUL,DRn */
1561 - gen_op_movl_fpul_FT0();  
1562 - gen_op_fcnvsd_FT_DT();  
1563 - gen_op_fmov_DT0_drN(DREG(B11_8)); 1651 + {
  1652 + TCGv fp = tcg_temp_new(TCG_TYPE_I64);
  1653 + tcg_gen_helper_1_1(helper_fcnvsd_FT_DT, fp, cpu_fpul);
  1654 + gen_store_fpr64(fp, DREG(B11_8));
  1655 + tcg_temp_free(fp);
  1656 + }
1564 return; 1657 return;
1565 case 0xf0bd: /* fcnvds DRn,FPUL */ 1658 case 0xf0bd: /* fcnvds DRn,FPUL */
1566 - gen_op_fmov_drN_DT0(DREG(B11_8));  
1567 - gen_op_fcnvds_DT_FT();  
1568 - gen_op_movl_FT0_fpul(); 1659 + {
  1660 + TCGv fp = tcg_temp_new(TCG_TYPE_I64);
  1661 + gen_load_fpr64(fp, DREG(B11_8));
  1662 + tcg_gen_helper_1_1(helper_fcnvds_DT_FT, cpu_fpul, fp);
  1663 + tcg_temp_free(fp);
  1664 + }
1569 return; 1665 return;
1570 } 1666 }
1571 1667