gwj / at91sam9263 · Commits

Commit cab3c825371b73fa71ada4dfa8d64ca99bc08638

Authored by Kevin Wolf
Committed by Anthony Liguori
1 parent 8cf07dcb

e1000: Ignore reset command 

When a reset is requested, the current e1000 emulation never clears the
reset bit which may cause a driver to hang. This patch masks the reset
bit out when setting the control registert, so the reset is immediately
completed.

Signed-off-by: Kevin Wolf <mail@kevin-wolf.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Inline Side-by-side
Showing 1 changed file with 9 additions and 2 deletions
hw/e1000.c
  View file @cab3c82
@@ -190,6 +190,13 @@ rxbufsize(uint32_t v) @@ -190,6 +190,13 @@ rxbufsize(uint32_t v)
190 } 190 }
191 191
192 static void 192 static void
  193 +set_ctrl(E1000State *s, int index, uint32_t val)
  194 +{
  195 + /* RST is self clearing */
  196 + s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
  197 +}
  198 +
  199 +static void
193 set_rx_control(E1000State *s, int index, uint32_t val) 200 set_rx_control(E1000State *s, int index, uint32_t val)
194 { 201 {
195 s->mac_reg[RCTL] = val; 202 s->mac_reg[RCTL] = val;
@@ -783,12 +790,12 @@ enum { NREADOPS = ARRAY_SIZE(macreg_readops) }; @@ -783,12 +790,12 @@ enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
783 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = { 790 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
784 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC), 791 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
785 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH), 792 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
786 - putreg(RDBAL), putreg(LEDCTL), putreg(CTRL), putreg(VET), 793 + putreg(RDBAL), putreg(LEDCTL), putreg(VET),
787 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl, 794 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
788 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics, 795 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
789 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt, 796 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
790 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr, 797 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
791 - [EECD] = set_eecd, [RCTL] = set_rx_control, 798 + [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
792 [RA ... RA+31] = &mac_writereg, 799 [RA ... RA+31] = &mac_writereg,
793 [MTA ... MTA+127] = &mac_writereg, 800 [MTA ... MTA+127] = &mac_writereg,
794 [VFTA ... VFTA+127] = &mac_writereg, 801 [VFTA ... VFTA+127] = &mac_writereg,