Commit cab3bee2d6f1d6eb6ad74006b8a63562cda9ba4d
1 parent
fe1e5c53
target-ppc: convert trap instructions to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5788 c046a42c-6fe2-441c-8c8c-71466251a162
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5 changed files
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32 additions
and
43 deletions
target-ppc/helper.h
... | ... | @@ -2,6 +2,10 @@ |
2 | 2 | |
3 | 3 | DEF_HELPER_2(raise_exception_err, void, i32, i32) |
4 | 4 | DEF_HELPER_0(raise_debug, void) |
5 | +DEF_HELPER_3(tw, void, tl, tl, i32) | |
6 | +#if defined(TARGET_PPC64) | |
7 | +DEF_HELPER_3(td, void, tl, tl, i32) | |
8 | +#endif | |
5 | 9 | |
6 | 10 | DEF_HELPER_2(fcmpo, i32, i64, i64) |
7 | 11 | DEF_HELPER_2(fcmpu, i32, i64, i64) | ... | ... |
target-ppc/op.c
... | ... | @@ -334,21 +334,6 @@ void OPPROTO op_store_excp_vector (void) |
334 | 334 | } |
335 | 335 | #endif |
336 | 336 | |
337 | -/* Trap word */ | |
338 | -void OPPROTO op_tw (void) | |
339 | -{ | |
340 | - do_tw(PARAM1); | |
341 | - RETURN(); | |
342 | -} | |
343 | - | |
344 | -#if defined(TARGET_PPC64) | |
345 | -void OPPROTO op_td (void) | |
346 | -{ | |
347 | - do_td(PARAM1); | |
348 | - RETURN(); | |
349 | -} | |
350 | -#endif | |
351 | - | |
352 | 337 | #if !defined(CONFIG_USER_ONLY) |
353 | 338 | /* tlbia */ |
354 | 339 | void OPPROTO op_tlbia (void) | ... | ... |
target-ppc/op_helper.c
... | ... | @@ -1424,25 +1424,25 @@ void do_hrfid (void) |
1424 | 1424 | #endif |
1425 | 1425 | #endif |
1426 | 1426 | |
1427 | -void do_tw (int flags) | |
1427 | +void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags) | |
1428 | 1428 | { |
1429 | - if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) || | |
1430 | - ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) || | |
1431 | - ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) || | |
1432 | - ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) || | |
1433 | - ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) { | |
1429 | + if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) || | |
1430 | + ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) || | |
1431 | + ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) || | |
1432 | + ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) || | |
1433 | + ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) { | |
1434 | 1434 | raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); |
1435 | 1435 | } |
1436 | 1436 | } |
1437 | 1437 | |
1438 | 1438 | #if defined(TARGET_PPC64) |
1439 | -void do_td (int flags) | |
1439 | +void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags) | |
1440 | 1440 | { |
1441 | - if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) || | |
1442 | - ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) || | |
1443 | - ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) || | |
1444 | - ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) || | |
1445 | - ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01))))) | |
1441 | + if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) || | |
1442 | + ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) || | |
1443 | + ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) || | |
1444 | + ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) || | |
1445 | + ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) | |
1446 | 1446 | raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); |
1447 | 1447 | } |
1448 | 1448 | #endif | ... | ... |
target-ppc/op_helper.h
... | ... | @@ -60,10 +60,6 @@ target_ulong ppc_load_dump_spr (int sprn); |
60 | 60 | void ppc_store_dump_spr (int sprn, target_ulong val); |
61 | 61 | |
62 | 62 | /* Misc */ |
63 | -void do_tw (int flags); | |
64 | -#if defined(TARGET_PPC64) | |
65 | -void do_td (int flags); | |
66 | -#endif | |
67 | 63 | #if !defined(CONFIG_USER_ONLY) |
68 | 64 | void do_store_msr (void); |
69 | 65 | void do_rfi (void); | ... | ... |
target-ppc/translate.c
... | ... | @@ -3819,42 +3819,46 @@ GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW) |
3819 | 3819 | /* tw */ |
3820 | 3820 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW) |
3821 | 3821 | { |
3822 | - tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
3823 | - tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
3822 | + TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); | |
3824 | 3823 | /* Update the nip since this might generate a trap exception */ |
3825 | 3824 | gen_update_nip(ctx, ctx->nip); |
3826 | - gen_op_tw(TO(ctx->opcode)); | |
3825 | + gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
3826 | + tcg_temp_free_i32(t0); | |
3827 | 3827 | } |
3828 | 3828 | |
3829 | 3829 | /* twi */ |
3830 | 3830 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
3831 | 3831 | { |
3832 | - tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
3833 | - tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); | |
3832 | + TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
3833 | + TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
3834 | 3834 | /* Update the nip since this might generate a trap exception */ |
3835 | 3835 | gen_update_nip(ctx, ctx->nip); |
3836 | - gen_op_tw(TO(ctx->opcode)); | |
3836 | + gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
3837 | + tcg_temp_free(t0); | |
3838 | + tcg_temp_free_i32(t1); | |
3837 | 3839 | } |
3838 | 3840 | |
3839 | 3841 | #if defined(TARGET_PPC64) |
3840 | 3842 | /* td */ |
3841 | 3843 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B) |
3842 | 3844 | { |
3843 | - tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
3844 | - tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); | |
3845 | + TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); | |
3845 | 3846 | /* Update the nip since this might generate a trap exception */ |
3846 | 3847 | gen_update_nip(ctx, ctx->nip); |
3847 | - gen_op_td(TO(ctx->opcode)); | |
3848 | + gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
3849 | + tcg_temp_free_i32(t0); | |
3848 | 3850 | } |
3849 | 3851 | |
3850 | 3852 | /* tdi */ |
3851 | 3853 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B) |
3852 | 3854 | { |
3853 | - tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); | |
3854 | - tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); | |
3855 | + TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
3856 | + TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
3855 | 3857 | /* Update the nip since this might generate a trap exception */ |
3856 | 3858 | gen_update_nip(ctx, ctx->nip); |
3857 | - gen_op_td(TO(ctx->opcode)); | |
3859 | + gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
3860 | + tcg_temp_free(t0); | |
3861 | + tcg_temp_free_i32(t1); | |
3858 | 3862 | } |
3859 | 3863 | #endif |
3860 | 3864 | ... | ... |