Commit c9bac22c7d2405d5d243717f4a6b2e85a99e62fe
1 parent
06d92f40
M68K watchpoint hacks.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2969 c046a42c-6fe2-441c-8c8c-71466251a162
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11 additions
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target-m68k/translate.c
| @@ -51,6 +51,7 @@ typedef struct DisasContext { | @@ -51,6 +51,7 @@ typedef struct DisasContext { | ||
| 51 | uint32_t fpcr; | 51 | uint32_t fpcr; |
| 52 | struct TranslationBlock *tb; | 52 | struct TranslationBlock *tb; |
| 53 | int singlestep_enabled; | 53 | int singlestep_enabled; |
| 54 | + int is_mem; | ||
| 54 | } DisasContext; | 55 | } DisasContext; |
| 55 | 56 | ||
| 56 | #define DISAS_JUMP_NEXT 4 | 57 | #define DISAS_JUMP_NEXT 4 |
| @@ -129,6 +130,7 @@ typedef void (*disas_proc)(DisasContext *, uint16_t); | @@ -129,6 +130,7 @@ typedef void (*disas_proc)(DisasContext *, uint16_t); | ||
| 129 | static inline int gen_load(DisasContext * s, int opsize, int addr, int sign) | 130 | static inline int gen_load(DisasContext * s, int opsize, int addr, int sign) |
| 130 | { | 131 | { |
| 131 | int tmp; | 132 | int tmp; |
| 133 | + s->is_mem = 1; | ||
| 132 | switch(opsize) { | 134 | switch(opsize) { |
| 133 | case OS_BYTE: | 135 | case OS_BYTE: |
| 134 | tmp = gen_new_qreg(QMODE_I32); | 136 | tmp = gen_new_qreg(QMODE_I32); |
| @@ -166,6 +168,7 @@ static inline int gen_load(DisasContext * s, int opsize, int addr, int sign) | @@ -166,6 +168,7 @@ static inline int gen_load(DisasContext * s, int opsize, int addr, int sign) | ||
| 166 | /* Generate a store. */ | 168 | /* Generate a store. */ |
| 167 | static inline void gen_store(DisasContext *s, int opsize, int addr, int val) | 169 | static inline void gen_store(DisasContext *s, int opsize, int addr, int val) |
| 168 | { | 170 | { |
| 171 | + s->is_mem = 1; | ||
| 169 | switch(opsize) { | 172 | switch(opsize) { |
| 170 | case OS_BYTE: | 173 | case OS_BYTE: |
| 171 | gen_st(s, 8, addr, val); | 174 | gen_st(s, 8, addr, val); |
| @@ -2205,6 +2208,7 @@ DISAS_INSN(fpu) | @@ -2205,6 +2208,7 @@ DISAS_INSN(fpu) | ||
| 2205 | dest = QREG_F0; | 2208 | dest = QREG_F0; |
| 2206 | while (mask) { | 2209 | while (mask) { |
| 2207 | if (ext & mask) { | 2210 | if (ext & mask) { |
| 2211 | + s->is_mem = 1; | ||
| 2208 | if (ext & (1 << 13)) { | 2212 | if (ext & (1 << 13)) { |
| 2209 | /* store */ | 2213 | /* store */ |
| 2210 | gen_st(s, f64, addr, dest); | 2214 | gen_st(s, f64, addr, dest); |
| @@ -3169,6 +3173,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, | @@ -3169,6 +3173,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, | ||
| 3169 | dc->singlestep_enabled = env->singlestep_enabled; | 3173 | dc->singlestep_enabled = env->singlestep_enabled; |
| 3170 | dc->fpcr = env->fpcr; | 3174 | dc->fpcr = env->fpcr; |
| 3171 | dc->user = (env->sr & SR_S) == 0; | 3175 | dc->user = (env->sr & SR_S) == 0; |
| 3176 | + dc->is_mem = 0; | ||
| 3172 | nb_gen_labels = 0; | 3177 | nb_gen_labels = 0; |
| 3173 | lj = -1; | 3178 | lj = -1; |
| 3174 | do { | 3179 | do { |
| @@ -3199,6 +3204,12 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, | @@ -3199,6 +3204,12 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, | ||
| 3199 | last_cc_op = dc->cc_op; | 3204 | last_cc_op = dc->cc_op; |
| 3200 | dc->insn_pc = dc->pc; | 3205 | dc->insn_pc = dc->pc; |
| 3201 | disas_m68k_insn(env, dc); | 3206 | disas_m68k_insn(env, dc); |
| 3207 | + | ||
| 3208 | + /* Terminate the TB on memory ops if watchpoints are present. */ | ||
| 3209 | + /* FIXME: This should be replacd by the deterministic execution | ||
| 3210 | + * IRQ raising bits. */ | ||
| 3211 | + if (dc->is_mem && env->nb_watchpoints) | ||
| 3212 | + break; | ||
| 3202 | } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end && | 3213 | } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end && |
| 3203 | !env->singlestep_enabled && | 3214 | !env->singlestep_enabled && |
| 3204 | (pc_offset) < (TARGET_PAGE_SIZE - 32)); | 3215 | (pc_offset) < (TARGET_PAGE_SIZE - 32)); |