gwj / at91sam9263 · Commits

Commit c6945b153cff51712263ec4abfee5e3ecc5e2577

Authored by aurel32
1 parent 3aa9bd6c

target-mips: DMA support for RC4030 chipset 

Attached patch implements DMA support to RC4030 chipset and simplifies
jazz IO part (at 0xf0000000), where registers contain 16 bit values.
Config register has not a clear meaning (only one value is always valid,
and sometimes another one), so use a magic value instead.
The patch also wires DMA transfers for the SCSI adapter in the Jazz
emulation (Mips Magnum 4000 and Acer Pica 61).

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6145 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 246 additions and 92 deletions
hw/mips.h
  View file @c6945b1
... ... @@ -27,6 +27,10 @@ extern void cpu_mips_irq_init_cpu(CPUState *env);
27 27 extern void cpu_mips_clock_init(CPUState *);
28 28  
29 29 /* rc4030.c */
30   -qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus);
  30 +typedef struct rc4030DMAState *rc4030_dma;
  31 +typedef void (*rc4030_dma_function)(void *dma, uint8_t *buf, int len);
  32 +qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
  33 + rc4030_dma **dmas,
  34 + rc4030_dma_function *dma_read, rc4030_dma_function *dma_write);
31 35  
32 36 #endif
... ...
hw/mips_jazz.c
  View file @c6945b1
... ... @@ -75,6 +75,24 @@ static CPUWriteMemoryFunc *rtc_write[3] = {
75 75 rtc_writeb,
76 76 };
77 77  
  78 +static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  79 +{
  80 + /* Nothing to do. That is only to ensure that
  81 + * the current DMA acknowledge cycle is completed. */
  82 +}
  83 +
  84 +static CPUReadMemoryFunc *dma_dummy_read[3] = {
  85 + NULL,
  86 + NULL,
  87 + NULL,
  88 +};
  89 +
  90 +static CPUWriteMemoryFunc *dma_dummy_write[3] = {
  91 + dma_dummy_writeb,
  92 + dma_dummy_writeb,
  93 + dma_dummy_writeb,
  94 +};
  95 +
78 96 #ifdef HAS_AUDIO
79 97 static void audio_init(qemu_irq *pic)
80 98 {
... ... @@ -102,16 +120,6 @@ static void audio_init(qemu_irq *pic)
102 120 }
103 121 #endif
104 122  
105   -static void espdma_memory_read(void *opaque, uint8_t *buf, int len)
106   -{
107   - printf("espdma_memory_read(buf %p, len %d) not implemented\n", buf, len);
108   -}
109   -
110   -static void espdma_memory_write(void *opaque, uint8_t *buf, int len)
111   -{
112   - printf("espdma_memory_write(buf %p, len %d) not implemented\n", buf, len);
113   -}
114   -
115 123 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
116 124 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
117 125  
... ... @@ -125,9 +133,11 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
125 133 int bios_size, n;
126 134 CPUState *env;
127 135 qemu_irq *rc4030, *i8259;
  136 + rc4030_dma *dmas;
  137 + rc4030_dma_function dma_read, dma_write;
128 138 void *scsi_hba;
129 139 int hd;
130   - int s_rtc;
  140 + int s_rtc, s_dma_dummy;
131 141 PITState *pit;
132 142 BlockDriverState *fds[MAX_FD];
133 143 qemu_irq esp_reset;
... ... @@ -153,7 +163,9 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
153 163  
154 164 /* load the BIOS image. */
155 165 bios_offset = ram_size + vga_ram_size;
156   - snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
  166 + if (bios_name == NULL)
  167 + bios_name = BIOS_FILENAME;
  168 + snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
157 169 bios_size = load_image(buf, phys_ram_base + bios_offset);
158 170 if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
159 171 fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
... ... @@ -171,10 +183,14 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
171 183 cpu_mips_clock_init(env);
172 184  
173 185 /* Chipset */
174   - rc4030 = rc4030_init(env->irq[6], env->irq[3]);
  186 + rc4030 = rc4030_init(env->irq[6], env->irq[3],
  187 + &dmas, &dma_read, &dma_write);
  188 + s_dma_dummy = cpu_register_io_memory(0, dma_dummy_read, dma_dummy_write, NULL);
  189 + cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
175 190  
176 191 /* ISA devices */
177 192 i8259 = i8259_init(env->irq[4]);
  193 + DMA_init(0);
178 194 pit = pit_init(0x40, i8259[0]);
179 195 pcspk_init(pit);
180 196  
... ... @@ -200,7 +216,7 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
200 216  
201 217 /* SCSI adapter */
202 218 scsi_hba = esp_init(0x80002000, 0,
203   - espdma_memory_read, espdma_memory_write, NULL,
  219 + dma_read, dma_write, dmas[0],
204 220 rc4030[5], &esp_reset);
205 221 for (n = 0; n < ESP_MAX_DEVS; n++) {
206 222 hd = drive_get_index(IF_SCSI, 0, n);
... ... @@ -278,6 +294,7 @@ QEMUMachine mips_magnum_machine = {
278 294 .init = mips_magnum_init,
279 295 .ram_require = MAGNUM_BIOS_SIZE + VGA_RAM_SIZE,
280 296 .nodisk_ok = 1,
  297 + .use_scsi = 1,
281 298 };
282 299  
283 300 QEMUMachine mips_pica61_machine = {
... ... @@ -286,4 +303,5 @@ QEMUMachine mips_pica61_machine = {
286 303 .init = mips_pica61_init,
287 304 .ram_require = MAGNUM_BIOS_SIZE + VGA_RAM_SIZE,
288 305 .nodisk_ok = 1,
  306 + .use_scsi = 1,
289 307 };
... ...
hw/rc4030.c
  View file @c6945b1
... ... @@ -26,13 +26,43 @@
26 26 #include "mips.h"
27 27 #include "qemu-timer.h"
28 28  
  29 +/********************************************************/
  30 +/* debug rc4030 */
  31 +
29 32 //#define DEBUG_RC4030
  33 +//#define DEBUG_RC4030_DMA
30 34  
31 35 #ifdef DEBUG_RC4030
  36 +#define DPRINTF(fmt, args...) \
  37 +do { printf("rc4030: " fmt , ##args); } while (0)
32 38 static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
33 39 "network", "scsi", "keyboard", "mouse", "serial0", "serial1" };
  40 +#else
  41 +#define DPRINTF(fmt, args...)
34 42 #endif
35 43  
  44 +#define RC4030_ERROR(fmt, args...) \
  45 +do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ##args); } while (0)
  46 +
  47 +/********************************************************/
  48 +/* rc4030 emulation */
  49 +
  50 +typedef struct dma_pagetable_entry {
  51 + int32_t frame;
  52 + int32_t owner;
  53 +} __attribute__((packed)) dma_pagetable_entry;
  54 +
  55 +#define DMA_PAGESIZE 4096
  56 +#define DMA_REG_ENABLE 1
  57 +#define DMA_REG_COUNT 2
  58 +#define DMA_REG_ADDRESS 3
  59 +
  60 +#define DMA_FLAG_ENABLE 0x0001
  61 +#define DMA_FLAG_MEM_TO_DEV 0x0002
  62 +#define DMA_FLAG_TC_INTR 0x0100
  63 +#define DMA_FLAG_MEM_INTR 0x0200
  64 +#define DMA_FLAG_ADDR_INTR 0x0400
  65 +
36 66 typedef struct rc4030State
37 67 {
38 68 uint32_t config; /* 0x0000: RC4030 config register */
... ... @@ -51,7 +81,6 @@ typedef struct rc4030State
51 81 uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
52 82 uint32_t cache_bwin; /* 0x0060: I/O Cache Buffer Window */
53 83  
54   - uint32_t offset208;
55 84 uint32_t offset210;
56 85 uint32_t nvram_protect; /* 0x0220: NV ram protect register */
57 86 uint32_t offset238;
... ... @@ -63,7 +92,6 @@ typedef struct rc4030State
63 92 QEMUTimer *periodic_timer;
64 93 uint32_t itr; /* Interval timer reload */
65 94  
66   - uint32_t dummy32;
67 95 qemu_irq timer_irq;
68 96 qemu_irq jazz_bus_irq;
69 97 } rc4030State;
... ... @@ -165,7 +193,7 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
165 193 case 0x01d0:
166 194 case 0x01d8:
167 195 case 0x01e0:
168   - case 0x1e8:
  196 + case 0x01e8:
169 197 case 0x01f0:
170 198 case 0x01f8:
171 199 {
... ... @@ -176,7 +204,7 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
176 204 break;
177 205 /* Offset 0x0208 */
178 206 case 0x0208:
179   - val = s->offset208;
  207 + val = 0;
180 208 break;
181 209 /* Offset 0x0210 */
182 210 case 0x0210:
... ... @@ -188,7 +216,7 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
188 216 break;
189 217 /* Interval timer count */
190 218 case 0x0230:
191   - val = s->dummy32;
  219 + val = 0;
192 220 qemu_irq_lower(s->timer_irq);
193 221 break;
194 222 /* Offset 0x0238 */
... ... @@ -196,17 +224,13 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
196 224 val = s->offset238;
197 225 break;
198 226 default:
199   -#ifdef DEBUG_RC4030
200   - printf("rc4030: invalid read [" TARGET_FMT_lx "]\n", addr);
201   -#endif
  227 + RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr);
202 228 val = 0;
203 229 break;
204 230 }
205 231  
206   -#ifdef DEBUG_RC4030
207 232 if ((addr & ~3) != 0x230)
208   - printf("rc4030: read 0x%02x at " TARGET_FMT_lx "\n", val, addr);
209   -#endif
  233 + DPRINTF("read 0x%02x at " TARGET_FMT_plx "\n", val, addr);
210 234  
211 235 return val;
212 236 }
... ... @@ -231,9 +255,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
231 255 rc4030State *s = opaque;
232 256 addr &= 0x3fff;
233 257  
234   -#ifdef DEBUG_RC4030
235   - printf("rc4030: write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
236   -#endif
  258 + DPRINTF("write 0x%02x at " TARGET_FMT_plx "\n", val, addr);
237 259  
238 260 switch (addr & ~0x3) {
239 261 /* Global config register */
... ... @@ -248,6 +270,13 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
248 270 case 0x0020:
249 271 s->dma_tl_limit = val;
250 272 break;
  273 + /* DMA transl. table invalidated */
  274 + case 0x0028:
  275 + break;
  276 + /* Cache Maintenance */
  277 + case 0x0030:
  278 + RC4030_ERROR("Cache maintenance not handled yet (val 0x%02x)\n", val);
  279 + break;
251 280 /* I/O Cache Physical Tag */
252 281 case 0x0048:
253 282 s->cache_ptag = val;
... ... @@ -322,7 +351,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
322 351 case 0x01d0:
323 352 case 0x01d8:
324 353 case 0x01e0:
325   - case 0x1e8:
  354 + case 0x01e8:
326 355 case 0x01f0:
327 356 case 0x01f8:
328 357 {
... ... @@ -342,9 +371,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
342 371 set_next_tick(s);
343 372 break;
344 373 default:
345   -#ifdef DEBUG_RC4030
346   - printf("rc4030: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
347   -#endif
  374 + RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr);
348 375 break;
349 376 }
350 377 }
... ... @@ -402,7 +429,7 @@ static void update_jazz_irq(rc4030State *s)
402 429 #ifdef DEBUG_RC4030
403 430 if (s->isr_jazz != 0) {
404 431 uint32_t irq = 0;
405   - printf("jazz pending:");
  432 + DPRINTF("pending irqs:");
406 433 for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) {
407 434 if (s->isr_jazz & (1 << irq)) {
408 435 printf(" %s", irq_names[irq]);
... ... @@ -442,7 +469,7 @@ static void rc4030_periodic_timer(void *opaque)
442 469 qemu_irq_raise(s->timer_irq);
443 470 }
444 471  
445   -static uint32_t int_readb(void *opaque, target_phys_addr_t addr)
  472 +static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
446 473 {
447 474 rc4030State *s = opaque;
448 475 uint32_t val;
... ... @@ -450,14 +477,14 @@ static uint32_t int_readb(void *opaque, target_phys_addr_t addr)
450 477 addr &= 0xfff;
451 478  
452 479 switch (addr) {
  480 + /* Local bus int source */
453 481 case 0x00: {
454   - /* Local bus int source */
455 482 uint32_t pending = s->isr_jazz & s->imr_jazz;
456 483 val = 0;
457 484 irq = 0;
458 485 while (pending) {
459 486 if (pending & 1) {
460   - //printf("returning irq %s\n", irq_names[irq]);
  487 + DPRINTF("returning irq %s\n", irq_names[irq]);
461 488 val = (irq + 1) << 2;
462 489 break;
463 490 }
... ... @@ -466,100 +493,93 @@ static uint32_t int_readb(void *opaque, target_phys_addr_t addr)
466 493 }
467 494 break;
468 495 }
  496 + /* Local bus int enable mask */
  497 + case 0x02:
  498 + val = s->imr_jazz;
  499 + break;
469 500 default:
470   -#ifdef DEBUG_RC4030
471   - printf("rc4030: (interrupt controller) invalid read [" TARGET_FMT_lx "]\n", addr);
472   -#endif
473   - val = 0;
  501 + RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr);
  502 + val = 0;
474 503 }
475 504  
476   -#ifdef DEBUG_RC4030
477   - printf("rc4030: (interrupt controller) read 0x%02x at " TARGET_FMT_lx "\n", val, addr);
478   -#endif
  505 + DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_plx "\n", val, addr);
479 506  
480 507 return val;
481 508 }
482 509  
483   -static uint32_t int_readw(void *opaque, target_phys_addr_t addr)
  510 +static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr)
484 511 {
485 512 uint32_t v;
486   - v = int_readb(opaque, addr);
487   - v |= int_readb(opaque, addr + 1) << 8;
488   - return v;
  513 + v = jazzio_readw(opaque, addr & ~0x1);
  514 + return (v >> (8 * (addr & 0x1))) & 0xff;
489 515 }
490 516  
491   -static uint32_t int_readl(void *opaque, target_phys_addr_t addr)
  517 +static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
492 518 {
493 519 uint32_t v;
494   - v = int_readb(opaque, addr);
495   - v |= int_readb(opaque, addr + 1) << 8;
496   - v |= int_readb(opaque, addr + 2) << 16;
497   - v |= int_readb(opaque, addr + 3) << 24;
  520 + v = jazzio_readw(opaque, addr);
  521 + v |= jazzio_readw(opaque, addr + 2) << 16;
498 522 return v;
499 523 }
500 524  
501   -static void int_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  525 +static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
502 526 {
503 527 rc4030State *s = opaque;
504 528 addr &= 0xfff;
505 529  
506   -#ifdef DEBUG_RC4030
507   - printf("rc4030: (interrupt controller) write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
508   -#endif
  530 + DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr);
509 531  
510 532 switch (addr) {
511 533 /* Local bus int enable mask */
512 534 case 0x02:
513   - s->imr_jazz = (s->imr_jazz & 0xff00) | (val << 0); update_jazz_irq(s);
514   - break;
515   - case 0x03:
516   - s->imr_jazz = (s->imr_jazz & 0x00ff) | (val << 8); update_jazz_irq(s);
  535 + s->imr_jazz = val;
  536 + update_jazz_irq(s);
517 537 break;
518 538 default:
519   -#ifdef DEBUG_RC4030
520   - printf("rc4030: (interrupt controller) invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
521   -#endif
  539 + RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at [" TARGET_FMT_plx "]\n", val, addr);
522 540 break;
523 541 }
524 542 }
525 543  
526   -static void int_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
  544 +static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
527 545 {
528   - int_writeb(opaque, addr, val & 0xff);
529   - int_writeb(opaque, addr + 1, (val >> 8) & 0xff);
  546 + uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
  547 +
  548 + switch (addr & 1) {
  549 + case 0:
  550 + val = val | (old_val & 0xff00);
  551 + break;
  552 + case 1:
  553 + val = (val << 8) | (old_val & 0x00ff);
  554 + break;
  555 + }
  556 + jazzio_writew(opaque, addr & ~0x1, val);
530 557 }
531 558  
532   -static void int_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  559 +static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
533 560 {
534   - int_writeb(opaque, addr, val & 0xff);
535   - int_writeb(opaque, addr + 1, (val >> 8) & 0xff);
536   - int_writeb(opaque, addr + 2, (val >> 16) & 0xff);
537   - int_writeb(opaque, addr + 3, (val >> 24) & 0xff);
  561 + jazzio_writew(opaque, addr, val & 0xffff);
  562 + jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff);
538 563 }
539 564  
540   -static CPUReadMemoryFunc *int_read[3] = {
541   - int_readb,
542   - int_readw,
543   - int_readl,
  565 +static CPUReadMemoryFunc *jazzio_read[3] = {
  566 + jazzio_readb,
  567 + jazzio_readw,
  568 + jazzio_readl,
544 569 };
545 570  
546   -static CPUWriteMemoryFunc *int_write[3] = {
547   - int_writeb,
548   - int_writew,
549   - int_writel,
  571 +static CPUWriteMemoryFunc *jazzio_write[3] = {
  572 + jazzio_writeb,
  573 + jazzio_writew,
  574 + jazzio_writel,
550 575 };
551 576  
552   -#define G364_512KB_RAM (0x0)
553   -#define G364_2MB_RAM (0x1)
554   -#define G364_8MB_RAM (0x2)
555   -#define G364_32MB_RAM (0x3)
556   -
557 577 static void rc4030_reset(void *opaque)
558 578 {
559 579 rc4030State *s = opaque;
560 580 int i;
561 581  
562   - s->config = (G364_2MB_RAM << 8) | 0x04;
  582 + s->config = 0x410; /* some boards seem to accept 0x104 too */
563 583 s->invalid_address_register = 0;
564 584  
565 585 memset(s->dma_regs, 0, sizeof(s->dma_regs));
... ... @@ -569,7 +589,6 @@ static void rc4030_reset(void *opaque)
569 589 s->cache_ptag = s->cache_ltag = 0;
570 590 s->cache_bmask = s->cache_bwin = 0;
571 591  
572   - s->offset208 = 0;
573 592 s->offset210 = 0x18186;
574 593 s->nvram_protect = 7;
575 594 s->offset238 = 7;
... ... @@ -578,21 +597,134 @@ static void rc4030_reset(void *opaque)
578 597 s->imr_jazz = s->isr_jazz = 0;
579 598  
580 599 s->itr = 0;
581   - s->dummy32 = 0;
582 600  
583 601 qemu_irq_lower(s->timer_irq);
584 602 qemu_irq_lower(s->jazz_bus_irq);
585 603 }
586 604  
587   -qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus)
  605 +static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
  606 +{
  607 + rc4030State *s = opaque;
  608 + target_phys_addr_t entry_addr;
  609 + target_phys_addr_t dma_addr, phys_addr;
  610 + dma_pagetable_entry entry;
  611 + int index, dev_to_mem;
  612 + int ncpy, i;
  613 +
  614 + s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
  615 +
  616 + /* Check DMA channel consistency */
  617 + dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
  618 + if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
  619 + (is_write != dev_to_mem)) {
  620 + s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
  621 + return;
  622 + }
  623 +
  624 + if (len > s->dma_regs[n][DMA_REG_COUNT])
  625 + len = s->dma_regs[n][DMA_REG_COUNT];
  626 +
  627 + dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
  628 + i = 0;
  629 + for (;;) {
  630 + if (i == len) {
  631 + s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
  632 + break;
  633 + }
  634 +
  635 + ncpy = DMA_PAGESIZE - (dma_addr & (DMA_PAGESIZE - 1));
  636 + if (ncpy > len - i)
  637 + ncpy = len - i;
  638 +
  639 + /* Get DMA translation table entry */
  640 + index = dma_addr / DMA_PAGESIZE;
  641 + if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) {
  642 + s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
  643 + break;
  644 + }
  645 + entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
  646 + /* XXX: not sure. should we really use only lowest bits? */
  647 + entry_addr &= 0x7fffffff;
  648 + cpu_physical_memory_rw(entry_addr, (uint8_t *)&entry, sizeof(entry), 0);
  649 +
  650 + /* Read/write data at right place */
  651 + phys_addr = entry.frame + (dma_addr & (DMA_PAGESIZE - 1));
  652 + cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write);
  653 +
  654 + i += ncpy;
  655 + dma_addr += ncpy;
  656 + s->dma_regs[n][DMA_REG_COUNT] -= ncpy;
  657 + }
  658 +
  659 +#ifdef DEBUG_RC4030_DMA
  660 + {
  661 + int i, j;
  662 + printf("rc4030 dma: Copying %d bytes %s host %p\n",
  663 + len, is_write ? "from" : "to", buf);
  664 + for (i = 0; i < len; i += 16) {
  665 + int n = min(16, len - i);
  666 + for (j = 0; j < n; j++)
  667 + printf("%02x ", buf[i + j]);
  668 + while (j++ < 16)
  669 + printf(" ");
  670 + printf("| ");
  671 + for (j = 0; j < n; j++)
  672 + printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.');
  673 + printf("\n");
  674 + }
  675 + }
  676 +#endif
  677 +}
  678 +
  679 +struct rc4030DMAState {
  680 + void *opaque;
  681 + int n;
  682 +};
  683 +
  684 +static void rc4030_dma_read(void *dma, uint8_t *buf, int len)
  685 +{
  686 + rc4030_dma s = dma;
  687 + rc4030_do_dma(s->opaque, s->n, buf, len, 0);
  688 +}
  689 +
  690 +static void rc4030_dma_write(void *dma, uint8_t *buf, int len)
  691 +{
  692 + rc4030_dma s = dma;
  693 + rc4030_do_dma(s->opaque, s->n, buf, len, 1);
  694 +}
  695 +
  696 +static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
  697 +{
  698 + rc4030_dma *s;
  699 + struct rc4030DMAState *p;
  700 + int i;
  701 +
  702 + s = (rc4030_dma *)qemu_mallocz(sizeof(rc4030_dma) * n);
  703 + p = (struct rc4030DMAState *)qemu_mallocz(sizeof(struct rc4030DMAState) * n);
  704 + for (i = 0; i < n; i++) {
  705 + p->opaque = opaque;
  706 + p->n = i;
  707 + s[i] = p;
  708 + p++;
  709 + }
  710 + return s;
  711 +}
  712 +
  713 +qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
  714 + rc4030_dma **dmas,
  715 + rc4030_dma_function *dma_read, rc4030_dma_function *dma_write)
588 716 {
589 717 rc4030State *s;
590   - int s_chipset, s_int;
  718 + int s_chipset, s_jazzio;
591 719  
592 720 s = qemu_mallocz(sizeof(rc4030State));
593 721 if (!s)
594 722 return NULL;
595 723  
  724 + *dmas = rc4030_allocate_dmas(s, 4);
  725 + *dma_read = rc4030_dma_read;
  726 + *dma_write = rc4030_dma_write;
  727 +
596 728 s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
597 729 s->timer_irq = timer;
598 730 s->jazz_bus_irq = jazz_bus;
... ... @@ -602,8 +734,8 @@ qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus)
602 734  
603 735 s_chipset = cpu_register_io_memory(0, rc4030_read, rc4030_write, s);
604 736 cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
605   - s_int = cpu_register_io_memory(0, int_read, int_write, s);
606   - cpu_register_physical_memory(0xf0000000, 0x00001000, s_int);
  737 + s_jazzio = cpu_register_io_memory(0, jazzio_read, jazzio_write, s);
  738 + cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio);
607 739  
608 740 return qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
609 741 }
... ...