gwj / at91sam9263 · Commits

Commit c5df018e56855cd6ede7ab7b07fb69703d581383

Authored by bellard
1 parent a541f297

ppc: suppressed unneeded globals and headers - added explicit type for ppc nvram 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@723 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 93 additions and 129 deletions
hw/m48t59.c
  View file @c5df018
... ... @@ -21,14 +21,8 @@
21 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 22 * THE SOFTWARE.
23 23 */
24   -
25   -#include <stdlib.h>
26   -#include <stdio.h> /* needed by vl.h */
27   -#include <stdint.h>
28   -#include <string.h>
29   -#include <time.h>
30   -
31 24 #include "vl.h"
  25 +#include "m48t59.h"
32 26  
33 27 //#define NVRAM_DEBUG
34 28  
... ... @@ -38,7 +32,7 @@
38 32 #define NVRAM_PRINTF(fmt, args...) do { } while (0)
39 33 #endif
40 34  
41   -typedef struct m48t59_t {
  35 +struct m48t59_t {
42 36 /* Hardware parameters */
43 37 int IRQ;
44 38 uint32_t io_base;
... ... @@ -53,10 +47,7 @@ typedef struct m48t59_t {
53 47 /* NVRAM storage */
54 48 uint16_t addr;
55 49 uint8_t *buffer;
56   -} m48t59_t;
57   -
58   -static m48t59_t *NVRAMs;
59   -static int nb_NVRAMs;
  50 +};
60 51  
61 52 /* Fake timer functions */
62 53 /* Generic helpers for BCD */
... ... @@ -185,9 +176,8 @@ static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
185 176 }
186 177  
187 178 /* Direct access to NVRAM */
188   -void m48t59_write (void *opaque, uint32_t val)
  179 +void m48t59_write (m48t59_t *NVRAM, uint32_t val)
189 180 {
190   - m48t59_t *NVRAM = opaque;
191 181 struct tm tm;
192 182 int tmp;
193 183  
... ... @@ -333,9 +323,8 @@ void m48t59_write (void *opaque, uint32_t val)
333 323 }
334 324 }
335 325  
336   -uint32_t m48t59_read (void *opaque)
  326 +uint32_t m48t59_read (m48t59_t *NVRAM)
337 327 {
338   - m48t59_t *NVRAM = opaque;
339 328 struct tm tm;
340 329 uint32_t retval = 0xFF;
341 330  
... ... @@ -418,10 +407,8 @@ uint32_t m48t59_read (void *opaque)
418 407 return retval;
419 408 }
420 409  
421   -void m48t59_set_addr (void *opaque, uint32_t addr)
  410 +void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr)
422 411 {
423   - m48t59_t *NVRAM = opaque;
424   -
425 412 NVRAM->addr = addr;
426 413 }
427 414  
... ... @@ -460,27 +447,25 @@ static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
460 447 }
461 448  
462 449 /* Initialisation routine */
463   -void *m48t59_init (int IRQ, uint32_t io_base, uint16_t size)
  450 +m48t59_t *m48t59_init (int IRQ, uint32_t io_base, uint16_t size)
464 451 {
465   - m48t59_t *tmp;
  452 + m48t59_t *s;
466 453  
467   - tmp = realloc(NVRAMs, (nb_NVRAMs + 1) * sizeof(m48t59_t));
468   - if (tmp == NULL)
  454 + s = qemu_mallocz(sizeof(m48t59_t));
  455 + if (!s)
469 456 return NULL;
470   - NVRAMs = tmp;
471   - tmp[nb_NVRAMs].buffer = malloc(size);
472   - if (tmp[nb_NVRAMs].buffer == NULL)
473   - return NULL;
474   - memset(tmp[nb_NVRAMs].buffer, 0, size);
475   - tmp[nb_NVRAMs].IRQ = IRQ;
476   - tmp[nb_NVRAMs].size = size;
477   - tmp[nb_NVRAMs].io_base = io_base;
478   - tmp[nb_NVRAMs].addr = 0;
479   - register_ioport_read(io_base, 0x04, 1, NVRAM_readb, &NVRAMs[nb_NVRAMs]);
480   - register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, &NVRAMs[nb_NVRAMs]);
481   - tmp[nb_NVRAMs].alrm_timer = qemu_new_timer(vm_clock, &alarm_cb,
482   - &tmp[nb_NVRAMs]);
483   - tmp[nb_NVRAMs].wd_timer = qemu_new_timer(vm_clock, &watchdog_cb,
484   - &tmp[nb_NVRAMs]);
485   - return &NVRAMs[nb_NVRAMs++];
  457 + s->buffer = qemu_mallocz(size);
  458 + if (!s->buffer) {
  459 + qemu_free(s);
  460 + return NULL;
  461 + }
  462 + s->IRQ = IRQ;
  463 + s->size = size;
  464 + s->io_base = io_base;
  465 + s->addr = 0;
  466 + register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
  467 + register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
  468 + s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
  469 + s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
  470 + return s;
486 471 }
... ...
hw/m48t59.h
  View file @c5df018
1 1 #if !defined (__M48T59_H__)
2 2 #define __M48T59_H__
3 3  
4   -void m48t59_write (void *opaque, uint32_t val);
5   -uint32_t m48t59_read (void *opaque);
6   -void m48t59_set_addr (void *opaque, uint32_t addr);
7   -void *m48t59_init (int IRQ, uint32_t io_base, uint16_t size);
  4 +typedef struct m48t59_t m48t59_t;
  5 +
  6 +void m48t59_write (m48t59_t *NVRAM, uint32_t val);
  7 +uint32_t m48t59_read (m48t59_t *NVRAM);
  8 +void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr);
  9 +m48t59_t *m48t59_init (int IRQ, uint32_t io_base, uint16_t size);
8 10  
9 11 #endif /* !defined (__M48T59_H__) */
... ...
hw/ppc.c
  View file @c5df018
... ... @@ -21,8 +21,6 @@
21 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 22 * THE SOFTWARE.
23 23 */
24   -
25   -#include <stdio.h>
26 24 #include "vl.h"
27 25  
28 26 void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
... ...
hw/ppc_prep.c
  View file @c5df018
... ... @@ -21,26 +21,6 @@
21 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 22 * THE SOFTWARE.
23 23 */
24   -#include <stdlib.h>
25   -#include <stdio.h>
26   -#include <stdarg.h>
27   -#include <string.h>
28   -#include <getopt.h>
29   -#include <inttypes.h>
30   -#include <unistd.h>
31   -#include <sys/mman.h>
32   -#include <fcntl.h>
33   -#include <signal.h>
34   -#include <time.h>
35   -#include <sys/time.h>
36   -#include <malloc.h>
37   -#include <termios.h>
38   -#include <sys/poll.h>
39   -#include <errno.h>
40   -#include <sys/wait.h>
41   -#include <netinet/in.h>
42   -
43   -#include "cpu.h"
44 24 #include "vl.h"
45 25 #include "m48t59.h"
46 26  
... ... @@ -209,8 +189,6 @@ static CPUReadMemoryFunc *PPC_io_read[] = {
209 189 &PPC_io_readl,
210 190 };
211 191  
212   -uint32_t pic_intack_read(CPUState *env);
213   -
214 192 /* Read-only register (?) */
215 193 static void _PPC_ioB_write (uint32_t addr, uint32_t value, uint32_t vaddr)
216 194 {
... ... @@ -368,63 +346,63 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
368 346 #define NVRAM_OSAREA_SIZE 512
369 347 #define NVRAM_CONFSIZE 1024
370 348  
371   -static inline void NVRAM_set_byte (void *opaque, uint32_t addr, uint8_t value)
  349 +static inline void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
372 350 {
373   - m48t59_set_addr(opaque, addr);
374   - m48t59_write(opaque, value);
  351 + m48t59_set_addr(nvram, addr);
  352 + m48t59_write(nvram, value);
375 353 }
376 354  
377   -static inline uint8_t NVRAM_get_byte (void *opaque, uint32_t addr)
  355 +static inline uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
378 356 {
379   - m48t59_set_addr(opaque, addr);
380   - return m48t59_read(opaque);
  357 + m48t59_set_addr(nvram, addr);
  358 + return m48t59_read(nvram);
381 359 }
382 360  
383   -static inline void NVRAM_set_word (void *opaque, uint32_t addr, uint16_t value)
  361 +static inline void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
384 362 {
385   - m48t59_set_addr(opaque, addr);
386   - m48t59_write(opaque, value >> 8);
387   - m48t59_set_addr(opaque, addr + 1);
388   - m48t59_write(opaque, value & 0xFF);
  363 + m48t59_set_addr(nvram, addr);
  364 + m48t59_write(nvram, value >> 8);
  365 + m48t59_set_addr(nvram, addr + 1);
  366 + m48t59_write(nvram, value & 0xFF);
389 367 }
390 368  
391   -static inline uint16_t NVRAM_get_word (void *opaque, uint32_t addr)
  369 +static inline uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
392 370 {
393 371 uint16_t tmp;
394 372  
395   - m48t59_set_addr(opaque, addr);
396   - tmp = m48t59_read(opaque) << 8;
397   - m48t59_set_addr(opaque, addr + 1);
398   - tmp |= m48t59_read(opaque);
  373 + m48t59_set_addr(nvram, addr);
  374 + tmp = m48t59_read(nvram) << 8;
  375 + m48t59_set_addr(nvram, addr + 1);
  376 + tmp |= m48t59_read(nvram);
399 377  
400 378 return tmp;
401 379 }
402 380  
403   -static inline void NVRAM_set_lword (void *opaque, uint32_t addr,
  381 +static inline void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr,
404 382 uint32_t value)
405 383 {
406   - m48t59_set_addr(opaque, addr);
407   - m48t59_write(opaque, value >> 24);
408   - m48t59_set_addr(opaque, addr + 1);
409   - m48t59_write(opaque, (value >> 16) & 0xFF);
410   - m48t59_set_addr(opaque, addr + 2);
411   - m48t59_write(opaque, (value >> 8) & 0xFF);
412   - m48t59_set_addr(opaque, addr + 3);
413   - m48t59_write(opaque, value & 0xFF);
  384 + m48t59_set_addr(nvram, addr);
  385 + m48t59_write(nvram, value >> 24);
  386 + m48t59_set_addr(nvram, addr + 1);
  387 + m48t59_write(nvram, (value >> 16) & 0xFF);
  388 + m48t59_set_addr(nvram, addr + 2);
  389 + m48t59_write(nvram, (value >> 8) & 0xFF);
  390 + m48t59_set_addr(nvram, addr + 3);
  391 + m48t59_write(nvram, value & 0xFF);
414 392 }
415 393  
416   -static inline uint32_t NVRAM_get_lword (void *opaque, uint32_t addr)
  394 +static inline uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
417 395 {
418 396 uint32_t tmp;
419 397  
420   - m48t59_set_addr(opaque, addr);
421   - tmp = m48t59_read(opaque) << 24;
422   - m48t59_set_addr(opaque, addr + 1);
423   - tmp |= m48t59_read(opaque) << 16;
424   - m48t59_set_addr(opaque, addr + 2);
425   - tmp |= m48t59_read(opaque) << 8;
426   - m48t59_set_addr(opaque, addr + 3);
427   - tmp |= m48t59_read(opaque);
  398 + m48t59_set_addr(nvram, addr);
  399 + tmp = m48t59_read(nvram) << 24;
  400 + m48t59_set_addr(nvram, addr + 1);
  401 + tmp |= m48t59_read(nvram) << 16;
  402 + m48t59_set_addr(nvram, addr + 2);
  403 + tmp |= m48t59_read(nvram) << 8;
  404 + m48t59_set_addr(nvram, addr + 3);
  405 + tmp |= m48t59_read(nvram);
428 406  
429 407 return tmp;
430 408 }
... ... @@ -444,7 +422,7 @@ static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
444 422 return tmp;
445 423 }
446 424  
447   -static void NVRAM_set_crc (void *opaque, uint32_t addr,
  425 +static void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
448 426 uint32_t start, uint32_t count)
449 427 {
450 428 uint32_t i;
... ... @@ -455,74 +433,74 @@ static void NVRAM_set_crc (void *opaque, uint32_t addr,
455 433 odd = 1;
456 434 count &= ~1;
457 435 for (i = 0; i != count; i++) {
458   - crc = NVRAM_crc_update(crc, NVRAM_get_word(opaque, start + i));
  436 + crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
459 437 }
460 438 if (odd) {
461   - crc = NVRAM_crc_update(crc, NVRAM_get_byte(opaque, start + i) << 8);
  439 + crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
462 440 }
463   - NVRAM_set_word(opaque, addr, crc);
  441 + NVRAM_set_word(nvram, addr, crc);
464 442 }
465 443  
466 444 static void prep_NVRAM_init (void)
467 445 {
468   - void *opaque;
  446 + m48t59_t *nvram;
469 447  
470   - opaque = m48t59_init(8, 0x0074, NVRAM_SIZE);
  448 + nvram = m48t59_init(8, 0x0074, NVRAM_SIZE);
471 449 /* NVRAM header */
472 450 /* 0x00: NVRAM size in kB */
473   - NVRAM_set_word(opaque, 0x00, NVRAM_SIZE >> 10);
  451 + NVRAM_set_word(nvram, 0x00, NVRAM_SIZE >> 10);
474 452 /* 0x02: NVRAM version */
475   - NVRAM_set_byte(opaque, 0x02, 0x01);
  453 + NVRAM_set_byte(nvram, 0x02, 0x01);
476 454 /* 0x03: NVRAM revision */
477   - NVRAM_set_byte(opaque, 0x03, 0x01);
  455 + NVRAM_set_byte(nvram, 0x03, 0x01);
478 456 /* 0x08: last OS */
479   - NVRAM_set_byte(opaque, 0x08, 0x00); /* Unknown */
  457 + NVRAM_set_byte(nvram, 0x08, 0x00); /* Unknown */
480 458 /* 0x09: endian */
481   - NVRAM_set_byte(opaque, 0x09, 'B'); /* Big-endian */
  459 + NVRAM_set_byte(nvram, 0x09, 'B'); /* Big-endian */
482 460 /* 0x0A: OSArea usage */
483   - NVRAM_set_byte(opaque, 0x0A, 0x00); /* Empty */
  461 + NVRAM_set_byte(nvram, 0x0A, 0x00); /* Empty */
484 462 /* 0x0B: PM mode */
485   - NVRAM_set_byte(opaque, 0x0B, 0x00); /* Normal */
  463 + NVRAM_set_byte(nvram, 0x0B, 0x00); /* Normal */
486 464 /* Restart block description record */
487 465 /* 0x0C: restart block version */
488   - NVRAM_set_word(opaque, 0x0C, 0x01);
  466 + NVRAM_set_word(nvram, 0x0C, 0x01);
489 467 /* 0x0E: restart block revision */
490   - NVRAM_set_word(opaque, 0x0E, 0x01);
  468 + NVRAM_set_word(nvram, 0x0E, 0x01);
491 469 /* 0x20: restart address */
492   - NVRAM_set_lword(opaque, 0x20, 0x00);
  470 + NVRAM_set_lword(nvram, 0x20, 0x00);
493 471 /* 0x24: save area address */
494   - NVRAM_set_lword(opaque, 0x24, 0x00);
  472 + NVRAM_set_lword(nvram, 0x24, 0x00);
495 473 /* 0x28: save area length */
496   - NVRAM_set_lword(opaque, 0x28, 0x00);
  474 + NVRAM_set_lword(nvram, 0x28, 0x00);
497 475 /* 0x1C: checksum of restart block */
498   - NVRAM_set_crc(opaque, 0x1C, 0x0C, 32);
  476 + NVRAM_set_crc(nvram, 0x1C, 0x0C, 32);
499 477  
500 478 /* Security section */
501 479 /* Set all to zero */
502 480 /* 0xC4: pointer to global environment area */
503   - NVRAM_set_lword(opaque, 0xC4, 0x0100);
  481 + NVRAM_set_lword(nvram, 0xC4, 0x0100);
504 482 /* 0xC8: size of global environment area */
505   - NVRAM_set_lword(opaque, 0xC8,
  483 + NVRAM_set_lword(nvram, 0xC8,
506 484 NVRAM_END - NVRAM_OSAREA_SIZE - NVRAM_CONFSIZE - 0x0100);
507 485 /* 0xD4: pointer to configuration area */
508   - NVRAM_set_lword(opaque, 0xD4, NVRAM_END - NVRAM_CONFSIZE);
  486 + NVRAM_set_lword(nvram, 0xD4, NVRAM_END - NVRAM_CONFSIZE);
509 487 /* 0xD8: size of configuration area */
510   - NVRAM_set_lword(opaque, 0xD8, NVRAM_CONFSIZE);
  488 + NVRAM_set_lword(nvram, 0xD8, NVRAM_CONFSIZE);
511 489 /* 0xE8: pointer to OS specific area */
512   - NVRAM_set_lword(opaque, 0xE8,
  490 + NVRAM_set_lword(nvram, 0xE8,
513 491 NVRAM_END - NVRAM_CONFSIZE - NVRAM_OSAREA_SIZE);
514 492 /* 0xD8: size of OS specific area */
515   - NVRAM_set_lword(opaque, 0xEC, NVRAM_OSAREA_SIZE);
  493 + NVRAM_set_lword(nvram, 0xEC, NVRAM_OSAREA_SIZE);
516 494  
517 495 /* Configuration area */
518 496 /* RTC init */
519   - // NVRAM_set_lword(opaque, 0x1FFC, 0x50);
  497 + // NVRAM_set_lword(nvram, 0x1FFC, 0x50);
520 498  
521 499 /* 0x04: checksum 0 => OS area */
522   - NVRAM_set_crc(opaque, 0x04, 0x00,
  500 + NVRAM_set_crc(nvram, 0x04, 0x00,
523 501 NVRAM_END - NVRAM_CONFSIZE - NVRAM_OSAREA_SIZE);
524 502 /* 0x06: checksum of config area */
525   - NVRAM_set_crc(opaque, 0x06, NVRAM_END - NVRAM_CONFSIZE, NVRAM_CONFSIZE);
  503 + NVRAM_set_crc(nvram, 0x06, NVRAM_END - NVRAM_CONFSIZE, NVRAM_CONFSIZE);
526 504 }
527 505  
528 506 int load_initrd (const char *filename, uint8_t *addr)
... ...
... ... @@ -416,6 +416,7 @@ void serial_receive_break(SerialState *s);
416 416  
417 417 void pic_set_irq(int irq, int level);
418 418 void pic_init(void);
  419 +uint32_t pic_intack_read(CPUState *env);
419 420  
420 421 /* i8254.c */
421 422  
... ...