gwj / at91sam9263 · Commits

Commit c588de3d27e442687121379efc26b36d89ee953f

Authored by balrog
1 parent d361be25

omap1: add OSC_12M_SEL UART register support (original patch from Jean-Christophe PLAGNIOL-VILLARD) 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5905 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 17 additions and 10 deletions
hw/omap1.c
  View file @c588de3
... ... @@ -1966,6 +1966,7 @@ struct omap_uart_s {
1966 1966 uint8_t cfps;
1967 1967 uint8_t mdr[2];
1968 1968 uint8_t scr;
  1969 + uint8_t clksel;
1969 1970 };
1970 1971  
1971 1972 void omap_uart_reset(struct omap_uart_s *s)
... ... @@ -1974,6 +1975,7 @@ void omap_uart_reset(struct omap_uart_s *s)
1974 1975 s->syscontrol = 0;
1975 1976 s->wkup = 0x3f;
1976 1977 s->cfps = 0x69;
  1978 + s->clksel = 0;
1977 1979 }
1978 1980  
1979 1981 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
... ... @@ -2006,17 +2008,19 @@ static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
2006 2008 return s->scr;
2007 2009 case 0x44: /* SSR */
2008 2010 return 0x0;
2009   - case 0x48: /* EBLR */
  2011 + case 0x48: /* EBLR (OMAP2) */
2010 2012 return s->eblr;
  2013 + case 0x4C: /* OSC_12M_SEL (OMAP1) */
  2014 + return s->clksel;
2011 2015 case 0x50: /* MVR */
2012 2016 return 0x30;
2013   - case 0x54: /* SYSC */
  2017 + case 0x54: /* SYSC (OMAP2) */
2014 2018 return s->syscontrol;
2015   - case 0x58: /* SYSS */
  2019 + case 0x58: /* SYSS (OMAP2) */
2016 2020 return 1;
2017   - case 0x5c: /* WER */
  2021 + case 0x5c: /* WER (OMAP2) */
2018 2022 return s->wkup;
2019   - case 0x60: /* CFPS */
  2023 + case 0x60: /* CFPS (OMAP2) */
2020 2024 return s->cfps;
2021 2025 }
2022 2026  
... ... @@ -2040,23 +2044,26 @@ static void omap_uart_write(void *opaque, target_phys_addr_t addr,
2040 2044 case 0x40: /* SCR */
2041 2045 s->scr = value & 0xff;
2042 2046 break;
2043   - case 0x48: /* EBLR */
  2047 + case 0x48: /* EBLR (OMAP2) */
2044 2048 s->eblr = value & 0xff;
2045 2049 break;
  2050 + case 0x4C: /* OSC_12M_SEL (OMAP1) */
  2051 + s->clksel = value & 1;
  2052 + break;
2046 2053 case 0x44: /* SSR */
2047 2054 case 0x50: /* MVR */
2048   - case 0x58: /* SYSS */
  2055 + case 0x58: /* SYSS (OMAP2) */
2049 2056 OMAP_RO_REG(addr);
2050 2057 break;
2051   - case 0x54: /* SYSC */
  2058 + case 0x54: /* SYSC (OMAP2) */
2052 2059 s->syscontrol = value & 0x1d;
2053 2060 if (value & 2)
2054 2061 omap_uart_reset(s);
2055 2062 break;
2056   - case 0x5c: /* WER */
  2063 + case 0x5c: /* WER (OMAP2) */
2057 2064 s->wkup = value & 0x7f;
2058 2065 break;
2059   - case 0x60: /* CFPS */
  2066 + case 0x60: /* CFPS (OMAP2) */
2060 2067 s->cfps = value & 0xff;
2061 2068 break;
2062 2069 default:
... ...