gwj / at91sam9263 · Commits

Commit c48fcb47518befb79b5cc75a2cad024c2d6e4bef

Authored by blueswir1
1 parent 1d8cde5b

Move CPU stuff unrelated to translation to helper.c 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4133 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 524 additions and 520 deletions
target-sparc/cpu.h
  View file @c48fcb4
@@ -286,6 +286,7 @@ typedef struct CPUSPARCState { @@ -286,6 +286,7 @@ typedef struct CPUSPARCState {
286 #endif 286 #endif
287 287
288 CPUSPARCState *cpu_sparc_init(const char *cpu_model); 288 CPUSPARCState *cpu_sparc_init(const char *cpu_model);
  289 +void gen_intermediate_code_init(CPUSPARCState *env);
289 int cpu_sparc_exec(CPUSPARCState *s); 290 int cpu_sparc_exec(CPUSPARCState *s);
290 int cpu_sparc_close(CPUSPARCState *s); 291 int cpu_sparc_close(CPUSPARCState *s);
291 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, 292 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
target-sparc/helper.c
  View file @c48fcb4
@@ -30,6 +30,22 @@ @@ -30,6 +30,22 @@
30 30
31 //#define DEBUG_MMU 31 //#define DEBUG_MMU
32 32
  33 +typedef struct sparc_def_t sparc_def_t;
  34 +
  35 +struct sparc_def_t {
  36 + const unsigned char *name;
  37 + target_ulong iu_version;
  38 + uint32_t fpu_version;
  39 + uint32_t mmu_version;
  40 + uint32_t mmu_bm;
  41 + uint32_t mmu_ctpr_mask;
  42 + uint32_t mmu_cxr_mask;
  43 + uint32_t mmu_sfsr_mask;
  44 + uint32_t mmu_trcr_mask;
  45 +};
  46 +
  47 +static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);
  48 +
33 /* Sparc MMU emulation */ 49 /* Sparc MMU emulation */
34 50
35 /* thread support */ 51 /* thread support */
@@ -98,9 +114,9 @@ static const int perm_table[2][8] = { @@ -98,9 +114,9 @@ static const int perm_table[2][8] = {
98 } 114 }
99 }; 115 };
100 116
101 -int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,  
102 - int *access_index, target_ulong address, int rw,  
103 - int mmu_idx) 117 +static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
  118 + int *prot, int *access_index,
  119 + target_ulong address, int rw, int mmu_idx)
104 { 120 {
105 int access_perms = 0; 121 int access_perms = 0;
106 target_phys_addr_t pde_ptr; 122 target_phys_addr_t pde_ptr;
@@ -483,9 +499,9 @@ static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical @@ -483,9 +499,9 @@ static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical
483 return 1; 499 return 1;
484 } 500 }
485 501
486 -int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,  
487 - int *access_index, target_ulong address, int rw,  
488 - int mmu_idx) 502 +static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
  503 + int *prot, int *access_index,
  504 + target_ulong address, int rw, int mmu_idx)
489 { 505 {
490 int is_user = mmu_idx == MMU_USER_IDX; 506 int is_user = mmu_idx == MMU_USER_IDX;
491 507
@@ -593,6 +609,30 @@ void dump_mmu(CPUState *env) @@ -593,6 +609,30 @@ void dump_mmu(CPUState *env)
593 #endif /* TARGET_SPARC64 */ 609 #endif /* TARGET_SPARC64 */
594 #endif /* !CONFIG_USER_ONLY */ 610 #endif /* !CONFIG_USER_ONLY */
595 611
  612 +
  613 +#if defined(CONFIG_USER_ONLY)
  614 +target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
  615 +{
  616 + return addr;
  617 +}
  618 +
  619 +#else
  620 +target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
  621 +{
  622 + target_phys_addr_t phys_addr;
  623 + int prot, access_index;
  624 +
  625 + if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
  626 + MMU_KERNEL_IDX) != 0)
  627 + if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
  628 + 0, MMU_KERNEL_IDX) != 0)
  629 + return -1;
  630 + if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
  631 + return -1;
  632 + return phys_addr;
  633 +}
  634 +#endif
  635 +
596 void memcpy32(target_ulong *dst, const target_ulong *src) 636 void memcpy32(target_ulong *dst, const target_ulong *src)
597 { 637 {
598 dst[0] = src[0]; 638 dst[0] = src[0];
@@ -605,6 +645,481 @@ void memcpy32(target_ulong *dst, const target_ulong *src) @@ -605,6 +645,481 @@ void memcpy32(target_ulong *dst, const target_ulong *src)
605 dst[7] = src[7]; 645 dst[7] = src[7];
606 } 646 }
607 647
  648 +void helper_flush(target_ulong addr)
  649 +{
  650 + addr &= ~7;
  651 + tb_invalidate_page_range(addr, addr + 8);
  652 +}
  653 +
  654 +void cpu_reset(CPUSPARCState *env)
  655 +{
  656 + tlb_flush(env, 1);
  657 + env->cwp = 0;
  658 + env->wim = 1;
  659 + env->regwptr = env->regbase + (env->cwp * 16);
  660 +#if defined(CONFIG_USER_ONLY)
  661 + env->user_mode_only = 1;
  662 +#ifdef TARGET_SPARC64
  663 + env->cleanwin = NWINDOWS - 2;
  664 + env->cansave = NWINDOWS - 2;
  665 + env->pstate = PS_RMO | PS_PEF | PS_IE;
  666 + env->asi = 0x82; // Primary no-fault
  667 +#endif
  668 +#else
  669 + env->psret = 0;
  670 + env->psrs = 1;
  671 + env->psrps = 1;
  672 +#ifdef TARGET_SPARC64
  673 + env->pstate = PS_PRIV;
  674 + env->hpstate = HS_PRIV;
  675 + env->pc = 0x1fff0000000ULL;
  676 + env->tsptr = &env->ts[env->tl];
  677 +#else
  678 + env->pc = 0;
  679 + env->mmuregs[0] &= ~(MMU_E | MMU_NF);
  680 + env->mmuregs[0] |= env->mmu_bm;
  681 +#endif
  682 + env->npc = env->pc + 4;
  683 +#endif
  684 +}
  685 +
  686 +CPUSPARCState *cpu_sparc_init(const char *cpu_model)
  687 +{
  688 + CPUSPARCState *env;
  689 + const sparc_def_t *def;
  690 +
  691 + def = cpu_sparc_find_by_name(cpu_model);
  692 + if (!def)
  693 + return NULL;
  694 +
  695 + env = qemu_mallocz(sizeof(CPUSPARCState));
  696 + if (!env)
  697 + return NULL;
  698 + cpu_exec_init(env);
  699 + env->cpu_model_str = cpu_model;
  700 + env->version = def->iu_version;
  701 + env->fsr = def->fpu_version;
  702 +#if !defined(TARGET_SPARC64)
  703 + env->mmu_bm = def->mmu_bm;
  704 + env->mmu_ctpr_mask = def->mmu_ctpr_mask;
  705 + env->mmu_cxr_mask = def->mmu_cxr_mask;
  706 + env->mmu_sfsr_mask = def->mmu_sfsr_mask;
  707 + env->mmu_trcr_mask = def->mmu_trcr_mask;
  708 + env->mmuregs[0] |= def->mmu_version;
  709 + cpu_sparc_set_id(env, 0);
  710 +#endif
  711 +
  712 + gen_intermediate_code_init(env);
  713 +
  714 + cpu_reset(env);
  715 +
  716 + return env;
  717 +}
  718 +
  719 +void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
  720 +{
  721 +#if !defined(TARGET_SPARC64)
  722 + env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
  723 +#endif
  724 +}
  725 +
  726 +static const sparc_def_t sparc_defs[] = {
  727 +#ifdef TARGET_SPARC64
  728 + {
  729 + .name = "Fujitsu Sparc64",
  730 + .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
  731 + | (MAXTL << 8) | (NWINDOWS - 1)),
  732 + .fpu_version = 0x00000000,
  733 + .mmu_version = 0,
  734 + },
  735 + {
  736 + .name = "Fujitsu Sparc64 III",
  737 + .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
  738 + | (MAXTL << 8) | (NWINDOWS - 1)),
  739 + .fpu_version = 0x00000000,
  740 + .mmu_version = 0,
  741 + },
  742 + {
  743 + .name = "Fujitsu Sparc64 IV",
  744 + .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
  745 + | (MAXTL << 8) | (NWINDOWS - 1)),
  746 + .fpu_version = 0x00000000,
  747 + .mmu_version = 0,
  748 + },
  749 + {
  750 + .name = "Fujitsu Sparc64 V",
  751 + .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
  752 + | (MAXTL << 8) | (NWINDOWS - 1)),
  753 + .fpu_version = 0x00000000,
  754 + .mmu_version = 0,
  755 + },
  756 + {
  757 + .name = "TI UltraSparc I",
  758 + .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
  759 + | (MAXTL << 8) | (NWINDOWS - 1)),
  760 + .fpu_version = 0x00000000,
  761 + .mmu_version = 0,
  762 + },
  763 + {
  764 + .name = "TI UltraSparc II",
  765 + .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
  766 + | (MAXTL << 8) | (NWINDOWS - 1)),
  767 + .fpu_version = 0x00000000,
  768 + .mmu_version = 0,
  769 + },
  770 + {
  771 + .name = "TI UltraSparc IIi",
  772 + .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
  773 + | (MAXTL << 8) | (NWINDOWS - 1)),
  774 + .fpu_version = 0x00000000,
  775 + .mmu_version = 0,
  776 + },
  777 + {
  778 + .name = "TI UltraSparc IIe",
  779 + .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
  780 + | (MAXTL << 8) | (NWINDOWS - 1)),
  781 + .fpu_version = 0x00000000,
  782 + .mmu_version = 0,
  783 + },
  784 + {
  785 + .name = "Sun UltraSparc III",
  786 + .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
  787 + | (MAXTL << 8) | (NWINDOWS - 1)),
  788 + .fpu_version = 0x00000000,
  789 + .mmu_version = 0,
  790 + },
  791 + {
  792 + .name = "Sun UltraSparc III Cu",
  793 + .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
  794 + | (MAXTL << 8) | (NWINDOWS - 1)),
  795 + .fpu_version = 0x00000000,
  796 + .mmu_version = 0,
  797 + },
  798 + {
  799 + .name = "Sun UltraSparc IIIi",
  800 + .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
  801 + | (MAXTL << 8) | (NWINDOWS - 1)),
  802 + .fpu_version = 0x00000000,
  803 + .mmu_version = 0,
  804 + },
  805 + {
  806 + .name = "Sun UltraSparc IV",
  807 + .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
  808 + | (MAXTL << 8) | (NWINDOWS - 1)),
  809 + .fpu_version = 0x00000000,
  810 + .mmu_version = 0,
  811 + },
  812 + {
  813 + .name = "Sun UltraSparc IV+",
  814 + .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
  815 + | (MAXTL << 8) | (NWINDOWS - 1)),
  816 + .fpu_version = 0x00000000,
  817 + .mmu_version = 0,
  818 + },
  819 + {
  820 + .name = "Sun UltraSparc IIIi+",
  821 + .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
  822 + | (MAXTL << 8) | (NWINDOWS - 1)),
  823 + .fpu_version = 0x00000000,
  824 + .mmu_version = 0,
  825 + },
  826 + {
  827 + .name = "NEC UltraSparc I",
  828 + .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
  829 + | (MAXTL << 8) | (NWINDOWS - 1)),
  830 + .fpu_version = 0x00000000,
  831 + .mmu_version = 0,
  832 + },
  833 +#else
  834 + {
  835 + .name = "Fujitsu MB86900",
  836 + .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
  837 + .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
  838 + .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
  839 + .mmu_bm = 0x00004000,
  840 + .mmu_ctpr_mask = 0x007ffff0,
  841 + .mmu_cxr_mask = 0x0000003f,
  842 + .mmu_sfsr_mask = 0xffffffff,
  843 + .mmu_trcr_mask = 0xffffffff,
  844 + },
  845 + {
  846 + .name = "Fujitsu MB86904",
  847 + .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
  848 + .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
  849 + .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
  850 + .mmu_bm = 0x00004000,
  851 + .mmu_ctpr_mask = 0x00ffffc0,
  852 + .mmu_cxr_mask = 0x000000ff,
  853 + .mmu_sfsr_mask = 0x00016fff,
  854 + .mmu_trcr_mask = 0x00ffffff,
  855 + },
  856 + {
  857 + .name = "Fujitsu MB86907",
  858 + .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
  859 + .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
  860 + .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
  861 + .mmu_bm = 0x00004000,
  862 + .mmu_ctpr_mask = 0xffffffc0,
  863 + .mmu_cxr_mask = 0x000000ff,
  864 + .mmu_sfsr_mask = 0x00016fff,
  865 + .mmu_trcr_mask = 0xffffffff,
  866 + },
  867 + {
  868 + .name = "LSI L64811",
  869 + .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
  870 + .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
  871 + .mmu_version = 0x10 << 24,
  872 + .mmu_bm = 0x00004000,
  873 + .mmu_ctpr_mask = 0x007ffff0,
  874 + .mmu_cxr_mask = 0x0000003f,
  875 + .mmu_sfsr_mask = 0xffffffff,
  876 + .mmu_trcr_mask = 0xffffffff,
  877 + },
  878 + {
  879 + .name = "Cypress CY7C601",
  880 + .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
  881 + .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
  882 + .mmu_version = 0x10 << 24,
  883 + .mmu_bm = 0x00004000,
  884 + .mmu_ctpr_mask = 0x007ffff0,
  885 + .mmu_cxr_mask = 0x0000003f,
  886 + .mmu_sfsr_mask = 0xffffffff,
  887 + .mmu_trcr_mask = 0xffffffff,
  888 + },
  889 + {
  890 + .name = "Cypress CY7C611",
  891 + .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
  892 + .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
  893 + .mmu_version = 0x10 << 24,
  894 + .mmu_bm = 0x00004000,
  895 + .mmu_ctpr_mask = 0x007ffff0,
  896 + .mmu_cxr_mask = 0x0000003f,
  897 + .mmu_sfsr_mask = 0xffffffff,
  898 + .mmu_trcr_mask = 0xffffffff,
  899 + },
  900 + {
  901 + .name = "TI SuperSparc II",
  902 + .iu_version = 0x40000000,
  903 + .fpu_version = 0 << 17,
  904 + .mmu_version = 0x04000000,
  905 + .mmu_bm = 0x00002000,
  906 + .mmu_ctpr_mask = 0xffffffc0,
  907 + .mmu_cxr_mask = 0x0000ffff,
  908 + .mmu_sfsr_mask = 0xffffffff,
  909 + .mmu_trcr_mask = 0xffffffff,
  910 + },
  911 + {
  912 + .name = "TI MicroSparc I",
  913 + .iu_version = 0x41000000,
  914 + .fpu_version = 4 << 17,
  915 + .mmu_version = 0x41000000,
  916 + .mmu_bm = 0x00004000,
  917 + .mmu_ctpr_mask = 0x007ffff0,
  918 + .mmu_cxr_mask = 0x0000003f,
  919 + .mmu_sfsr_mask = 0x00016fff,
  920 + .mmu_trcr_mask = 0x0000003f,
  921 + },
  922 + {
  923 + .name = "TI MicroSparc II",
  924 + .iu_version = 0x42000000,
  925 + .fpu_version = 4 << 17,
  926 + .mmu_version = 0x02000000,
  927 + .mmu_bm = 0x00004000,
  928 + .mmu_ctpr_mask = 0x00ffffc0,
  929 + .mmu_cxr_mask = 0x000000ff,
  930 + .mmu_sfsr_mask = 0x00016fff,
  931 + .mmu_trcr_mask = 0x00ffffff,
  932 + },
  933 + {
  934 + .name = "TI MicroSparc IIep",
  935 + .iu_version = 0x42000000,
  936 + .fpu_version = 4 << 17,
  937 + .mmu_version = 0x04000000,
  938 + .mmu_bm = 0x00004000,
  939 + .mmu_ctpr_mask = 0x00ffffc0,
  940 + .mmu_cxr_mask = 0x000000ff,
  941 + .mmu_sfsr_mask = 0x00016bff,
  942 + .mmu_trcr_mask = 0x00ffffff,
  943 + },
  944 + {
  945 + .name = "TI SuperSparc 51",
  946 + .iu_version = 0x43000000,
  947 + .fpu_version = 0 << 17,
  948 + .mmu_version = 0x04000000,
  949 + .mmu_bm = 0x00002000,
  950 + .mmu_ctpr_mask = 0xffffffc0,
  951 + .mmu_cxr_mask = 0x0000ffff,
  952 + .mmu_sfsr_mask = 0xffffffff,
  953 + .mmu_trcr_mask = 0xffffffff,
  954 + },
  955 + {
  956 + .name = "TI SuperSparc 61",
  957 + .iu_version = 0x44000000,
  958 + .fpu_version = 0 << 17,
  959 + .mmu_version = 0x04000000,
  960 + .mmu_bm = 0x00002000,
  961 + .mmu_ctpr_mask = 0xffffffc0,
  962 + .mmu_cxr_mask = 0x0000ffff,
  963 + .mmu_sfsr_mask = 0xffffffff,
  964 + .mmu_trcr_mask = 0xffffffff,
  965 + },
  966 + {
  967 + .name = "Ross RT625",
  968 + .iu_version = 0x1e000000,
  969 + .fpu_version = 1 << 17,
  970 + .mmu_version = 0x1e000000,
  971 + .mmu_bm = 0x00004000,
  972 + .mmu_ctpr_mask = 0x007ffff0,
  973 + .mmu_cxr_mask = 0x0000003f,
  974 + .mmu_sfsr_mask = 0xffffffff,
  975 + .mmu_trcr_mask = 0xffffffff,
  976 + },
  977 + {
  978 + .name = "Ross RT620",
  979 + .iu_version = 0x1f000000,
  980 + .fpu_version = 1 << 17,
  981 + .mmu_version = 0x1f000000,
  982 + .mmu_bm = 0x00004000,
  983 + .mmu_ctpr_mask = 0x007ffff0,
  984 + .mmu_cxr_mask = 0x0000003f,
  985 + .mmu_sfsr_mask = 0xffffffff,
  986 + .mmu_trcr_mask = 0xffffffff,
  987 + },
  988 + {
  989 + .name = "BIT B5010",
  990 + .iu_version = 0x20000000,
  991 + .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
  992 + .mmu_version = 0x20000000,
  993 + .mmu_bm = 0x00004000,
  994 + .mmu_ctpr_mask = 0x007ffff0,
  995 + .mmu_cxr_mask = 0x0000003f,
  996 + .mmu_sfsr_mask = 0xffffffff,
  997 + .mmu_trcr_mask = 0xffffffff,
  998 + },
  999 + {
  1000 + .name = "Matsushita MN10501",
  1001 + .iu_version = 0x50000000,
  1002 + .fpu_version = 0 << 17,
  1003 + .mmu_version = 0x50000000,
  1004 + .mmu_bm = 0x00004000,
  1005 + .mmu_ctpr_mask = 0x007ffff0,
  1006 + .mmu_cxr_mask = 0x0000003f,
  1007 + .mmu_sfsr_mask = 0xffffffff,
  1008 + .mmu_trcr_mask = 0xffffffff,
  1009 + },
  1010 + {
  1011 + .name = "Weitek W8601",
  1012 + .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
  1013 + .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
  1014 + .mmu_version = 0x10 << 24,
  1015 + .mmu_bm = 0x00004000,
  1016 + .mmu_ctpr_mask = 0x007ffff0,
  1017 + .mmu_cxr_mask = 0x0000003f,
  1018 + .mmu_sfsr_mask = 0xffffffff,
  1019 + .mmu_trcr_mask = 0xffffffff,
  1020 + },
  1021 + {
  1022 + .name = "LEON2",
  1023 + .iu_version = 0xf2000000,
  1024 + .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
  1025 + .mmu_version = 0xf2000000,
  1026 + .mmu_bm = 0x00004000,
  1027 + .mmu_ctpr_mask = 0x007ffff0,
  1028 + .mmu_cxr_mask = 0x0000003f,
  1029 + .mmu_sfsr_mask = 0xffffffff,
  1030 + .mmu_trcr_mask = 0xffffffff,
  1031 + },
  1032 + {
  1033 + .name = "LEON3",
  1034 + .iu_version = 0xf3000000,
  1035 + .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
  1036 + .mmu_version = 0xf3000000,
  1037 + .mmu_bm = 0x00004000,
  1038 + .mmu_ctpr_mask = 0x007ffff0,
  1039 + .mmu_cxr_mask = 0x0000003f,
  1040 + .mmu_sfsr_mask = 0xffffffff,
  1041 + .mmu_trcr_mask = 0xffffffff,
  1042 + },
  1043 +#endif
  1044 +};
  1045 +
  1046 +static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name)
  1047 +{
  1048 + unsigned int i;
  1049 +
  1050 + for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
  1051 + if (strcasecmp(name, sparc_defs[i].name) == 0) {
  1052 + return &sparc_defs[i];
  1053 + }
  1054 + }
  1055 + return NULL;
  1056 +}
  1057 +
  1058 +void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
  1059 +{
  1060 + unsigned int i;
  1061 +
  1062 + for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
  1063 + (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
  1064 + sparc_defs[i].name,
  1065 + sparc_defs[i].iu_version,
  1066 + sparc_defs[i].fpu_version,
  1067 + sparc_defs[i].mmu_version);
  1068 + }
  1069 +}
  1070 +
  1071 +#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
  1072 +
  1073 +void cpu_dump_state(CPUState *env, FILE *f,
  1074 + int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
  1075 + int flags)
  1076 +{
  1077 + int i, x;
  1078 +
  1079 + cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
  1080 + cpu_fprintf(f, "General Registers:\n");
  1081 + for (i = 0; i < 4; i++)
  1082 + cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
  1083 + cpu_fprintf(f, "\n");
  1084 + for (; i < 8; i++)
  1085 + cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
  1086 + cpu_fprintf(f, "\nCurrent Register Window:\n");
  1087 + for (x = 0; x < 3; x++) {
  1088 + for (i = 0; i < 4; i++)
  1089 + cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
  1090 + (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
  1091 + env->regwptr[i + x * 8]);
  1092 + cpu_fprintf(f, "\n");
  1093 + for (; i < 8; i++)
  1094 + cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
  1095 + (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
  1096 + env->regwptr[i + x * 8]);
  1097 + cpu_fprintf(f, "\n");
  1098 + }
  1099 + cpu_fprintf(f, "\nFloating Point Registers:\n");
  1100 + for (i = 0; i < 32; i++) {
  1101 + if ((i & 3) == 0)
  1102 + cpu_fprintf(f, "%%f%02d:", i);
  1103 + cpu_fprintf(f, " %016lf", env->fpr[i]);
  1104 + if ((i & 3) == 3)
  1105 + cpu_fprintf(f, "\n");
  1106 + }
  1107 +#ifdef TARGET_SPARC64
  1108 + cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
  1109 + env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
  1110 + cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
  1111 + env->cansave, env->canrestore, env->otherwin, env->wstate,
  1112 + env->cleanwin, NWINDOWS - 1 - env->cwp);
  1113 +#else
  1114 + cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
  1115 + GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
  1116 + GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
  1117 + env->psrs?'S':'-', env->psrps?'P':'-',
  1118 + env->psret?'E':'-', env->wim);
  1119 +#endif
  1120 + cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
  1121 +}
  1122 +
608 #ifdef TARGET_SPARC64 1123 #ifdef TARGET_SPARC64
609 #if !defined(CONFIG_USER_ONLY) 1124 #if !defined(CONFIG_USER_ONLY)
610 #include "qemu-common.h" 1125 #include "qemu-common.h"
target-sparc/translate.c
  View file @c48fcb4
@@ -65,22 +65,6 @@ typedef struct DisasContext { @@ -65,22 +65,6 @@ typedef struct DisasContext {
65 struct TranslationBlock *tb; 65 struct TranslationBlock *tb;
66 } DisasContext; 66 } DisasContext;
67 67
68 -typedef struct sparc_def_t sparc_def_t;  
69 -  
70 -struct sparc_def_t {  
71 - const unsigned char *name;  
72 - target_ulong iu_version;  
73 - uint32_t fpu_version;  
74 - uint32_t mmu_version;  
75 - uint32_t mmu_bm;  
76 - uint32_t mmu_ctpr_mask;  
77 - uint32_t mmu_cxr_mask;  
78 - uint32_t mmu_sfsr_mask;  
79 - uint32_t mmu_trcr_mask;  
80 -};  
81 -  
82 -static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);  
83 -  
84 extern FILE *logfile; 68 extern FILE *logfile;
85 extern int loglevel; 69 extern int loglevel;
86 70
@@ -4661,44 +4645,10 @@ int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb) @@ -4661,44 +4645,10 @@ int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4661 return gen_intermediate_code_internal(tb, 1, env); 4645 return gen_intermediate_code_internal(tb, 1, env);
4662 } 4646 }
4663 4647
4664 -void cpu_reset(CPUSPARCState *env)  
4665 -{  
4666 - tlb_flush(env, 1);  
4667 - env->cwp = 0;  
4668 - env->wim = 1;  
4669 - env->regwptr = env->regbase + (env->cwp * 16);  
4670 -#if defined(CONFIG_USER_ONLY)  
4671 - env->user_mode_only = 1;  
4672 -#ifdef TARGET_SPARC64  
4673 - env->cleanwin = NWINDOWS - 2;  
4674 - env->cansave = NWINDOWS - 2;  
4675 - env->pstate = PS_RMO | PS_PEF | PS_IE;  
4676 - env->asi = 0x82; // Primary no-fault  
4677 -#endif  
4678 -#else  
4679 - env->psret = 0;  
4680 - env->psrs = 1;  
4681 - env->psrps = 1;  
4682 -#ifdef TARGET_SPARC64  
4683 - env->pstate = PS_PRIV;  
4684 - env->hpstate = HS_PRIV;  
4685 - env->pc = 0x1fff0000000ULL;  
4686 - env->tsptr = &env->ts[env->tl];  
4687 -#else  
4688 - env->pc = 0;  
4689 - env->mmuregs[0] &= ~(MMU_E | MMU_NF);  
4690 - env->mmuregs[0] |= env->mmu_bm;  
4691 -#endif  
4692 - env->npc = env->pc + 4;  
4693 -#endif  
4694 -}  
4695 -  
4696 -CPUSPARCState *cpu_sparc_init(const char *cpu_model) 4648 +void gen_intermediate_code_init(CPUSPARCState *env)
4697 { 4649 {
4698 - CPUSPARCState *env;  
4699 - const sparc_def_t *def;  
4700 - static int inited;  
4701 unsigned int i; 4650 unsigned int i;
  4651 + static int inited;
4702 static const char * const gregnames[8] = { 4652 static const char * const gregnames[8] = {
4703 NULL, // g0 not used 4653 NULL, // g0 not used
4704 "g1", 4654 "g1",
@@ -4710,27 +4660,6 @@ CPUSPARCState *cpu_sparc_init(const char *cpu_model) @@ -4710,27 +4660,6 @@ CPUSPARCState *cpu_sparc_init(const char *cpu_model)
4710 "g7", 4660 "g7",
4711 }; 4661 };
4712 4662
4713 - def = cpu_sparc_find_by_name(cpu_model);  
4714 - if (!def)  
4715 - return NULL;  
4716 -  
4717 - env = qemu_mallocz(sizeof(CPUSPARCState));  
4718 - if (!env)  
4719 - return NULL;  
4720 - cpu_exec_init(env);  
4721 - env->cpu_model_str = cpu_model;  
4722 - env->version = def->iu_version;  
4723 - env->fsr = def->fpu_version;  
4724 -#if !defined(TARGET_SPARC64)  
4725 - env->mmu_bm = def->mmu_bm;  
4726 - env->mmu_ctpr_mask = def->mmu_ctpr_mask;  
4727 - env->mmu_cxr_mask = def->mmu_cxr_mask;  
4728 - env->mmu_sfsr_mask = def->mmu_sfsr_mask;  
4729 - env->mmu_trcr_mask = def->mmu_trcr_mask;  
4730 - env->mmuregs[0] |= def->mmu_version;  
4731 - cpu_sparc_set_id(env, 0);  
4732 -#endif  
4733 -  
4734 /* init various static tables */ 4663 /* init various static tables */
4735 if (!inited) { 4664 if (!inited) {
4736 inited = 1; 4665 inited = 1;
@@ -4782,445 +4711,4 @@ CPUSPARCState *cpu_sparc_init(const char *cpu_model) @@ -4782,445 +4711,4 @@ CPUSPARCState *cpu_sparc_init(const char *cpu_model)
4782 offsetof(CPUState, gregs[i]), 4711 offsetof(CPUState, gregs[i]),
4783 gregnames[i]); 4712 gregnames[i]);
4784 } 4713 }
4785 -  
4786 - cpu_reset(env);  
4787 -  
4788 - return env;  
4789 -}  
4790 -  
4791 -void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)  
4792 -{  
4793 -#if !defined(TARGET_SPARC64)  
4794 - env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;  
4795 -#endif  
4796 -}  
4797 -  
4798 -static const sparc_def_t sparc_defs[] = {  
4799 -#ifdef TARGET_SPARC64  
4800 - {  
4801 - .name = "Fujitsu Sparc64",  
4802 - .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)  
4803 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4804 - .fpu_version = 0x00000000,  
4805 - .mmu_version = 0,  
4806 - },  
4807 - {  
4808 - .name = "Fujitsu Sparc64 III",  
4809 - .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)  
4810 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4811 - .fpu_version = 0x00000000,  
4812 - .mmu_version = 0,  
4813 - },  
4814 - {  
4815 - .name = "Fujitsu Sparc64 IV",  
4816 - .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)  
4817 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4818 - .fpu_version = 0x00000000,  
4819 - .mmu_version = 0,  
4820 - },  
4821 - {  
4822 - .name = "Fujitsu Sparc64 V",  
4823 - .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)  
4824 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4825 - .fpu_version = 0x00000000,  
4826 - .mmu_version = 0,  
4827 - },  
4828 - {  
4829 - .name = "TI UltraSparc I",  
4830 - .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)  
4831 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4832 - .fpu_version = 0x00000000,  
4833 - .mmu_version = 0,  
4834 - },  
4835 - {  
4836 - .name = "TI UltraSparc II",  
4837 - .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)  
4838 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4839 - .fpu_version = 0x00000000,  
4840 - .mmu_version = 0,  
4841 - },  
4842 - {  
4843 - .name = "TI UltraSparc IIi",  
4844 - .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)  
4845 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4846 - .fpu_version = 0x00000000,  
4847 - .mmu_version = 0,  
4848 - },  
4849 - {  
4850 - .name = "TI UltraSparc IIe",  
4851 - .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)  
4852 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4853 - .fpu_version = 0x00000000,  
4854 - .mmu_version = 0,  
4855 - },  
4856 - {  
4857 - .name = "Sun UltraSparc III",  
4858 - .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)  
4859 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4860 - .fpu_version = 0x00000000,  
4861 - .mmu_version = 0,  
4862 - },  
4863 - {  
4864 - .name = "Sun UltraSparc III Cu",  
4865 - .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)  
4866 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4867 - .fpu_version = 0x00000000,  
4868 - .mmu_version = 0,  
4869 - },  
4870 - {  
4871 - .name = "Sun UltraSparc IIIi",  
4872 - .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)  
4873 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4874 - .fpu_version = 0x00000000,  
4875 - .mmu_version = 0,  
4876 - },  
4877 - {  
4878 - .name = "Sun UltraSparc IV",  
4879 - .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)  
4880 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4881 - .fpu_version = 0x00000000,  
4882 - .mmu_version = 0,  
4883 - },  
4884 - {  
4885 - .name = "Sun UltraSparc IV+",  
4886 - .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)  
4887 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4888 - .fpu_version = 0x00000000,  
4889 - .mmu_version = 0,  
4890 - },  
4891 - {  
4892 - .name = "Sun UltraSparc IIIi+",  
4893 - .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)  
4894 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4895 - .fpu_version = 0x00000000,  
4896 - .mmu_version = 0,  
4897 - },  
4898 - {  
4899 - .name = "NEC UltraSparc I",  
4900 - .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)  
4901 - | (MAXTL << 8) | (NWINDOWS - 1)),  
4902 - .fpu_version = 0x00000000,  
4903 - .mmu_version = 0,  
4904 - },  
4905 -#else  
4906 - {  
4907 - .name = "Fujitsu MB86900",  
4908 - .iu_version = 0x00 << 24, /* Impl 0, ver 0 */  
4909 - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */  
4910 - .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */  
4911 - .mmu_bm = 0x00004000,  
4912 - .mmu_ctpr_mask = 0x007ffff0,  
4913 - .mmu_cxr_mask = 0x0000003f,  
4914 - .mmu_sfsr_mask = 0xffffffff,  
4915 - .mmu_trcr_mask = 0xffffffff,  
4916 - },  
4917 - {  
4918 - .name = "Fujitsu MB86904",  
4919 - .iu_version = 0x04 << 24, /* Impl 0, ver 4 */  
4920 - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */  
4921 - .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */  
4922 - .mmu_bm = 0x00004000,  
4923 - .mmu_ctpr_mask = 0x00ffffc0,  
4924 - .mmu_cxr_mask = 0x000000ff,  
4925 - .mmu_sfsr_mask = 0x00016fff,  
4926 - .mmu_trcr_mask = 0x00ffffff,  
4927 - },  
4928 - {  
4929 - .name = "Fujitsu MB86907",  
4930 - .iu_version = 0x05 << 24, /* Impl 0, ver 5 */  
4931 - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */  
4932 - .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */  
4933 - .mmu_bm = 0x00004000,  
4934 - .mmu_ctpr_mask = 0xffffffc0,  
4935 - .mmu_cxr_mask = 0x000000ff,  
4936 - .mmu_sfsr_mask = 0x00016fff,  
4937 - .mmu_trcr_mask = 0xffffffff,  
4938 - },  
4939 - {  
4940 - .name = "LSI L64811",  
4941 - .iu_version = 0x10 << 24, /* Impl 1, ver 0 */  
4942 - .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */  
4943 - .mmu_version = 0x10 << 24,  
4944 - .mmu_bm = 0x00004000,  
4945 - .mmu_ctpr_mask = 0x007ffff0,  
4946 - .mmu_cxr_mask = 0x0000003f,  
4947 - .mmu_sfsr_mask = 0xffffffff,  
4948 - .mmu_trcr_mask = 0xffffffff,  
4949 - },  
4950 - {  
4951 - .name = "Cypress CY7C601",  
4952 - .iu_version = 0x11 << 24, /* Impl 1, ver 1 */  
4953 - .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */  
4954 - .mmu_version = 0x10 << 24,  
4955 - .mmu_bm = 0x00004000,  
4956 - .mmu_ctpr_mask = 0x007ffff0,  
4957 - .mmu_cxr_mask = 0x0000003f,  
4958 - .mmu_sfsr_mask = 0xffffffff,  
4959 - .mmu_trcr_mask = 0xffffffff,  
4960 - },  
4961 - {  
4962 - .name = "Cypress CY7C611",  
4963 - .iu_version = 0x13 << 24, /* Impl 1, ver 3 */  
4964 - .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */  
4965 - .mmu_version = 0x10 << 24,  
4966 - .mmu_bm = 0x00004000,  
4967 - .mmu_ctpr_mask = 0x007ffff0,  
4968 - .mmu_cxr_mask = 0x0000003f,  
4969 - .mmu_sfsr_mask = 0xffffffff,  
4970 - .mmu_trcr_mask = 0xffffffff,  
4971 - },  
4972 - {  
4973 - .name = "TI SuperSparc II",  
4974 - .iu_version = 0x40000000,  
4975 - .fpu_version = 0 << 17,  
4976 - .mmu_version = 0x04000000,  
4977 - .mmu_bm = 0x00002000,  
4978 - .mmu_ctpr_mask = 0xffffffc0,  
4979 - .mmu_cxr_mask = 0x0000ffff,  
4980 - .mmu_sfsr_mask = 0xffffffff,  
4981 - .mmu_trcr_mask = 0xffffffff,  
4982 - },  
4983 - {  
4984 - .name = "TI MicroSparc I",  
4985 - .iu_version = 0x41000000,  
4986 - .fpu_version = 4 << 17,  
4987 - .mmu_version = 0x41000000,  
4988 - .mmu_bm = 0x00004000,  
4989 - .mmu_ctpr_mask = 0x007ffff0,  
4990 - .mmu_cxr_mask = 0x0000003f,  
4991 - .mmu_sfsr_mask = 0x00016fff,  
4992 - .mmu_trcr_mask = 0x0000003f,  
4993 - },  
4994 - {  
4995 - .name = "TI MicroSparc II",  
4996 - .iu_version = 0x42000000,  
4997 - .fpu_version = 4 << 17,  
4998 - .mmu_version = 0x02000000,  
4999 - .mmu_bm = 0x00004000,  
5000 - .mmu_ctpr_mask = 0x00ffffc0,  
5001 - .mmu_cxr_mask = 0x000000ff,  
5002 - .mmu_sfsr_mask = 0x00016fff,  
5003 - .mmu_trcr_mask = 0x00ffffff,  
5004 - },  
5005 - {  
5006 - .name = "TI MicroSparc IIep",  
5007 - .iu_version = 0x42000000,  
5008 - .fpu_version = 4 << 17,  
5009 - .mmu_version = 0x04000000,  
5010 - .mmu_bm = 0x00004000,  
5011 - .mmu_ctpr_mask = 0x00ffffc0,  
5012 - .mmu_cxr_mask = 0x000000ff,  
5013 - .mmu_sfsr_mask = 0x00016bff,  
5014 - .mmu_trcr_mask = 0x00ffffff,  
5015 - },  
5016 - {  
5017 - .name = "TI SuperSparc 51",  
5018 - .iu_version = 0x43000000,  
5019 - .fpu_version = 0 << 17,  
5020 - .mmu_version = 0x04000000,  
5021 - .mmu_bm = 0x00002000,  
5022 - .mmu_ctpr_mask = 0xffffffc0,  
5023 - .mmu_cxr_mask = 0x0000ffff,  
5024 - .mmu_sfsr_mask = 0xffffffff,  
5025 - .mmu_trcr_mask = 0xffffffff,  
5026 - },  
5027 - {  
5028 - .name = "TI SuperSparc 61",  
5029 - .iu_version = 0x44000000,  
5030 - .fpu_version = 0 << 17,  
5031 - .mmu_version = 0x04000000,  
5032 - .mmu_bm = 0x00002000,  
5033 - .mmu_ctpr_mask = 0xffffffc0,  
5034 - .mmu_cxr_mask = 0x0000ffff,  
5035 - .mmu_sfsr_mask = 0xffffffff,  
5036 - .mmu_trcr_mask = 0xffffffff,  
5037 - },  
5038 - {  
5039 - .name = "Ross RT625",  
5040 - .iu_version = 0x1e000000,  
5041 - .fpu_version = 1 << 17,  
5042 - .mmu_version = 0x1e000000,  
5043 - .mmu_bm = 0x00004000,  
5044 - .mmu_ctpr_mask = 0x007ffff0,  
5045 - .mmu_cxr_mask = 0x0000003f,  
5046 - .mmu_sfsr_mask = 0xffffffff,  
5047 - .mmu_trcr_mask = 0xffffffff,  
5048 - },  
5049 - {  
5050 - .name = "Ross RT620",  
5051 - .iu_version = 0x1f000000,  
5052 - .fpu_version = 1 << 17,  
5053 - .mmu_version = 0x1f000000,  
5054 - .mmu_bm = 0x00004000,  
5055 - .mmu_ctpr_mask = 0x007ffff0,  
5056 - .mmu_cxr_mask = 0x0000003f,  
5057 - .mmu_sfsr_mask = 0xffffffff,  
5058 - .mmu_trcr_mask = 0xffffffff,  
5059 - },  
5060 - {  
5061 - .name = "BIT B5010",  
5062 - .iu_version = 0x20000000,  
5063 - .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */  
5064 - .mmu_version = 0x20000000,  
5065 - .mmu_bm = 0x00004000,  
5066 - .mmu_ctpr_mask = 0x007ffff0,  
5067 - .mmu_cxr_mask = 0x0000003f,  
5068 - .mmu_sfsr_mask = 0xffffffff,  
5069 - .mmu_trcr_mask = 0xffffffff,  
5070 - },  
5071 - {  
5072 - .name = "Matsushita MN10501",  
5073 - .iu_version = 0x50000000,  
5074 - .fpu_version = 0 << 17,  
5075 - .mmu_version = 0x50000000,  
5076 - .mmu_bm = 0x00004000,  
5077 - .mmu_ctpr_mask = 0x007ffff0,  
5078 - .mmu_cxr_mask = 0x0000003f,  
5079 - .mmu_sfsr_mask = 0xffffffff,  
5080 - .mmu_trcr_mask = 0xffffffff,  
5081 - },  
5082 - {  
5083 - .name = "Weitek W8601",  
5084 - .iu_version = 0x90 << 24, /* Impl 9, ver 0 */  
5085 - .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */  
5086 - .mmu_version = 0x10 << 24,  
5087 - .mmu_bm = 0x00004000,  
5088 - .mmu_ctpr_mask = 0x007ffff0,  
5089 - .mmu_cxr_mask = 0x0000003f,  
5090 - .mmu_sfsr_mask = 0xffffffff,  
5091 - .mmu_trcr_mask = 0xffffffff,  
5092 - },  
5093 - {  
5094 - .name = "LEON2",  
5095 - .iu_version = 0xf2000000,  
5096 - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */  
5097 - .mmu_version = 0xf2000000,  
5098 - .mmu_bm = 0x00004000,  
5099 - .mmu_ctpr_mask = 0x007ffff0,  
5100 - .mmu_cxr_mask = 0x0000003f,  
5101 - .mmu_sfsr_mask = 0xffffffff,  
5102 - .mmu_trcr_mask = 0xffffffff,  
5103 - },  
5104 - {  
5105 - .name = "LEON3",  
5106 - .iu_version = 0xf3000000,  
5107 - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */  
5108 - .mmu_version = 0xf3000000,  
5109 - .mmu_bm = 0x00004000,  
5110 - .mmu_ctpr_mask = 0x007ffff0,  
5111 - .mmu_cxr_mask = 0x0000003f,  
5112 - .mmu_sfsr_mask = 0xffffffff,  
5113 - .mmu_trcr_mask = 0xffffffff,  
5114 - },  
5115 -#endif  
5116 -};  
5117 -  
5118 -static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name)  
5119 -{  
5120 - unsigned int i;  
5121 -  
5122 - for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {  
5123 - if (strcasecmp(name, sparc_defs[i].name) == 0) {  
5124 - return &sparc_defs[i];  
5125 - }  
5126 - }  
5127 - return NULL;  
5128 -}  
5129 -  
5130 -void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))  
5131 -{  
5132 - unsigned int i;  
5133 -  
5134 - for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {  
5135 - (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",  
5136 - sparc_defs[i].name,  
5137 - sparc_defs[i].iu_version,  
5138 - sparc_defs[i].fpu_version,  
5139 - sparc_defs[i].mmu_version);  
5140 - }  
5141 -}  
5142 -  
5143 -#define GET_FLAG(a,b) ((env->psr & a)?b:'-')  
5144 -  
5145 -void cpu_dump_state(CPUState *env, FILE *f,  
5146 - int (*cpu_fprintf)(FILE *f, const char *fmt, ...),  
5147 - int flags)  
5148 -{  
5149 - int i, x;  
5150 -  
5151 - cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);  
5152 - cpu_fprintf(f, "General Registers:\n");  
5153 - for (i = 0; i < 4; i++)  
5154 - cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);  
5155 - cpu_fprintf(f, "\n");  
5156 - for (; i < 8; i++)  
5157 - cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);  
5158 - cpu_fprintf(f, "\nCurrent Register Window:\n");  
5159 - for (x = 0; x < 3; x++) {  
5160 - for (i = 0; i < 4; i++)  
5161 - cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",  
5162 - (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,  
5163 - env->regwptr[i + x * 8]);  
5164 - cpu_fprintf(f, "\n");  
5165 - for (; i < 8; i++)  
5166 - cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",  
5167 - (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,  
5168 - env->regwptr[i + x * 8]);  
5169 - cpu_fprintf(f, "\n");  
5170 - }  
5171 - cpu_fprintf(f, "\nFloating Point Registers:\n");  
5172 - for (i = 0; i < 32; i++) {  
5173 - if ((i & 3) == 0)  
5174 - cpu_fprintf(f, "%%f%02d:", i);  
5175 - cpu_fprintf(f, " %016lf", env->fpr[i]);  
5176 - if ((i & 3) == 3)  
5177 - cpu_fprintf(f, "\n");  
5178 - }  
5179 -#ifdef TARGET_SPARC64  
5180 - cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",  
5181 - env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);  
5182 - cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",  
5183 - env->cansave, env->canrestore, env->otherwin, env->wstate,  
5184 - env->cleanwin, NWINDOWS - 1 - env->cwp);  
5185 -#else  
5186 - cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),  
5187 - GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),  
5188 - GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),  
5189 - env->psrs?'S':'-', env->psrps?'P':'-',  
5190 - env->psret?'E':'-', env->wim);  
5191 -#endif  
5192 - cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));  
5193 -}  
5194 -  
5195 -#if defined(CONFIG_USER_ONLY)  
5196 -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)  
5197 -{  
5198 - return addr;  
5199 -}  
5200 -  
5201 -#else  
5202 -extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,  
5203 - int *access_index, target_ulong address, int rw,  
5204 - int mmu_idx);  
5205 -  
5206 -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)  
5207 -{  
5208 - target_phys_addr_t phys_addr;  
5209 - int prot, access_index;  
5210 -  
5211 - if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,  
5212 - MMU_KERNEL_IDX) != 0)  
5213 - if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,  
5214 - 0, MMU_KERNEL_IDX) != 0)  
5215 - return -1;  
5216 - if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)  
5217 - return -1;  
5218 - return phys_addr;  
5219 -}  
5220 -#endif  
5221 -  
5222 -void helper_flush(target_ulong addr)  
5223 -{  
5224 - addr &= ~7;  
5225 - tb_invalidate_page_range(addr, addr + 8);  
5226 } 4714 }