gwj / at91sam9263 · Commits

Commit c2f01775dddb9e8ab5595400290d6379910ef2be

Authored by balrog
1 parent e0e36fe9

SH: r2d pci support (Takashi YOSHII). 

This patch adds pci support to sh/r2d board.
This is the first user of PCIC support I formerly sent.

PCIC actually is inside of chip with CPU core on SH7751.
But, this code is written as if SH7750 and PCIC are on board.
I care little about physical device boundary, but fitting with qemu's
design.

This patch also adds some BSC (Bus State Controller) registers,
because PCI device driver software have to accesses them.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5932 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 44 additions and 0 deletions
hw/r2d.c
  View file @c2f0177
... ... @@ -28,6 +28,9 @@
28 28 #include "devices.h"
29 29 #include "sysemu.h"
30 30 #include "boards.h"
  31 +#include "pci.h"
  32 +#include "net.h"
  33 +#include "sh7750_regs.h"
31 34  
32 35 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
33 36 #define SDRAM_SIZE 0x04000000
... ... @@ -178,6 +181,17 @@ static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
178 181 return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
179 182 }
180 183  
  184 +static void r2d_pci_set_irq(qemu_irq *p, int n, int l)
  185 +{
  186 + qemu_set_irq(p[n], l);
  187 +}
  188 +
  189 +static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
  190 +{
  191 + const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
  192 + return intx[d->devfn >> 3];
  193 +}
  194 +
181 195 static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
182 196 const char *boot_device, DisplayState * ds,
183 197 const char *kernel_filename, const char *kernel_cmdline,
... ... @@ -187,6 +201,8 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
187 201 struct SH7750State *s;
188 202 ram_addr_t sdram_addr, sm501_vga_ram_addr;
189 203 qemu_irq *irq;
  204 + PCIBus *pci;
  205 + int i;
190 206  
191 207 if (!cpu_model)
192 208 cpu_model = "SH7751R";
... ... @@ -203,6 +219,7 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
203 219 /* Register peripherals */
204 220 s = sh7750_init(env);
205 221 irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
  222 + pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
206 223  
207 224 sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE);
208 225 sm501_init(ds, 0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
... ... @@ -212,9 +229,19 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
212 229 mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
213 230 drives_table[drive_get_index(IF_IDE, 0, 0)].bdrv, NULL);
214 231  
  232 + /* NIC: rtl8139 on-board, and 2 slots. */
  233 + pci_rtl8139_init(pci, &nd_table[0], 2 << 3);
  234 + for (i = 1; i < nb_nics; i++)
  235 + pci_nic_init(pci, &nd_table[i], -1);
  236 +
215 237 /* Todo: register on board registers */
216 238 {
217 239 int kernel_size;
  240 + /* initialization which should be done by firmware */
  241 + uint32_t bcr1 = 1 << 3; /* cs3 SDRAM */
  242 + uint16_t bcr2 = 3 << (3 * 2); /* cs3 32-bit */
  243 + cpu_physical_memory_write(SH7750_BCR1_A7, &bcr1, 4);
  244 + cpu_physical_memory_write(SH7750_BCR2_A7, &bcr2, 2);
218 245  
219 246 kernel_size = load_image(kernel_filename, phys_ram_base);
220 247  
... ...
hw/sh7750.c
  View file @c2f0177
... ... @@ -41,6 +41,8 @@ typedef struct SH7750State {
41 41 /* Peripheral frequency in Hz */
42 42 uint32_t periph_freq;
43 43 /* SDRAM controller */
  44 + uint32_t bcr1;
  45 + uint32_t bcr2;
44 46 uint16_t rfcr;
45 47 /* IO ports */
46 48 uint16_t gpioic;
... ... @@ -208,6 +210,8 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
208 210 SH7750State *s = opaque;
209 211  
210 212 switch (addr) {
  213 + case SH7750_BCR2_A7:
  214 + return s->bcr2;
211 215 case SH7750_FRQCR_A7:
212 216 return 0;
213 217 case SH7750_RFCR_A7:
... ... @@ -231,6 +235,15 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
231 235 SH7750State *s = opaque;
232 236  
233 237 switch (addr) {
  238 + case SH7750_BCR1_A7:
  239 + return s->bcr1;
  240 + case SH7750_BCR4_A7:
  241 + case SH7750_WCR1_A7:
  242 + case SH7750_WCR2_A7:
  243 + case SH7750_WCR3_A7:
  244 + case SH7750_MCR_A7:
  245 + ignore_access("long read", addr);
  246 + return 0;
234 247 case SH7750_MMUCR_A7:
235 248 return s->cpu->mmucr;
236 249 case SH7750_PTEH_A7:
... ... @@ -285,6 +298,8 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
285 298 switch (addr) {
286 299 /* SDRAM controller */
287 300 case SH7750_BCR2_A7:
  301 + s->bcr2 = mem_value;
  302 + return;
288 303 case SH7750_BCR3_A7:
289 304 case SH7750_RTCOR_A7:
290 305 case SH7750_RTCNT_A7:
... ... @@ -331,6 +346,8 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
331 346 switch (addr) {
332 347 /* SDRAM controller */
333 348 case SH7750_BCR1_A7:
  349 + s->bcr1 = mem_value;
  350 + return;
334 351 case SH7750_BCR4_A7:
335 352 case SH7750_WCR1_A7:
336 353 case SH7750_WCR2_A7:
... ...