gwj / at91sam9263 · Commits

Commit c2432a42fe13c3c6774f5443ac8f6f7261fe91d1

Authored by aurel32
1 parent 68af3f24

SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support 

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6548 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 5 changed files with 58 additions and 14 deletions
hw/sh7750.c
  View file @c2432a4
... ... @@ -42,8 +42,12 @@ typedef struct SH7750State {
42 42 uint32_t periph_freq;
43 43 /* SDRAM controller */
44 44 uint32_t bcr1;
45   - uint32_t bcr2;
  45 + uint16_t bcr2;
  46 + uint16_t bcr3;
  47 + uint32_t bcr4;
46 48 uint16_t rfcr;
  49 + /* PCMCIA controller */
  50 + uint16_t pcr;
47 51 /* IO ports */
48 52 uint16_t gpioic;
49 53 uint32_t pctra;
... ... @@ -66,7 +70,10 @@ typedef struct SH7750State {
66 70 struct intc_desc intc;
67 71 } SH7750State;
68 72  
69   -
  73 +static int inline has_bcr3_and_bcr4(SH7750State * s)
  74 +{
  75 + return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
  76 +}
70 77 /**********************************************************************
71 78 I/O ports
72 79 **********************************************************************/
... ... @@ -211,8 +218,14 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
211 218 switch (addr) {
212 219 case SH7750_BCR2_A7:
213 220 return s->bcr2;
  221 + case SH7750_BCR3_A7:
  222 + if(!has_bcr3_and_bcr4(s))
  223 + error_access("word read", addr);
  224 + return s->bcr3;
214 225 case SH7750_FRQCR_A7:
215 226 return 0;
  227 + case SH7750_PCR_A7:
  228 + return s->pcr;
216 229 case SH7750_RFCR_A7:
217 230 fprintf(stderr,
218 231 "Read access to refresh count register, incrementing\n");
... ... @@ -221,6 +234,11 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
221 234 return porta_lines(s);
222 235 case SH7750_PDTRB_A7:
223 236 return portb_lines(s);
  237 + case SH7750_RTCOR_A7:
  238 + case SH7750_RTCNT_A7:
  239 + case SH7750_RTCSR_A7:
  240 + ignore_access("word read", addr);
  241 + return 0;
224 242 default:
225 243 error_access("word read", addr);
226 244 assert(0);
... ... @@ -235,6 +253,9 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
235 253 case SH7750_BCR1_A7:
236 254 return s->bcr1;
237 255 case SH7750_BCR4_A7:
  256 + if(!has_bcr3_and_bcr4(s))
  257 + error_access("long read", addr);
  258 + return s->bcr4;
238 259 case SH7750_WCR1_A7:
239 260 case SH7750_WCR2_A7:
240 261 case SH7750_WCR3_A7:
... ... @@ -271,19 +292,19 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
271 292 }
272 293 }
273 294  
  295 +#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
  296 + && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
274 297 static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
275 298 uint32_t mem_value)
276 299 {
277   - switch (addr) {
278   - /* PRECHARGE ? XXXXX */
279   - case SH7750_PRECHARGE0_A7:
280   - case SH7750_PRECHARGE1_A7:
  300 +
  301 + if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
281 302 ignore_access("byte write", addr);
282 303 return;
283   - default:
284   - error_access("byte write", addr);
285   - assert(0);
286 304 }
  305 +
  306 + error_access("byte write", addr);
  307 + assert(0);
287 308 }
288 309  
289 310 static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
... ... @@ -298,8 +319,15 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
298 319 s->bcr2 = mem_value;
299 320 return;
300 321 case SH7750_BCR3_A7:
301   - case SH7750_RTCOR_A7:
  322 + if(!has_bcr3_and_bcr4(s))
  323 + error_access("word write", addr);
  324 + s->bcr3 = mem_value;
  325 + return;
  326 + case SH7750_PCR_A7:
  327 + s->pcr = mem_value;
  328 + return;
302 329 case SH7750_RTCNT_A7:
  330 + case SH7750_RTCOR_A7:
303 331 case SH7750_RTCSR_A7:
304 332 ignore_access("word write", addr);
305 333 return;
... ... @@ -343,6 +371,10 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
343 371 s->bcr1 = mem_value;
344 372 return;
345 373 case SH7750_BCR4_A7:
  374 + if(!has_bcr3_and_bcr4(s))
  375 + error_access("long write", addr);
  376 + s->bcr4 = mem_value;
  377 + return;
346 378 case SH7750_WCR1_A7:
347 379 case SH7750_WCR2_A7:
348 380 case SH7750_WCR3_A7:
... ...
hw/sh7750_regnames.c
  View file @c2432a4
... ... @@ -80,8 +80,8 @@ static regname_t regnames[] = {
80 80 REGNAME(SH7750_ICR_A7)
81 81 REGNAME(SH7750_BCR3_A7)
82 82 REGNAME(SH7750_BCR4_A7)
83   - REGNAME(SH7750_PRECHARGE0_A7)
84   - REGNAME(SH7750_PRECHARGE1_A7) {(uint32_t) - 1, 0}
  83 + REGNAME(SH7750_SDMR2_A7)
  84 + REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, 0}
85 85 };
86 86  
87 87 const char *regname(uint32_t addr)
... ...
hw/sh7750_regs.h
  View file @c2432a4
... ... @@ -979,6 +979,17 @@
979 979  
980 980 #define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
981 981  
  982 +/* Synchronous DRAM mode registers - SDMR */
  983 +#define SH7750_SDMR2_REGOFS 0x900000 /* base offset */
  984 +#define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */
  985 +#define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS)
  986 +#define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS)
  987 +
  988 +#define SH7750_SDMR3_REGOFS 0x940000 /* offset */
  989 +#define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */
  990 +#define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS)
  991 +#define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS)
  992 +
982 993 /*
983 994 * Direct Memory Access Controller (DMAC)
984 995 */
... ... @@ -1262,7 +1273,5 @@
1262 1273 */
1263 1274 #define SH7750_BCR3_A7 0x1f800050
1264 1275 #define SH7750_BCR4_A7 0x1e0a00f0
1265   -#define SH7750_PRECHARGE0_A7 0x1f900088
1266   -#define SH7750_PRECHARGE1_A7 0x1f940088
1267 1276  
1268 1277 #endif
... ...
target-sh4/cpu.h
  View file @c2432a4
... ... @@ -95,6 +95,7 @@ typedef struct tlb_t {
95 95  
96 96 enum sh_features {
97 97 SH_FEATURE_SH4A = 1,
  98 + SH_FEATURE_BCR3_AND_BCR4 = 2,
98 99 };
99 100  
100 101 typedef struct CPUSH4State {
... ...
target-sh4/translate.c
  View file @c2432a4
... ... @@ -222,12 +222,14 @@ static sh4_def_t sh4_defs[] = {
222 222 .pvr = 0x00050000,
223 223 .prr = 0x00000100,
224 224 .cvr = 0x00110000,
  225 + .features = SH_FEATURE_BCR3_AND_BCR4,
225 226 }, {
226 227 .name = "SH7751R",
227 228 .id = SH_CPU_SH7751R,
228 229 .pvr = 0x04050005,
229 230 .prr = 0x00000113,
230 231 .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
  232 + .features = SH_FEATURE_BCR3_AND_BCR4,
231 233 }, {
232 234 .name = "SH7785",
233 235 .id = SH_CPU_SH7785,
... ...