gwj / at91sam9263 · Commits

Commit c19148bd8f5c2800265372d3554035efde1c5517

Authored by blueswir1
1 parent e7d05e6f

Make MAXTL dynamic, bounds check tl when indexing 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4942 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 4 changed files with 56 additions and 51 deletions
target-sparc/cpu.h
  View file @c19148b
@@ -252,13 +252,15 @@ typedef struct CPUSPARCState { @@ -252,13 +252,15 @@ typedef struct CPUSPARCState {
252 float128 qt0, qt1; 252 float128 qt0, qt1;
253 float_status fp_status; 253 float_status fp_status;
254 #if defined(TARGET_SPARC64) 254 #if defined(TARGET_SPARC64)
255 -#define MAXTL 4 255 +#define MAXTL_MAX 8
  256 +#define MAXTL_MASK (MAXTL_MAX - 1)
256 trap_state *tsptr; 257 trap_state *tsptr;
257 - trap_state ts[MAXTL]; 258 + trap_state ts[MAXTL_MAX];
258 uint32_t xcc; /* Extended integer condition codes */ 259 uint32_t xcc; /* Extended integer condition codes */
259 uint32_t asi; 260 uint32_t asi;
260 uint32_t pstate; 261 uint32_t pstate;
261 uint32_t tl; 262 uint32_t tl;
  263 + uint32_t maxtl;
262 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; 264 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
263 uint64_t agregs[8]; /* alternate general registers */ 265 uint64_t agregs[8]; /* alternate general registers */
264 uint64_t bgregs[8]; /* backup for normal global registers */ 266 uint64_t bgregs[8]; /* backup for normal global registers */
@@ -270,7 +272,7 @@ typedef struct CPUSPARCState { @@ -270,7 +272,7 @@ typedef struct CPUSPARCState {
270 uint64_t gsr; 272 uint64_t gsr;
271 uint32_t gl; // UA2005 273 uint32_t gl; // UA2005
272 /* UA 2005 hyperprivileged registers */ 274 /* UA 2005 hyperprivileged registers */
273 - uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr; 275 + uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
274 void *hstick; // UA 2005 276 void *hstick; // UA 2005
275 #endif 277 #endif
276 uint32_t features; 278 uint32_t features;
target-sparc/helper.c
  View file @c19148b
@@ -48,6 +48,7 @@ struct sparc_def_t { @@ -48,6 +48,7 @@ struct sparc_def_t {
48 uint32_t mmu_trcr_mask; 48 uint32_t mmu_trcr_mask;
49 uint32_t features; 49 uint32_t features;
50 uint32_t nwindows; 50 uint32_t nwindows;
  51 + uint32_t maxtl;
51 }; 52 };
52 53
53 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); 54 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
@@ -738,20 +739,20 @@ void do_interrupt(CPUState *env) @@ -738,20 +739,20 @@ void do_interrupt(CPUState *env)
738 } 739 }
739 #endif 740 #endif
740 #if !defined(CONFIG_USER_ONLY) 741 #if !defined(CONFIG_USER_ONLY)
741 - if (env->tl == MAXTL) {  
742 - cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state",  
743 - env->exception_index); 742 + if (env->tl >= env->maxtl) {
  743 + cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
  744 + " Error state", env->exception_index, env->tl, env->maxtl);
744 return; 745 return;
745 } 746 }
746 #endif 747 #endif
747 - if (env->tl < MAXTL - 1) { 748 + if (env->tl < env->maxtl - 1) {
748 env->tl++; 749 env->tl++;
749 } else { 750 } else {
750 env->pstate |= PS_RED; 751 env->pstate |= PS_RED;
751 - if (env->tl != MAXTL) 752 + if (env->tl < env->maxtl)
752 env->tl++; 753 env->tl++;
753 } 754 }
754 - env->tsptr = &env->ts[env->tl]; 755 + env->tsptr = &env->ts[env->tl & MAXTL_MASK];
755 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) | 756 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
756 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | 757 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
757 GET_CWP64(env); 758 GET_CWP64(env);
@@ -918,7 +919,7 @@ void cpu_reset(CPUSPARCState *env) @@ -918,7 +919,7 @@ void cpu_reset(CPUSPARCState *env)
918 env->pstate = PS_PRIV; 919 env->pstate = PS_PRIV;
919 env->hpstate = HS_PRIV; 920 env->hpstate = HS_PRIV;
920 env->pc = 0x1fff0000020ULL; // XXX should be different for system_reset 921 env->pc = 0x1fff0000020ULL; // XXX should be different for system_reset
921 - env->tsptr = &env->ts[env->tl]; 922 + env->tsptr = &env->ts[env->tl & MAXTL_MASK];
922 #else 923 #else
923 env->pc = 0; 924 env->pc = 0;
924 env->mmuregs[0] &= ~(MMU_E | MMU_NF); 925 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
@@ -950,6 +951,8 @@ static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) @@ -950,6 +951,8 @@ static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
950 cpu_sparc_set_id(env, 0); 951 cpu_sparc_set_id(env, 0);
951 #else 952 #else
952 env->mmu_version = def->mmu_version; 953 env->mmu_version = def->mmu_version;
  954 + env->maxtl = def->maxtl;
  955 + env->version |= def->maxtl << 8;
953 env->version |= def->nwindows - 1; 956 env->version |= def->nwindows - 1;
954 #endif 957 #endif
955 return 0; 958 return 0;
@@ -991,159 +994,159 @@ static const sparc_def_t sparc_defs[] = { @@ -991,159 +994,159 @@ static const sparc_def_t sparc_defs[] = {
991 #ifdef TARGET_SPARC64 994 #ifdef TARGET_SPARC64
992 { 995 {
993 .name = "Fujitsu Sparc64", 996 .name = "Fujitsu Sparc64",
994 - .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)  
995 - | (MAXTL << 8)), 997 + .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
996 .fpu_version = 0x00000000, 998 .fpu_version = 0x00000000,
997 .mmu_version = mmu_us_12, 999 .mmu_version = mmu_us_12,
998 .nwindows = 4, 1000 .nwindows = 4,
  1001 + .maxtl = 4,
999 .features = CPU_DEFAULT_FEATURES, 1002 .features = CPU_DEFAULT_FEATURES,
1000 }, 1003 },
1001 { 1004 {
1002 .name = "Fujitsu Sparc64 III", 1005 .name = "Fujitsu Sparc64 III",
1003 - .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)  
1004 - | (MAXTL << 8)), 1006 + .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
1005 .fpu_version = 0x00000000, 1007 .fpu_version = 0x00000000,
1006 .mmu_version = mmu_us_12, 1008 .mmu_version = mmu_us_12,
1007 .nwindows = 5, 1009 .nwindows = 5,
  1010 + .maxtl = 4,
1008 .features = CPU_DEFAULT_FEATURES, 1011 .features = CPU_DEFAULT_FEATURES,
1009 }, 1012 },
1010 { 1013 {
1011 .name = "Fujitsu Sparc64 IV", 1014 .name = "Fujitsu Sparc64 IV",
1012 - .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)  
1013 - | (MAXTL << 8)), 1015 + .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
1014 .fpu_version = 0x00000000, 1016 .fpu_version = 0x00000000,
1015 .mmu_version = mmu_us_12, 1017 .mmu_version = mmu_us_12,
1016 .nwindows = 8, 1018 .nwindows = 8,
  1019 + .maxtl = 5,
1017 .features = CPU_DEFAULT_FEATURES, 1020 .features = CPU_DEFAULT_FEATURES,
1018 }, 1021 },
1019 { 1022 {
1020 .name = "Fujitsu Sparc64 V", 1023 .name = "Fujitsu Sparc64 V",
1021 - .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)  
1022 - | (MAXTL << 8)), 1024 + .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
1023 .fpu_version = 0x00000000, 1025 .fpu_version = 0x00000000,
1024 .mmu_version = mmu_us_12, 1026 .mmu_version = mmu_us_12,
1025 .nwindows = 8, 1027 .nwindows = 8,
  1028 + .maxtl = 5,
1026 .features = CPU_DEFAULT_FEATURES, 1029 .features = CPU_DEFAULT_FEATURES,
1027 }, 1030 },
1028 { 1031 {
1029 .name = "TI UltraSparc I", 1032 .name = "TI UltraSparc I",
1030 - .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)  
1031 - | (MAXTL << 8)), 1033 + .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
1032 .fpu_version = 0x00000000, 1034 .fpu_version = 0x00000000,
1033 .mmu_version = mmu_us_12, 1035 .mmu_version = mmu_us_12,
1034 .nwindows = 8, 1036 .nwindows = 8,
  1037 + .maxtl = 5,
1035 .features = CPU_DEFAULT_FEATURES, 1038 .features = CPU_DEFAULT_FEATURES,
1036 }, 1039 },
1037 { 1040 {
1038 .name = "TI UltraSparc II", 1041 .name = "TI UltraSparc II",
1039 - .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)  
1040 - | (MAXTL << 8)), 1042 + .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
1041 .fpu_version = 0x00000000, 1043 .fpu_version = 0x00000000,
1042 .mmu_version = mmu_us_12, 1044 .mmu_version = mmu_us_12,
1043 .nwindows = 8, 1045 .nwindows = 8,
  1046 + .maxtl = 5,
1044 .features = CPU_DEFAULT_FEATURES, 1047 .features = CPU_DEFAULT_FEATURES,
1045 }, 1048 },
1046 { 1049 {
1047 .name = "TI UltraSparc IIi", 1050 .name = "TI UltraSparc IIi",
1048 - .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)  
1049 - | (MAXTL << 8)), 1051 + .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
1050 .fpu_version = 0x00000000, 1052 .fpu_version = 0x00000000,
1051 .mmu_version = mmu_us_12, 1053 .mmu_version = mmu_us_12,
1052 .nwindows = 8, 1054 .nwindows = 8,
  1055 + .maxtl = 5,
1053 .features = CPU_DEFAULT_FEATURES, 1056 .features = CPU_DEFAULT_FEATURES,
1054 }, 1057 },
1055 { 1058 {
1056 .name = "TI UltraSparc IIe", 1059 .name = "TI UltraSparc IIe",
1057 - .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)  
1058 - | (MAXTL << 8)), 1060 + .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
1059 .fpu_version = 0x00000000, 1061 .fpu_version = 0x00000000,
1060 .mmu_version = mmu_us_12, 1062 .mmu_version = mmu_us_12,
1061 .nwindows = 8, 1063 .nwindows = 8,
  1064 + .maxtl = 5,
1062 .features = CPU_DEFAULT_FEATURES, 1065 .features = CPU_DEFAULT_FEATURES,
1063 }, 1066 },
1064 { 1067 {
1065 .name = "Sun UltraSparc III", 1068 .name = "Sun UltraSparc III",
1066 - .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)  
1067 - | (MAXTL << 8)), 1069 + .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
1068 .fpu_version = 0x00000000, 1070 .fpu_version = 0x00000000,
1069 .mmu_version = mmu_us_12, 1071 .mmu_version = mmu_us_12,
1070 .nwindows = 8, 1072 .nwindows = 8,
  1073 + .maxtl = 5,
1071 .features = CPU_DEFAULT_FEATURES, 1074 .features = CPU_DEFAULT_FEATURES,
1072 }, 1075 },
1073 { 1076 {
1074 .name = "Sun UltraSparc III Cu", 1077 .name = "Sun UltraSparc III Cu",
1075 - .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)  
1076 - | (MAXTL << 8)), 1078 + .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
1077 .fpu_version = 0x00000000, 1079 .fpu_version = 0x00000000,
1078 .mmu_version = mmu_us_3, 1080 .mmu_version = mmu_us_3,
1079 .nwindows = 8, 1081 .nwindows = 8,
  1082 + .maxtl = 5,
1080 .features = CPU_DEFAULT_FEATURES, 1083 .features = CPU_DEFAULT_FEATURES,
1081 }, 1084 },
1082 { 1085 {
1083 .name = "Sun UltraSparc IIIi", 1086 .name = "Sun UltraSparc IIIi",
1084 - .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)  
1085 - | (MAXTL << 8)), 1087 + .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
1086 .fpu_version = 0x00000000, 1088 .fpu_version = 0x00000000,
1087 .mmu_version = mmu_us_12, 1089 .mmu_version = mmu_us_12,
1088 .nwindows = 8, 1090 .nwindows = 8,
  1091 + .maxtl = 5,
1089 .features = CPU_DEFAULT_FEATURES, 1092 .features = CPU_DEFAULT_FEATURES,
1090 }, 1093 },
1091 { 1094 {
1092 .name = "Sun UltraSparc IV", 1095 .name = "Sun UltraSparc IV",
1093 - .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)  
1094 - | (MAXTL << 8)), 1096 + .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
1095 .fpu_version = 0x00000000, 1097 .fpu_version = 0x00000000,
1096 .mmu_version = mmu_us_4, 1098 .mmu_version = mmu_us_4,
1097 .nwindows = 8, 1099 .nwindows = 8,
  1100 + .maxtl = 5,
1098 .features = CPU_DEFAULT_FEATURES, 1101 .features = CPU_DEFAULT_FEATURES,
1099 }, 1102 },
1100 { 1103 {
1101 .name = "Sun UltraSparc IV+", 1104 .name = "Sun UltraSparc IV+",
1102 - .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)  
1103 - | (MAXTL << 8)), 1105 + .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
1104 .fpu_version = 0x00000000, 1106 .fpu_version = 0x00000000,
1105 .mmu_version = mmu_us_12, 1107 .mmu_version = mmu_us_12,
1106 .nwindows = 8, 1108 .nwindows = 8,
  1109 + .maxtl = 5,
1107 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, 1110 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
1108 }, 1111 },
1109 { 1112 {
1110 .name = "Sun UltraSparc IIIi+", 1113 .name = "Sun UltraSparc IIIi+",
1111 - .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)  
1112 - | (MAXTL << 8)), 1114 + .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
1113 .fpu_version = 0x00000000, 1115 .fpu_version = 0x00000000,
1114 .mmu_version = mmu_us_3, 1116 .mmu_version = mmu_us_3,
1115 .nwindows = 8, 1117 .nwindows = 8,
  1118 + .maxtl = 5,
1116 .features = CPU_DEFAULT_FEATURES, 1119 .features = CPU_DEFAULT_FEATURES,
1117 }, 1120 },
1118 { 1121 {
1119 .name = "Sun UltraSparc T1", 1122 .name = "Sun UltraSparc T1",
1120 // defined in sparc_ifu_fdp.v and ctu.h 1123 // defined in sparc_ifu_fdp.v and ctu.h
1121 - .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)  
1122 - | (MAXTL << 8)), 1124 + .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
1123 .fpu_version = 0x00000000, 1125 .fpu_version = 0x00000000,
1124 .mmu_version = mmu_sun4v, 1126 .mmu_version = mmu_sun4v,
1125 .nwindows = 8, 1127 .nwindows = 8,
  1128 + .maxtl = 6,
1126 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 1129 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
1127 | CPU_FEATURE_GL, 1130 | CPU_FEATURE_GL,
1128 }, 1131 },
1129 { 1132 {
1130 .name = "Sun UltraSparc T2", 1133 .name = "Sun UltraSparc T2",
1131 // defined in tlu_asi_ctl.v and n2_revid_cust.v 1134 // defined in tlu_asi_ctl.v and n2_revid_cust.v
1132 - .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)  
1133 - | (MAXTL << 8)), 1135 + .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
1134 .fpu_version = 0x00000000, 1136 .fpu_version = 0x00000000,
1135 .mmu_version = mmu_sun4v, 1137 .mmu_version = mmu_sun4v,
1136 .nwindows = 8, 1138 .nwindows = 8,
  1139 + .maxtl = 6,
1137 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 1140 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
1138 | CPU_FEATURE_GL, 1141 | CPU_FEATURE_GL,
1139 }, 1142 },
1140 { 1143 {
1141 .name = "NEC UltraSparc I", 1144 .name = "NEC UltraSparc I",
1142 - .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)  
1143 - | (MAXTL << 8)), 1145 + .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
1144 .fpu_version = 0x00000000, 1146 .fpu_version = 0x00000000,
1145 .mmu_version = mmu_us_12, 1147 .mmu_version = mmu_us_12,
1146 .nwindows = 8, 1148 .nwindows = 8,
  1149 + .maxtl = 5,
1147 .features = CPU_DEFAULT_FEATURES, 1150 .features = CPU_DEFAULT_FEATURES,
1148 }, 1151 },
1149 #else 1152 #else
target-sparc/machine.c
  View file @c19148b
@@ -72,7 +72,7 @@ void cpu_save(QEMUFile *f, void *opaque) @@ -72,7 +72,7 @@ void cpu_save(QEMUFile *f, void *opaque)
72 qemu_put_be64s(f, &env->dtlb_tte[i]); 72 qemu_put_be64s(f, &env->dtlb_tte[i]);
73 } 73 }
74 qemu_put_be32s(f, &env->mmu_version); 74 qemu_put_be32s(f, &env->mmu_version);
75 - for (i = 0; i < MAXTL; i++) { 75 + for (i = 0; i < MAXTL_MAX; i++) {
76 qemu_put_be64s(f, &env->ts[i].tpc); 76 qemu_put_be64s(f, &env->ts[i].tpc);
77 qemu_put_be64s(f, &env->ts[i].tnpc); 77 qemu_put_be64s(f, &env->ts[i].tnpc);
78 qemu_put_be64s(f, &env->ts[i].tstate); 78 qemu_put_be64s(f, &env->ts[i].tstate);
@@ -103,7 +103,7 @@ void cpu_save(QEMUFile *f, void *opaque) @@ -103,7 +103,7 @@ void cpu_save(QEMUFile *f, void *opaque)
103 qemu_put_be64s(f, &env->gsr); 103 qemu_put_be64s(f, &env->gsr);
104 qemu_put_be32s(f, &env->gl); 104 qemu_put_be32s(f, &env->gl);
105 qemu_put_be64s(f, &env->hpstate); 105 qemu_put_be64s(f, &env->hpstate);
106 - for (i = 0; i < MAXTL; i++) 106 + for (i = 0; i < MAXTL_MAX; i++)
107 qemu_put_be64s(f, &env->htstate[i]); 107 qemu_put_be64s(f, &env->htstate[i]);
108 qemu_put_be64s(f, &env->hintp); 108 qemu_put_be64s(f, &env->hintp);
109 qemu_put_be64s(f, &env->htba); 109 qemu_put_be64s(f, &env->htba);
@@ -165,7 +165,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) @@ -165,7 +165,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
165 qemu_get_be64s(f, &env->dtlb_tte[i]); 165 qemu_get_be64s(f, &env->dtlb_tte[i]);
166 } 166 }
167 qemu_get_be32s(f, &env->mmu_version); 167 qemu_get_be32s(f, &env->mmu_version);
168 - for (i = 0; i < MAXTL; i++) { 168 + for (i = 0; i < MAXTL_MAX; i++) {
169 qemu_get_be64s(f, &env->ts[i].tpc); 169 qemu_get_be64s(f, &env->ts[i].tpc);
170 qemu_get_be64s(f, &env->ts[i].tnpc); 170 qemu_get_be64s(f, &env->ts[i].tnpc);
171 qemu_get_be64s(f, &env->ts[i].tstate); 171 qemu_get_be64s(f, &env->ts[i].tstate);
@@ -175,7 +175,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) @@ -175,7 +175,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
175 qemu_get_be32s(f, &env->asi); 175 qemu_get_be32s(f, &env->asi);
176 qemu_get_be32s(f, &env->pstate); 176 qemu_get_be32s(f, &env->pstate);
177 qemu_get_be32s(f, &env->tl); 177 qemu_get_be32s(f, &env->tl);
178 - env->tsptr = &env->ts[env->tl]; 178 + env->tsptr = &env->ts[env->tl & MAXTL_MASK];
179 qemu_get_be32s(f, &env->cansave); 179 qemu_get_be32s(f, &env->cansave);
180 qemu_get_be32s(f, &env->canrestore); 180 qemu_get_be32s(f, &env->canrestore);
181 qemu_get_be32s(f, &env->otherwin); 181 qemu_get_be32s(f, &env->otherwin);
@@ -197,7 +197,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) @@ -197,7 +197,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
197 qemu_get_be64s(f, &env->gsr); 197 qemu_get_be64s(f, &env->gsr);
198 qemu_get_be32s(f, &env->gl); 198 qemu_get_be32s(f, &env->gl);
199 qemu_get_be64s(f, &env->hpstate); 199 qemu_get_be64s(f, &env->hpstate);
200 - for (i = 0; i < MAXTL; i++) 200 + for (i = 0; i < MAXTL_MAX; i++)
201 qemu_get_be64s(f, &env->htstate[i]); 201 qemu_get_be64s(f, &env->htstate[i]);
202 qemu_get_be64s(f, &env->hintp); 202 qemu_get_be64s(f, &env->hintp);
203 qemu_get_be64s(f, &env->htba); 203 qemu_get_be64s(f, &env->htba);
target-sparc/op_helper.c
  View file @c19148b
@@ -2742,7 +2742,7 @@ void helper_done(void) @@ -2742,7 +2742,7 @@ void helper_done(void)
2742 change_pstate((env->tsptr->tstate >> 8) & 0xf3f); 2742 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2743 PUT_CWP64(env, env->tsptr->tstate & 0xff); 2743 PUT_CWP64(env, env->tsptr->tstate & 0xff);
2744 env->tl--; 2744 env->tl--;
2745 - env->tsptr = &env->ts[env->tl]; 2745 + env->tsptr = &env->ts[env->tl & MAXTL_MASK];
2746 } 2746 }
2747 2747
2748 void helper_retry(void) 2748 void helper_retry(void)
@@ -2754,7 +2754,7 @@ void helper_retry(void) @@ -2754,7 +2754,7 @@ void helper_retry(void)
2754 change_pstate((env->tsptr->tstate >> 8) & 0xf3f); 2754 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2755 PUT_CWP64(env, env->tsptr->tstate & 0xff); 2755 PUT_CWP64(env, env->tsptr->tstate & 0xff);
2756 env->tl--; 2756 env->tl--;
2757 - env->tsptr = &env->ts[env->tl]; 2757 + env->tsptr = &env->ts[env->tl & MAXTL_MASK];
2758 } 2758 }
2759 #endif 2759 #endif
2760 2760