gwj / at91sam9263 · Commits

Commit c190ea07290c3973f4549d6e2ed9e8b2cddaf497

Authored by blueswir1
1 parent a94fd955

Add EBUS bridge 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6266 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 56 additions and 10 deletions
hw/apb_pci.c
  View file @c190ea0
... ... @@ -223,12 +223,11 @@ static void pci_apb_set_irq(qemu_irq *pic, int irq_num, int level)
223 223  
224 224 PCIBus *pci_apb_init(target_phys_addr_t special_base,
225 225 target_phys_addr_t mem_base,
226   - qemu_irq *pic)
  226 + qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
227 227 {
228 228 APBState *s;
229 229 PCIDevice *d;
230 230 int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
231   - PCIBus *secondary;
232 231  
233 232 s = qemu_mallocz(sizeof(APBState));
234 233 /* Ultrasparc PBM main bus */
... ... @@ -269,9 +268,9 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
269 268 d->config[0x0E] = 0x00; // header_type
270 269  
271 270 /* APB secondary busses */
272   - secondary = pci_bridge_init(s->bus, 8, 0x108e5000, pci_apb_map_irq,
273   - "Advanced PCI Bus secondary bridge 1");
274   - pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq,
275   - "Advanced PCI Bus secondary bridge 2");
  271 + *bus2 = pci_bridge_init(s->bus, 8, 0x108e5000, pci_apb_map_irq,
  272 + "Advanced PCI Bus secondary bridge 1");
  273 + *bus3 = pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq,
  274 + "Advanced PCI Bus secondary bridge 2");
276 275 return s->bus;
277 276 }
... ...
hw/pci.h
  View file @c190ea0
... ... @@ -168,8 +168,9 @@ void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
168 168 PCIBus *pci_prep_init(qemu_irq *pic);
169 169  
170 170 /* apb_pci.c */
171   -PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
172   - qemu_irq *pic);
  171 +PCIBus *pci_apb_init(target_phys_addr_t special_base,
  172 + target_phys_addr_t mem_base,
  173 + qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
173 174  
174 175 /* sh_pci.c */
175 176 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
... ...
hw/sun4u.c
  View file @c190ea0
... ... @@ -344,6 +344,48 @@ static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
344 344  
345 345 static fdctrl_t *floppy_controller;
346 346  
  347 +static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
  348 + uint32_t addr, uint32_t size, int type)
  349 +{
  350 + DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
  351 + switch (region_num) {
  352 + case 0:
  353 + isa_mmio_init(addr, 0x1000000);
  354 + break;
  355 + case 1:
  356 + isa_mmio_init(addr, 0x800000);
  357 + break;
  358 + }
  359 +}
  360 +
  361 +/* EBUS (Eight bit bus) bridge */
  362 +static void
  363 +pci_ebus_init(PCIBus *bus, int devfn)
  364 +{
  365 + PCIDevice *s;
  366 +
  367 + s = pci_register_device(bus, "EBUS", sizeof(*s), devfn, NULL, NULL);
  368 + s->config[0x00] = 0x8e; // vendor_id : Sun
  369 + s->config[0x01] = 0x10;
  370 + s->config[0x02] = 0x00; // device_id
  371 + s->config[0x03] = 0x10;
  372 + s->config[0x04] = 0x06; // command = bus master, pci mem
  373 + s->config[0x05] = 0x00;
  374 + s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
  375 + s->config[0x07] = 0x03; // status = medium devsel
  376 + s->config[0x08] = 0x01; // revision
  377 + s->config[0x09] = 0x00; // programming i/f
  378 + s->config[0x0A] = 0x80; // class_sub = misc bridge
  379 + s->config[0x0B] = 0x06; // class_base = PCI_bridge
  380 + s->config[0x0D] = 0x0a; // latency_timer
  381 + s->config[0x0E] = 0x00; // header_type
  382 +
  383 + pci_register_io_region(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM,
  384 + ebus_mmio_mapfunc);
  385 + pci_register_io_region(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM,
  386 + ebus_mmio_mapfunc);
  387 +}
  388 +
347 389 static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
348 390 const char *boot_devices, DisplayState *ds,
349 391 const char *kernel_filename, const char *kernel_cmdline,
... ... @@ -357,7 +399,7 @@ static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
357 399 unsigned int i;
358 400 ram_addr_t ram_offset, prom_offset, vga_ram_offset;
359 401 long initrd_size, kernel_size;
360   - PCIBus *pci_bus;
  402 + PCIBus *pci_bus, *pci_bus2, *pci_bus3;
361 403 QEMUBH *bh;
362 404 qemu_irq *irq;
363 405 int drive_index;
... ... @@ -462,13 +504,17 @@ static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
462 504 }
463 505 }
464 506 }
465   - pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
  507 + pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL, &pci_bus2,
  508 + &pci_bus3);
466 509 isa_mem_base = VGA_BASE;
467 510 vga_ram_offset = qemu_ram_alloc(vga_ram_size);
468 511 pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset,
469 512 vga_ram_offset, vga_ram_size,
470 513 0, 0);
471 514  
  515 + // XXX Should be pci_bus3
  516 + pci_ebus_init(pci_bus, -1);
  517 +
472 518 i = 0;
473 519 if (hwdef->console_serial_base) {
474 520 serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
... ...