gwj / at91sam9263 · Commits

Commit c070355d398160b6c1ed7ea22753903e96a298d6

Authored by malc
1 parent b01d9fea

Relax memory operations constraints 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4950 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 5 additions and 17 deletions
tcg/ppc64/tcg-target.c
  View file @c070355
@@ -217,24 +217,12 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str) @@ -217,24 +217,12 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
217 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3); 217 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
218 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); 218 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
219 break; 219 break;
220 - case 'K': /* qemu_st[8..32] constraint */ 220 + case 'S': /* qemu_st constraint */
221 ct->ct |= TCG_CT_REG; 221 ct->ct |= TCG_CT_REG;
222 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff); 222 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
223 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3); 223 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
224 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); 224 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
225 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5); 225 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
226 -#if TARGET_LONG_BITS == 64  
227 - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6);  
228 -#endif  
229 - break;  
230 - case 'M': /* qemu_st64 constraint */  
231 - ct->ct |= TCG_CT_REG;  
232 - tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);  
233 - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);  
234 - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);  
235 - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);  
236 - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6);  
237 - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R7);  
238 break; 226 break;
239 default: 227 default:
240 return -1; 228 return -1;
@@ -1424,10 +1412,10 @@ static const TCGTargetOpDef ppc_op_defs[] = { @@ -1424,10 +1412,10 @@ static const TCGTargetOpDef ppc_op_defs[] = {
1424 { INDEX_op_qemu_ld32s, { "r", "L" } }, 1412 { INDEX_op_qemu_ld32s, { "r", "L" } },
1425 { INDEX_op_qemu_ld64, { "r", "L" } }, 1413 { INDEX_op_qemu_ld64, { "r", "L" } },
1426 1414
1427 - { INDEX_op_qemu_st8, { "K", "K" } },  
1428 - { INDEX_op_qemu_st16, { "K", "K" } },  
1429 - { INDEX_op_qemu_st32, { "K", "K" } },  
1430 - { INDEX_op_qemu_st64, { "M", "M", "M" } }, 1415 + { INDEX_op_qemu_st8, { "S", "S" } },
  1416 + { INDEX_op_qemu_st16, { "S", "S" } },
  1417 + { INDEX_op_qemu_st32, { "S", "S" } },
  1418 + { INDEX_op_qemu_st64, { "S", "S", "S" } },
1431 1419
1432 { INDEX_op_ext8s_i32, { "r", "r" } }, 1420 { INDEX_op_ext8s_i32, { "r", "r" } },
1433 { INDEX_op_ext16s_i32, { "r", "r" } }, 1421 { INDEX_op_ext16s_i32, { "r", "r" } },