gwj / at91sam9263 · Commits

Commit c068688b03f4af8994ba0d7bd41a74c8f245453b

Authored by j_mayer
1 parent 5e3b100b

Extend TB flags to 64 bits (Alexander Graf). 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3198 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 7 additions and 6 deletions
cpu-exec.c
  View file @c068688
... ... @@ -77,7 +77,7 @@ void cpu_resume_from_signal(CPUState *env1, void *puc)
77 77  
78 78 static TranslationBlock *tb_find_slow(target_ulong pc,
79 79 target_ulong cs_base,
80   - unsigned int flags)
  80 + uint64_t flags)
81 81 {
82 82 TranslationBlock *tb, **ptb1;
83 83 int code_gen_size;
... ... @@ -155,7 +155,7 @@ static inline TranslationBlock *tb_find_fast(void)
155 155 {
156 156 TranslationBlock *tb;
157 157 target_ulong cs_base, pc;
158   - unsigned int flags;
  158 + uint64_t flags;
159 159  
160 160 /* we record a subset of the CPU state. It will
161 161 always be the same before a given translated block
... ...
exec-all.h
  View file @c068688
... ... @@ -171,7 +171,7 @@ static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
171 171 typedef struct TranslationBlock {
172 172 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
173 173 target_ulong cs_base; /* CS base for this block */
174   - unsigned int flags; /* flags defining in which context the code was generated */
  174 + uint64_t flags; /* flags defining in which context the code was generated */
175 175 uint16_t size; /* size of target code for this block (1 <=
176 176 size <= TARGET_PAGE_SIZE) */
177 177 uint16_t cflags; /* compile flags */
... ...
target-i386/translate.c
  View file @c068688
... ... @@ -95,7 +95,7 @@ typedef struct DisasContext {
95 95 int singlestep_enabled; /* "hardware" single step enabled */
96 96 int jmp_opt; /* use direct block chaining for direct jumps */
97 97 int mem_index; /* select memory access functions */
98   - int flags; /* all execution flags */
  98 + uint64_t flags; /* all execution flags */
99 99 struct TranslationBlock *tb;
100 100 int popl_esp_hack; /* for correct popl with esp base handling */
101 101 int rip_offset; /* only used in x86_64, but left for simplicity */
... ... @@ -6462,7 +6462,8 @@ static inline int gen_intermediate_code_internal(CPUState *env,
6462 6462 DisasContext dc1, *dc = &dc1;
6463 6463 target_ulong pc_ptr;
6464 6464 uint16_t *gen_opc_end;
6465   - int flags, j, lj, cflags;
  6465 + int j, lj, cflags;
  6466 + uint64_t flags;
6466 6467 target_ulong pc_start;
6467 6468 target_ulong cs_base;
6468 6469  
... ...
target-mips/translate.c
  View file @c068688
... ... @@ -6403,7 +6403,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
6403 6403 ctx.tb = tb;
6404 6404 ctx.bstate = BS_NONE;
6405 6405 /* Restore delay slot state from the tb context. */
6406   - ctx.hflags = tb->flags;
  6406 + ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
6407 6407 restore_cpu_state(env, &ctx);
6408 6408 #if defined(CONFIG_USER_ONLY)
6409 6409 ctx.mem_idx = 0;
... ...