gwj / at91sam9263 · Commits

Commit c047da1af40c116fb9b365ccaa3ae6dda80727d1

Authored by aurel32
1 parent 390af821

SH4: Convert shift functions to TCG 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5119 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 9 additions and 24 deletions
target-sh4/op.c
  View file @c047da1
@@ -115,27 +115,6 @@ void OPPROTO op_rotr_Rn(void) @@ -115,27 +115,6 @@ void OPPROTO op_rotr_Rn(void)
115 RETURN(); 115 RETURN();
116 } 116 }
117 117
118 -void OPPROTO op_shal_Rn(void)  
119 -{  
120 - cond_t(env->gregs[PARAM1] & 0x80000000);  
121 - env->gregs[PARAM1] <<= 1;  
122 - RETURN();  
123 -}  
124 -  
125 -void OPPROTO op_shar_Rn(void)  
126 -{  
127 - cond_t(env->gregs[PARAM1] & 1);  
128 - *(int32_t *)&env->gregs[PARAM1] >>= 1;  
129 - RETURN();  
130 -}  
131 -  
132 -void OPPROTO op_shlr_Rn(void)  
133 -{  
134 - cond_t(env->gregs[PARAM1] & 1);  
135 - env->gregs[PARAM1] >>= 1;  
136 - RETURN();  
137 -}  
138 -  
139 void OPPROTO op_fmov_frN_FT0(void) 118 void OPPROTO op_fmov_frN_FT0(void)
140 { 119 {
141 FT0 = env->fregs[PARAM1]; 120 FT0 = env->fregs[PARAM1];
target-sh4/translate.c
  View file @c047da1
@@ -1226,13 +1226,19 @@ void _decode_opc(DisasContext * ctx) @@ -1226,13 +1226,19 @@ void _decode_opc(DisasContext * ctx)
1226 return; 1226 return;
1227 case 0x4000: /* shll Rn */ 1227 case 0x4000: /* shll Rn */
1228 case 0x4020: /* shal Rn */ 1228 case 0x4020: /* shal Rn */
1229 - gen_op_shal_Rn(REG(B11_8)); 1229 + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 0x80000000);
  1230 + gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0);
  1231 + tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
1230 return; 1232 return;
1231 case 0x4021: /* shar Rn */ 1233 case 0x4021: /* shar Rn */
1232 - gen_op_shar_Rn(REG(B11_8)); 1234 + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1);
  1235 + gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0);
  1236 + tcg_gen_sari_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
1233 return; 1237 return;
1234 case 0x4001: /* shlr Rn */ 1238 case 0x4001: /* shlr Rn */
1235 - gen_op_shlr_Rn(REG(B11_8)); 1239 + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1);
  1240 + gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0);
  1241 + tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
1236 return; 1242 return;
1237 case 0x4008: /* shll2 Rn */ 1243 case 0x4008: /* shll2 Rn */
1238 tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2); 1244 tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2);