gwj / at91sam9263 · Commits

Commit c01fccd2de748b8e809573e23a4ed2d5ebd2f715

Authored by aurel32
1 parent 829ef7b0

target-mips: rename helpers from do_ to helper_ 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6773 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 6 changed files with 277 additions and 293 deletions
target-mips/cpu.h
  View file @c01fccd
... ... @@ -41,10 +41,10 @@ struct CPUMIPSTLBContext {
41 41 uint32_t nb_tlb;
42 42 uint32_t tlb_in_use;
43 43 int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
44   - void (*do_tlbwi) (void);
45   - void (*do_tlbwr) (void);
46   - void (*do_tlbp) (void);
47   - void (*do_tlbr) (void);
  44 + void (*helper_tlbwi) (void);
  45 + void (*helper_tlbwr) (void);
  46 + void (*helper_tlbp) (void);
  47 + void (*helper_tlbr) (void);
48 48 union {
49 49 struct {
50 50 r4k_tlb_t tlb[MIPS_TLB_MAX];
... ... @@ -466,10 +466,10 @@ int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
466 466 target_ulong address, int rw, int access_type);
467 467 int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
468 468 target_ulong address, int rw, int access_type);
469   -void r4k_do_tlbwi (void);
470   -void r4k_do_tlbwr (void);
471   -void r4k_do_tlbp (void);
472   -void r4k_do_tlbr (void);
  469 +void r4k_helper_tlbwi (void);
  470 +void r4k_helper_tlbwr (void);
  471 +void r4k_helper_tlbp (void);
  472 +void r4k_helper_tlbr (void);
473 473 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
474 474  
475 475 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
... ...
target-mips/exec.h
  View file @c01fccd
... ... @@ -17,8 +17,6 @@ register struct CPUMIPSState *env asm(AREG0);
17 17 #include "softmmu_exec.h"
18 18 #endif /* !defined(CONFIG_USER_ONLY) */
19 19  
20   -void do_mtc0_status_debug(uint32_t old, uint32_t val);
21   -void do_mtc0_status_irqraise_debug(void);
22 20 void dump_fpu(CPUState *env);
23 21 void fpu_dump_state(CPUState *env, FILE *f,
24 22 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
... ...
target-mips/helper.h
  View file @c01fccd
1 1 #include "def-helper.h"
2 2  
3   -/* FIXME: We should rename the helper functions and remove this hack. */
4   -#undef HELPER
5   -#define HELPER(name) do_##name
6   -
7   -
8 3 DEF_HELPER_2(raise_exception_err, void, i32, int)
9 4 DEF_HELPER_1(raise_exception, void, i32)
10 5 DEF_HELPER_0(interrupt_restart, void)
... ...
target-mips/op_helper.c
  View file @c01fccd
... ... @@ -26,7 +26,7 @@
26 26 /*****************************************************************************/
27 27 /* Exceptions processing helpers */
28 28  
29   -void do_raise_exception_err (uint32_t exception, int error_code)
  29 +void helper_raise_exception_err (uint32_t exception, int error_code)
30 30 {
31 31 #if 1
32 32 if (exception < 0x100)
... ... @@ -37,12 +37,12 @@ void do_raise_exception_err (uint32_t exception, int error_code)
37 37 cpu_loop_exit();
38 38 }
39 39  
40   -void do_raise_exception (uint32_t exception)
  40 +void helper_raise_exception (uint32_t exception)
41 41 {
42   - do_raise_exception_err(exception, 0);
  42 + helper_raise_exception_err(exception, 0);
43 43 }
44 44  
45   -void do_interrupt_restart (void)
  45 +void helper_interrupt_restart (void)
46 46 {
47 47 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
48 48 !(env->CP0_Status & (1 << CP0St_ERL)) &&
... ... @@ -50,7 +50,7 @@ void do_interrupt_restart (void)
50 50 (env->CP0_Status & (1 << CP0St_IE)) &&
51 51 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
52 52 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
53   - do_raise_exception(EXCP_EXT_INTERRUPT);
  53 + helper_raise_exception(EXCP_EXT_INTERRUPT);
54 54 }
55 55 }
56 56  
... ... @@ -67,23 +67,23 @@ static void do_restore_state (void *pc_ptr)
67 67 }
68 68 #endif
69 69  
70   -target_ulong do_clo (target_ulong t0)
  70 +target_ulong helper_clo (target_ulong t0)
71 71 {
72 72 return clo32(t0);
73 73 }
74 74  
75   -target_ulong do_clz (target_ulong t0)
  75 +target_ulong helper_clz (target_ulong t0)
76 76 {
77 77 return clz32(t0);
78 78 }
79 79  
80 80 #if defined(TARGET_MIPS64)
81   -target_ulong do_dclo (target_ulong t0)
  81 +target_ulong helper_dclo (target_ulong t0)
82 82 {
83 83 return clo64(t0);
84 84 }
85 85  
86   -target_ulong do_dclz (target_ulong t0)
  86 +target_ulong helper_dclz (target_ulong t0)
87 87 {
88 88 return clz64(t0);
89 89 }
... ... @@ -114,7 +114,7 @@ static inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO)
114 114 }
115 115  
116 116 #if TARGET_LONG_BITS > HOST_LONG_BITS
117   -void do_madd (target_ulong t0, target_ulong t1)
  117 +void helper_madd (target_ulong t0, target_ulong t1)
118 118 {
119 119 int64_t tmp;
120 120  
... ... @@ -122,7 +122,7 @@ void do_madd (target_ulong t0, target_ulong t1)
122 122 set_HILO((int64_t)get_HILO() + tmp);
123 123 }
124 124  
125   -void do_maddu (target_ulong t0, target_ulong t1)
  125 +void helper_maddu (target_ulong t0, target_ulong t1)
126 126 {
127 127 uint64_t tmp;
128 128  
... ... @@ -130,7 +130,7 @@ void do_maddu (target_ulong t0, target_ulong t1)
130 130 set_HILO(get_HILO() + tmp);
131 131 }
132 132  
133   -void do_msub (target_ulong t0, target_ulong t1)
  133 +void helper_msub (target_ulong t0, target_ulong t1)
134 134 {
135 135 int64_t tmp;
136 136  
... ... @@ -138,7 +138,7 @@ void do_msub (target_ulong t0, target_ulong t1)
138 138 set_HILO((int64_t)get_HILO() - tmp);
139 139 }
140 140  
141   -void do_msubu (target_ulong t0, target_ulong t1)
  141 +void helper_msubu (target_ulong t0, target_ulong t1)
142 142 {
143 143 uint64_t tmp;
144 144  
... ... @@ -148,98 +148,98 @@ void do_msubu (target_ulong t0, target_ulong t1)
148 148 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
149 149  
150 150 /* Multiplication variants of the vr54xx. */
151   -target_ulong do_muls (target_ulong t0, target_ulong t1)
  151 +target_ulong helper_muls (target_ulong t0, target_ulong t1)
152 152 {
153 153 set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
154 154  
155 155 return t0;
156 156 }
157 157  
158   -target_ulong do_mulsu (target_ulong t0, target_ulong t1)
  158 +target_ulong helper_mulsu (target_ulong t0, target_ulong t1)
159 159 {
160 160 set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
161 161  
162 162 return t0;
163 163 }
164 164  
165   -target_ulong do_macc (target_ulong t0, target_ulong t1)
  165 +target_ulong helper_macc (target_ulong t0, target_ulong t1)
166 166 {
167 167 set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
168 168  
169 169 return t0;
170 170 }
171 171  
172   -target_ulong do_macchi (target_ulong t0, target_ulong t1)
  172 +target_ulong helper_macchi (target_ulong t0, target_ulong t1)
173 173 {
174 174 set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
175 175  
176 176 return t0;
177 177 }
178 178  
179   -target_ulong do_maccu (target_ulong t0, target_ulong t1)
  179 +target_ulong helper_maccu (target_ulong t0, target_ulong t1)
180 180 {
181 181 set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
182 182  
183 183 return t0;
184 184 }
185 185  
186   -target_ulong do_macchiu (target_ulong t0, target_ulong t1)
  186 +target_ulong helper_macchiu (target_ulong t0, target_ulong t1)
187 187 {
188 188 set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
189 189  
190 190 return t0;
191 191 }
192 192  
193   -target_ulong do_msac (target_ulong t0, target_ulong t1)
  193 +target_ulong helper_msac (target_ulong t0, target_ulong t1)
194 194 {
195 195 set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
196 196  
197 197 return t0;
198 198 }
199 199  
200   -target_ulong do_msachi (target_ulong t0, target_ulong t1)
  200 +target_ulong helper_msachi (target_ulong t0, target_ulong t1)
201 201 {
202 202 set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
203 203  
204 204 return t0;
205 205 }
206 206  
207   -target_ulong do_msacu (target_ulong t0, target_ulong t1)
  207 +target_ulong helper_msacu (target_ulong t0, target_ulong t1)
208 208 {
209 209 set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
210 210  
211 211 return t0;
212 212 }
213 213  
214   -target_ulong do_msachiu (target_ulong t0, target_ulong t1)
  214 +target_ulong helper_msachiu (target_ulong t0, target_ulong t1)
215 215 {
216 216 set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
217 217  
218 218 return t0;
219 219 }
220 220  
221   -target_ulong do_mulhi (target_ulong t0, target_ulong t1)
  221 +target_ulong helper_mulhi (target_ulong t0, target_ulong t1)
222 222 {
223 223 set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
224 224  
225 225 return t0;
226 226 }
227 227  
228   -target_ulong do_mulhiu (target_ulong t0, target_ulong t1)
  228 +target_ulong helper_mulhiu (target_ulong t0, target_ulong t1)
229 229 {
230 230 set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
231 231  
232 232 return t0;
233 233 }
234 234  
235   -target_ulong do_mulshi (target_ulong t0, target_ulong t1)
  235 +target_ulong helper_mulshi (target_ulong t0, target_ulong t1)
236 236 {
237 237 set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
238 238  
239 239 return t0;
240 240 }
241 241  
242   -target_ulong do_mulshiu (target_ulong t0, target_ulong t1)
  242 +target_ulong helper_mulshiu (target_ulong t0, target_ulong t1)
243 243 {
244 244 set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
245 245  
... ... @@ -247,12 +247,12 @@ target_ulong do_mulshiu (target_ulong t0, target_ulong t1)
247 247 }
248 248  
249 249 #ifdef TARGET_MIPS64
250   -void do_dmult (target_ulong t0, target_ulong t1)
  250 +void helper_dmult (target_ulong t0, target_ulong t1)
251 251 {
252 252 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
253 253 }
254 254  
255   -void do_dmultu (target_ulong t0, target_ulong t1)
  255 +void helper_dmultu (target_ulong t0, target_ulong t1)
256 256 {
257 257 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
258 258 }
... ... @@ -266,7 +266,7 @@ void do_dmultu (target_ulong t0, target_ulong t1)
266 266 #define GET_OFFSET(addr, offset) (addr - (offset))
267 267 #endif
268 268  
269   -target_ulong do_lwl(target_ulong t0, target_ulong t1, int mem_idx)
  269 +target_ulong helper_lwl(target_ulong t0, target_ulong t1, int mem_idx)
270 270 {
271 271 target_ulong tmp;
272 272  
... ... @@ -303,7 +303,7 @@ target_ulong do_lwl(target_ulong t0, target_ulong t1, int mem_idx)
303 303 return (int32_t)t1;
304 304 }
305 305  
306   -target_ulong do_lwr(target_ulong t0, target_ulong t1, int mem_idx)
  306 +target_ulong helper_lwr(target_ulong t0, target_ulong t1, int mem_idx)
307 307 {
308 308 target_ulong tmp;
309 309  
... ... @@ -340,7 +340,7 @@ target_ulong do_lwr(target_ulong t0, target_ulong t1, int mem_idx)
340 340 return (int32_t)t1;
341 341 }
342 342  
343   -void do_swl(target_ulong t0, target_ulong t1, int mem_idx)
  343 +void helper_swl(target_ulong t0, target_ulong t1, int mem_idx)
344 344 {
345 345 #ifdef CONFIG_USER_ONLY
346 346 #define stfun stb_raw
... ... @@ -367,7 +367,7 @@ void do_swl(target_ulong t0, target_ulong t1, int mem_idx)
367 367 stfun(GET_OFFSET(t0, 3), (uint8_t)t1);
368 368 }
369 369  
370   -void do_swr(target_ulong t0, target_ulong t1, int mem_idx)
  370 +void helper_swr(target_ulong t0, target_ulong t1, int mem_idx)
371 371 {
372 372 #ifdef CONFIG_USER_ONLY
373 373 #define stfun stb_raw
... ... @@ -404,7 +404,7 @@ void do_swr(target_ulong t0, target_ulong t1, int mem_idx)
404 404 #define GET_LMASK64(v) (((v) & 7) ^ 7)
405 405 #endif
406 406  
407   -target_ulong do_ldl(target_ulong t0, target_ulong t1, int mem_idx)
  407 +target_ulong helper_ldl(target_ulong t0, target_ulong t1, int mem_idx)
408 408 {
409 409 uint64_t tmp;
410 410  
... ... @@ -462,7 +462,7 @@ target_ulong do_ldl(target_ulong t0, target_ulong t1, int mem_idx)
462 462 return t1;
463 463 }
464 464  
465   -target_ulong do_ldr(target_ulong t0, target_ulong t1, int mem_idx)
  465 +target_ulong helper_ldr(target_ulong t0, target_ulong t1, int mem_idx)
466 466 {
467 467 uint64_t tmp;
468 468  
... ... @@ -520,7 +520,7 @@ target_ulong do_ldr(target_ulong t0, target_ulong t1, int mem_idx)
520 520 return t1;
521 521 }
522 522  
523   -void do_sdl(target_ulong t0, target_ulong t1, int mem_idx)
  523 +void helper_sdl(target_ulong t0, target_ulong t1, int mem_idx)
524 524 {
525 525 #ifdef CONFIG_USER_ONLY
526 526 #define stfun stb_raw
... ... @@ -559,7 +559,7 @@ void do_sdl(target_ulong t0, target_ulong t1, int mem_idx)
559 559 stfun(GET_OFFSET(t0, 7), (uint8_t)t1);
560 560 }
561 561  
562   -void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
  562 +void helper_sdr(target_ulong t0, target_ulong t1, int mem_idx)
563 563 {
564 564 #ifdef CONFIG_USER_ONLY
565 565 #define stfun stb_raw
... ... @@ -601,32 +601,32 @@ void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
601 601  
602 602 #ifndef CONFIG_USER_ONLY
603 603 /* CP0 helpers */
604   -target_ulong do_mfc0_mvpcontrol (void)
  604 +target_ulong helper_mfc0_mvpcontrol (void)
605 605 {
606 606 return env->mvp->CP0_MVPControl;
607 607 }
608 608  
609   -target_ulong do_mfc0_mvpconf0 (void)
  609 +target_ulong helper_mfc0_mvpconf0 (void)
610 610 {
611 611 return env->mvp->CP0_MVPConf0;
612 612 }
613 613  
614   -target_ulong do_mfc0_mvpconf1 (void)
  614 +target_ulong helper_mfc0_mvpconf1 (void)
615 615 {
616 616 return env->mvp->CP0_MVPConf1;
617 617 }
618 618  
619   -target_ulong do_mfc0_random (void)
  619 +target_ulong helper_mfc0_random (void)
620 620 {
621 621 return (int32_t)cpu_mips_get_random(env);
622 622 }
623 623  
624   -target_ulong do_mfc0_tcstatus (void)
  624 +target_ulong helper_mfc0_tcstatus (void)
625 625 {
626 626 return env->active_tc.CP0_TCStatus;
627 627 }
628 628  
629   -target_ulong do_mftc0_tcstatus(void)
  629 +target_ulong helper_mftc0_tcstatus(void)
630 630 {
631 631 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
632 632  
... ... @@ -636,12 +636,12 @@ target_ulong do_mftc0_tcstatus(void)
636 636 return env->tcs[other_tc].CP0_TCStatus;
637 637 }
638 638  
639   -target_ulong do_mfc0_tcbind (void)
  639 +target_ulong helper_mfc0_tcbind (void)
640 640 {
641 641 return env->active_tc.CP0_TCBind;
642 642 }
643 643  
644   -target_ulong do_mftc0_tcbind(void)
  644 +target_ulong helper_mftc0_tcbind(void)
645 645 {
646 646 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
647 647  
... ... @@ -651,12 +651,12 @@ target_ulong do_mftc0_tcbind(void)
651 651 return env->tcs[other_tc].CP0_TCBind;
652 652 }
653 653  
654   -target_ulong do_mfc0_tcrestart (void)
  654 +target_ulong helper_mfc0_tcrestart (void)
655 655 {
656 656 return env->active_tc.PC;
657 657 }
658 658  
659   -target_ulong do_mftc0_tcrestart(void)
  659 +target_ulong helper_mftc0_tcrestart(void)
660 660 {
661 661 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
662 662  
... ... @@ -666,12 +666,12 @@ target_ulong do_mftc0_tcrestart(void)
666 666 return env->tcs[other_tc].PC;
667 667 }
668 668  
669   -target_ulong do_mfc0_tchalt (void)
  669 +target_ulong helper_mfc0_tchalt (void)
670 670 {
671 671 return env->active_tc.CP0_TCHalt;
672 672 }
673 673  
674   -target_ulong do_mftc0_tchalt(void)
  674 +target_ulong helper_mftc0_tchalt(void)
675 675 {
676 676 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
677 677  
... ... @@ -681,12 +681,12 @@ target_ulong do_mftc0_tchalt(void)
681 681 return env->tcs[other_tc].CP0_TCHalt;
682 682 }
683 683  
684   -target_ulong do_mfc0_tccontext (void)
  684 +target_ulong helper_mfc0_tccontext (void)
685 685 {
686 686 return env->active_tc.CP0_TCContext;
687 687 }
688 688  
689   -target_ulong do_mftc0_tccontext(void)
  689 +target_ulong helper_mftc0_tccontext(void)
690 690 {
691 691 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
692 692  
... ... @@ -696,12 +696,12 @@ target_ulong do_mftc0_tccontext(void)
696 696 return env->tcs[other_tc].CP0_TCContext;
697 697 }
698 698  
699   -target_ulong do_mfc0_tcschedule (void)
  699 +target_ulong helper_mfc0_tcschedule (void)
700 700 {
701 701 return env->active_tc.CP0_TCSchedule;
702 702 }
703 703  
704   -target_ulong do_mftc0_tcschedule(void)
  704 +target_ulong helper_mftc0_tcschedule(void)
705 705 {
706 706 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
707 707  
... ... @@ -711,12 +711,12 @@ target_ulong do_mftc0_tcschedule(void)
711 711 return env->tcs[other_tc].CP0_TCSchedule;
712 712 }
713 713  
714   -target_ulong do_mfc0_tcschefback (void)
  714 +target_ulong helper_mfc0_tcschefback (void)
715 715 {
716 716 return env->active_tc.CP0_TCScheFBack;
717 717 }
718 718  
719   -target_ulong do_mftc0_tcschefback(void)
  719 +target_ulong helper_mftc0_tcschefback(void)
720 720 {
721 721 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
722 722  
... ... @@ -726,12 +726,12 @@ target_ulong do_mftc0_tcschefback(void)
726 726 return env->tcs[other_tc].CP0_TCScheFBack;
727 727 }
728 728  
729   -target_ulong do_mfc0_count (void)
  729 +target_ulong helper_mfc0_count (void)
730 730 {
731 731 return (int32_t)cpu_mips_get_count(env);
732 732 }
733 733  
734   -target_ulong do_mftc0_entryhi(void)
  734 +target_ulong helper_mftc0_entryhi(void)
735 735 {
736 736 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
737 737 int32_t tcstatus;
... ... @@ -744,7 +744,7 @@ target_ulong do_mftc0_entryhi(void)
744 744 return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
745 745 }
746 746  
747   -target_ulong do_mftc0_status(void)
  747 +target_ulong helper_mftc0_status(void)
748 748 {
749 749 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
750 750 target_ulong t0;
... ... @@ -763,22 +763,22 @@ target_ulong do_mftc0_status(void)
763 763 return t0;
764 764 }
765 765  
766   -target_ulong do_mfc0_lladdr (void)
  766 +target_ulong helper_mfc0_lladdr (void)
767 767 {
768 768 return (int32_t)env->CP0_LLAddr >> 4;
769 769 }
770 770  
771   -target_ulong do_mfc0_watchlo (uint32_t sel)
  771 +target_ulong helper_mfc0_watchlo (uint32_t sel)
772 772 {
773 773 return (int32_t)env->CP0_WatchLo[sel];
774 774 }
775 775  
776   -target_ulong do_mfc0_watchhi (uint32_t sel)
  776 +target_ulong helper_mfc0_watchhi (uint32_t sel)
777 777 {
778 778 return env->CP0_WatchHi[sel];
779 779 }
780 780  
781   -target_ulong do_mfc0_debug (void)
  781 +target_ulong helper_mfc0_debug (void)
782 782 {
783 783 target_ulong t0 = env->CP0_Debug;
784 784 if (env->hflags & MIPS_HFLAG_DM)
... ... @@ -787,7 +787,7 @@ target_ulong do_mfc0_debug (void)
787 787 return t0;
788 788 }
789 789  
790   -target_ulong do_mftc0_debug(void)
  790 +target_ulong helper_mftc0_debug(void)
791 791 {
792 792 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
793 793 int32_t tcstatus;
... ... @@ -803,43 +803,43 @@ target_ulong do_mftc0_debug(void)
803 803 }
804 804  
805 805 #if defined(TARGET_MIPS64)
806   -target_ulong do_dmfc0_tcrestart (void)
  806 +target_ulong helper_dmfc0_tcrestart (void)
807 807 {
808 808 return env->active_tc.PC;
809 809 }
810 810  
811   -target_ulong do_dmfc0_tchalt (void)
  811 +target_ulong helper_dmfc0_tchalt (void)
812 812 {
813 813 return env->active_tc.CP0_TCHalt;
814 814 }
815 815  
816   -target_ulong do_dmfc0_tccontext (void)
  816 +target_ulong helper_dmfc0_tccontext (void)
817 817 {
818 818 return env->active_tc.CP0_TCContext;
819 819 }
820 820  
821   -target_ulong do_dmfc0_tcschedule (void)
  821 +target_ulong helper_dmfc0_tcschedule (void)
822 822 {
823 823 return env->active_tc.CP0_TCSchedule;
824 824 }
825 825  
826   -target_ulong do_dmfc0_tcschefback (void)
  826 +target_ulong helper_dmfc0_tcschefback (void)
827 827 {
828 828 return env->active_tc.CP0_TCScheFBack;
829 829 }
830 830  
831   -target_ulong do_dmfc0_lladdr (void)
  831 +target_ulong helper_dmfc0_lladdr (void)
832 832 {
833 833 return env->CP0_LLAddr >> 4;
834 834 }
835 835  
836   -target_ulong do_dmfc0_watchlo (uint32_t sel)
  836 +target_ulong helper_dmfc0_watchlo (uint32_t sel)
837 837 {
838 838 return env->CP0_WatchLo[sel];
839 839 }
840 840 #endif /* TARGET_MIPS64 */
841 841  
842   -void do_mtc0_index (target_ulong t0)
  842 +void helper_mtc0_index (target_ulong t0)
843 843 {
844 844 int num = 1;
845 845 unsigned int tmp = env->tlb->nb_tlb;
... ... @@ -851,7 +851,7 @@ void do_mtc0_index (target_ulong t0)
851 851 env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1));
852 852 }
853 853  
854   -void do_mtc0_mvpcontrol (target_ulong t0)
  854 +void helper_mtc0_mvpcontrol (target_ulong t0)
855 855 {
856 856 uint32_t mask = 0;
857 857 uint32_t newval;
... ... @@ -868,7 +868,7 @@ void do_mtc0_mvpcontrol (target_ulong t0)
868 868 env->mvp->CP0_MVPControl = newval;
869 869 }
870 870  
871   -void do_mtc0_vpecontrol (target_ulong t0)
  871 +void helper_mtc0_vpecontrol (target_ulong t0)
872 872 {
873 873 uint32_t mask;
874 874 uint32_t newval;
... ... @@ -885,7 +885,7 @@ void do_mtc0_vpecontrol (target_ulong t0)
885 885 env->CP0_VPEControl = newval;
886 886 }
887 887  
888   -void do_mtc0_vpeconf0 (target_ulong t0)
  888 +void helper_mtc0_vpeconf0 (target_ulong t0)
889 889 {
890 890 uint32_t mask = 0;
891 891 uint32_t newval;
... ... @@ -902,7 +902,7 @@ void do_mtc0_vpeconf0 (target_ulong t0)
902 902 env->CP0_VPEConf0 = newval;
903 903 }
904 904  
905   -void do_mtc0_vpeconf1 (target_ulong t0)
  905 +void helper_mtc0_vpeconf1 (target_ulong t0)
906 906 {
907 907 uint32_t mask = 0;
908 908 uint32_t newval;
... ... @@ -920,25 +920,25 @@ void do_mtc0_vpeconf1 (target_ulong t0)
920 920 env->CP0_VPEConf1 = newval;
921 921 }
922 922  
923   -void do_mtc0_yqmask (target_ulong t0)
  923 +void helper_mtc0_yqmask (target_ulong t0)
924 924 {
925 925 /* Yield qualifier inputs not implemented. */
926 926 env->CP0_YQMask = 0x00000000;
927 927 }
928 928  
929   -void do_mtc0_vpeopt (target_ulong t0)
  929 +void helper_mtc0_vpeopt (target_ulong t0)
930 930 {
931 931 env->CP0_VPEOpt = t0 & 0x0000ffff;
932 932 }
933 933  
934   -void do_mtc0_entrylo0 (target_ulong t0)
  934 +void helper_mtc0_entrylo0 (target_ulong t0)
935 935 {
936 936 /* Large physaddr (PABITS) not implemented */
937 937 /* 1k pages not implemented */
938 938 env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;
939 939 }
940 940  
941   -void do_mtc0_tcstatus (target_ulong t0)
  941 +void helper_mtc0_tcstatus (target_ulong t0)
942 942 {
943 943 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
944 944 uint32_t newval;
... ... @@ -950,7 +950,7 @@ void do_mtc0_tcstatus (target_ulong t0)
950 950 env->active_tc.CP0_TCStatus = newval;
951 951 }
952 952  
953   -void do_mttc0_tcstatus (target_ulong t0)
  953 +void helper_mttc0_tcstatus (target_ulong t0)
954 954 {
955 955 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
956 956  
... ... @@ -962,7 +962,7 @@ void do_mttc0_tcstatus (target_ulong t0)
962 962 env->tcs[other_tc].CP0_TCStatus = t0;
963 963 }
964 964  
965   -void do_mtc0_tcbind (target_ulong t0)
  965 +void helper_mtc0_tcbind (target_ulong t0)
966 966 {
967 967 uint32_t mask = (1 << CP0TCBd_TBE);
968 968 uint32_t newval;
... ... @@ -973,7 +973,7 @@ void do_mtc0_tcbind (target_ulong t0)
973 973 env->active_tc.CP0_TCBind = newval;
974 974 }
975 975  
976   -void do_mttc0_tcbind (target_ulong t0)
  976 +void helper_mttc0_tcbind (target_ulong t0)
977 977 {
978 978 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
979 979 uint32_t mask = (1 << CP0TCBd_TBE);
... ... @@ -990,7 +990,7 @@ void do_mttc0_tcbind (target_ulong t0)
990 990 }
991 991 }
992 992  
993   -void do_mtc0_tcrestart (target_ulong t0)
  993 +void helper_mtc0_tcrestart (target_ulong t0)
994 994 {
995 995 env->active_tc.PC = t0;
996 996 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
... ... @@ -998,7 +998,7 @@ void do_mtc0_tcrestart (target_ulong t0)
998 998 /* MIPS16 not implemented. */
999 999 }
1000 1000  
1001   -void do_mttc0_tcrestart (target_ulong t0)
  1001 +void helper_mttc0_tcrestart (target_ulong t0)
1002 1002 {
1003 1003 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1004 1004  
... ... @@ -1015,14 +1015,14 @@ void do_mttc0_tcrestart (target_ulong t0)
1015 1015 }
1016 1016 }
1017 1017  
1018   -void do_mtc0_tchalt (target_ulong t0)
  1018 +void helper_mtc0_tchalt (target_ulong t0)
1019 1019 {
1020 1020 env->active_tc.CP0_TCHalt = t0 & 0x1;
1021 1021  
1022 1022 // TODO: Halt TC / Restart (if allocated+active) TC.
1023 1023 }
1024 1024  
1025   -void do_mttc0_tchalt (target_ulong t0)
  1025 +void helper_mttc0_tchalt (target_ulong t0)
1026 1026 {
1027 1027 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1028 1028  
... ... @@ -1034,12 +1034,12 @@ void do_mttc0_tchalt (target_ulong t0)
1034 1034 env->tcs[other_tc].CP0_TCHalt = t0;
1035 1035 }
1036 1036  
1037   -void do_mtc0_tccontext (target_ulong t0)
  1037 +void helper_mtc0_tccontext (target_ulong t0)
1038 1038 {
1039 1039 env->active_tc.CP0_TCContext = t0;
1040 1040 }
1041 1041  
1042   -void do_mttc0_tccontext (target_ulong t0)
  1042 +void helper_mttc0_tccontext (target_ulong t0)
1043 1043 {
1044 1044 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1045 1045  
... ... @@ -1049,12 +1049,12 @@ void do_mttc0_tccontext (target_ulong t0)
1049 1049 env->tcs[other_tc].CP0_TCContext = t0;
1050 1050 }
1051 1051  
1052   -void do_mtc0_tcschedule (target_ulong t0)
  1052 +void helper_mtc0_tcschedule (target_ulong t0)
1053 1053 {
1054 1054 env->active_tc.CP0_TCSchedule = t0;
1055 1055 }
1056 1056  
1057   -void do_mttc0_tcschedule (target_ulong t0)
  1057 +void helper_mttc0_tcschedule (target_ulong t0)
1058 1058 {
1059 1059 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1060 1060  
... ... @@ -1064,12 +1064,12 @@ void do_mttc0_tcschedule (target_ulong t0)
1064 1064 env->tcs[other_tc].CP0_TCSchedule = t0;
1065 1065 }
1066 1066  
1067   -void do_mtc0_tcschefback (target_ulong t0)
  1067 +void helper_mtc0_tcschefback (target_ulong t0)
1068 1068 {
1069 1069 env->active_tc.CP0_TCScheFBack = t0;
1070 1070 }
1071 1071  
1072   -void do_mttc0_tcschefback (target_ulong t0)
  1072 +void helper_mttc0_tcschefback (target_ulong t0)
1073 1073 {
1074 1074 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1075 1075  
... ... @@ -1079,25 +1079,25 @@ void do_mttc0_tcschefback (target_ulong t0)
1079 1079 env->tcs[other_tc].CP0_TCScheFBack = t0;
1080 1080 }
1081 1081  
1082   -void do_mtc0_entrylo1 (target_ulong t0)
  1082 +void helper_mtc0_entrylo1 (target_ulong t0)
1083 1083 {
1084 1084 /* Large physaddr (PABITS) not implemented */
1085 1085 /* 1k pages not implemented */
1086 1086 env->CP0_EntryLo1 = t0 & 0x3FFFFFFF;
1087 1087 }
1088 1088  
1089   -void do_mtc0_context (target_ulong t0)
  1089 +void helper_mtc0_context (target_ulong t0)
1090 1090 {
1091 1091 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF);
1092 1092 }
1093 1093  
1094   -void do_mtc0_pagemask (target_ulong t0)
  1094 +void helper_mtc0_pagemask (target_ulong t0)
1095 1095 {
1096 1096 /* 1k pages not implemented */
1097 1097 env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1098 1098 }
1099 1099  
1100   -void do_mtc0_pagegrain (target_ulong t0)
  1100 +void helper_mtc0_pagegrain (target_ulong t0)
1101 1101 {
1102 1102 /* SmartMIPS not implemented */
1103 1103 /* Large physaddr (PABITS) not implemented */
... ... @@ -1105,47 +1105,47 @@ void do_mtc0_pagegrain (target_ulong t0)
1105 1105 env->CP0_PageGrain = 0;
1106 1106 }
1107 1107  
1108   -void do_mtc0_wired (target_ulong t0)
  1108 +void helper_mtc0_wired (target_ulong t0)
1109 1109 {
1110 1110 env->CP0_Wired = t0 % env->tlb->nb_tlb;
1111 1111 }
1112 1112  
1113   -void do_mtc0_srsconf0 (target_ulong t0)
  1113 +void helper_mtc0_srsconf0 (target_ulong t0)
1114 1114 {
1115 1115 env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask;
1116 1116 }
1117 1117  
1118   -void do_mtc0_srsconf1 (target_ulong t0)
  1118 +void helper_mtc0_srsconf1 (target_ulong t0)
1119 1119 {
1120 1120 env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask;
1121 1121 }
1122 1122  
1123   -void do_mtc0_srsconf2 (target_ulong t0)
  1123 +void helper_mtc0_srsconf2 (target_ulong t0)
1124 1124 {
1125 1125 env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask;
1126 1126 }
1127 1127  
1128   -void do_mtc0_srsconf3 (target_ulong t0)
  1128 +void helper_mtc0_srsconf3 (target_ulong t0)
1129 1129 {
1130 1130 env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask;
1131 1131 }
1132 1132  
1133   -void do_mtc0_srsconf4 (target_ulong t0)
  1133 +void helper_mtc0_srsconf4 (target_ulong t0)
1134 1134 {
1135 1135 env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask;
1136 1136 }
1137 1137  
1138   -void do_mtc0_hwrena (target_ulong t0)
  1138 +void helper_mtc0_hwrena (target_ulong t0)
1139 1139 {
1140 1140 env->CP0_HWREna = t0 & 0x0000000F;
1141 1141 }
1142 1142  
1143   -void do_mtc0_count (target_ulong t0)
  1143 +void helper_mtc0_count (target_ulong t0)
1144 1144 {
1145 1145 cpu_mips_store_count(env, t0);
1146 1146 }
1147 1147  
1148   -void do_mtc0_entryhi (target_ulong t0)
  1148 +void helper_mtc0_entryhi (target_ulong t0)
1149 1149 {
1150 1150 target_ulong old, val;
1151 1151  
... ... @@ -1165,7 +1165,7 @@ void do_mtc0_entryhi (target_ulong t0)
1165 1165 cpu_mips_tlb_flush(env, 1);
1166 1166 }
1167 1167  
1168   -void do_mttc0_entryhi(target_ulong t0)
  1168 +void helper_mttc0_entryhi(target_ulong t0)
1169 1169 {
1170 1170 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1171 1171 int32_t tcstatus;
... ... @@ -1180,12 +1180,12 @@ void do_mttc0_entryhi(target_ulong t0)
1180 1180 }
1181 1181 }
1182 1182  
1183   -void do_mtc0_compare (target_ulong t0)
  1183 +void helper_mtc0_compare (target_ulong t0)
1184 1184 {
1185 1185 cpu_mips_store_compare(env, t0);
1186 1186 }
1187 1187  
1188   -void do_mtc0_status (target_ulong t0)
  1188 +void helper_mtc0_status (target_ulong t0)
1189 1189 {
1190 1190 uint32_t val, old;
1191 1191 uint32_t mask = env->CP0_Status_rw_bitmask;
... ... @@ -1194,12 +1194,22 @@ void do_mtc0_status (target_ulong t0)
1194 1194 old = env->CP0_Status;
1195 1195 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1196 1196 compute_hflags(env);
1197   - if (qemu_loglevel_mask(CPU_LOG_EXEC))
1198   - do_mtc0_status_debug(old, val);
  1197 + if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
  1198 + qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
  1199 + old, old & env->CP0_Cause & CP0Ca_IP_mask,
  1200 + val, val & env->CP0_Cause & CP0Ca_IP_mask,
  1201 + env->CP0_Cause);
  1202 + switch (env->hflags & MIPS_HFLAG_KSU) {
  1203 + case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
  1204 + case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
  1205 + case MIPS_HFLAG_KM: qemu_log("\n"); break;
  1206 + default: cpu_abort(env, "Invalid MMU mode!\n"); break;
  1207 + }
  1208 + }
1199 1209 cpu_mips_update_irq(env);
1200 1210 }
1201 1211  
1202   -void do_mttc0_status(target_ulong t0)
  1212 +void helper_mttc0_status(target_ulong t0)
1203 1213 {
1204 1214 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1205 1215 int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
... ... @@ -1214,19 +1224,19 @@ void do_mttc0_status(target_ulong t0)
1214 1224 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1215 1225 }
1216 1226  
1217   -void do_mtc0_intctl (target_ulong t0)
  1227 +void helper_mtc0_intctl (target_ulong t0)
1218 1228 {
1219 1229 /* vectored interrupts not implemented, no performance counters. */
1220 1230 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0);
1221 1231 }
1222 1232  
1223   -void do_mtc0_srsctl (target_ulong t0)
  1233 +void helper_mtc0_srsctl (target_ulong t0)
1224 1234 {
1225 1235 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1226 1236 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask);
1227 1237 }
1228 1238  
1229   -void do_mtc0_cause (target_ulong t0)
  1239 +void helper_mtc0_cause (target_ulong t0)
1230 1240 {
1231 1241 uint32_t mask = 0x00C00300;
1232 1242 uint32_t old = env->CP0_Cause;
... ... @@ -1250,49 +1260,49 @@ void do_mtc0_cause (target_ulong t0)
1250 1260 }
1251 1261 }
1252 1262  
1253   -void do_mtc0_ebase (target_ulong t0)
  1263 +void helper_mtc0_ebase (target_ulong t0)
1254 1264 {
1255 1265 /* vectored interrupts not implemented */
1256 1266 /* Multi-CPU not implemented */
1257 1267 env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000);
1258 1268 }
1259 1269  
1260   -void do_mtc0_config0 (target_ulong t0)
  1270 +void helper_mtc0_config0 (target_ulong t0)
1261 1271 {
1262 1272 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007);
1263 1273 }
1264 1274  
1265   -void do_mtc0_config2 (target_ulong t0)
  1275 +void helper_mtc0_config2 (target_ulong t0)
1266 1276 {
1267 1277 /* tertiary/secondary caches not implemented */
1268 1278 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1269 1279 }
1270 1280  
1271   -void do_mtc0_watchlo (target_ulong t0, uint32_t sel)
  1281 +void helper_mtc0_watchlo (target_ulong t0, uint32_t sel)
1272 1282 {
1273 1283 /* Watch exceptions for instructions, data loads, data stores
1274 1284 not implemented. */
1275 1285 env->CP0_WatchLo[sel] = (t0 & ~0x7);
1276 1286 }
1277 1287  
1278   -void do_mtc0_watchhi (target_ulong t0, uint32_t sel)
  1288 +void helper_mtc0_watchhi (target_ulong t0, uint32_t sel)
1279 1289 {
1280 1290 env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8);
1281 1291 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7);
1282 1292 }
1283 1293  
1284   -void do_mtc0_xcontext (target_ulong t0)
  1294 +void helper_mtc0_xcontext (target_ulong t0)
1285 1295 {
1286 1296 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1287 1297 env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask);
1288 1298 }
1289 1299  
1290   -void do_mtc0_framemask (target_ulong t0)
  1300 +void helper_mtc0_framemask (target_ulong t0)
1291 1301 {
1292 1302 env->CP0_Framemask = t0; /* XXX */
1293 1303 }
1294 1304  
1295   -void do_mtc0_debug (target_ulong t0)
  1305 +void helper_mtc0_debug (target_ulong t0)
1296 1306 {
1297 1307 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120);
1298 1308 if (t0 & (1 << CP0DB_DM))
... ... @@ -1301,7 +1311,7 @@ void do_mtc0_debug (target_ulong t0)
1301 1311 env->hflags &= ~MIPS_HFLAG_DM;
1302 1312 }
1303 1313  
1304   -void do_mttc0_debug(target_ulong t0)
  1314 +void helper_mttc0_debug(target_ulong t0)
1305 1315 {
1306 1316 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1307 1317 uint32_t val = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
... ... @@ -1315,52 +1325,33 @@ void do_mttc0_debug(target_ulong t0)
1315 1325 (t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1316 1326 }
1317 1327  
1318   -void do_mtc0_performance0 (target_ulong t0)
  1328 +void helper_mtc0_performance0 (target_ulong t0)
1319 1329 {
1320 1330 env->CP0_Performance0 = t0 & 0x000007ff;
1321 1331 }
1322 1332  
1323   -void do_mtc0_taglo (target_ulong t0)
  1333 +void helper_mtc0_taglo (target_ulong t0)
1324 1334 {
1325 1335 env->CP0_TagLo = t0 & 0xFFFFFCF6;
1326 1336 }
1327 1337  
1328   -void do_mtc0_datalo (target_ulong t0)
  1338 +void helper_mtc0_datalo (target_ulong t0)
1329 1339 {
1330 1340 env->CP0_DataLo = t0; /* XXX */
1331 1341 }
1332 1342  
1333   -void do_mtc0_taghi (target_ulong t0)
  1343 +void helper_mtc0_taghi (target_ulong t0)
1334 1344 {
1335 1345 env->CP0_TagHi = t0; /* XXX */
1336 1346 }
1337 1347  
1338   -void do_mtc0_datahi (target_ulong t0)
  1348 +void helper_mtc0_datahi (target_ulong t0)
1339 1349 {
1340 1350 env->CP0_DataHi = t0; /* XXX */
1341 1351 }
1342 1352  
1343   -void do_mtc0_status_debug(uint32_t old, uint32_t val)
1344   -{
1345   - qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1346   - old, old & env->CP0_Cause & CP0Ca_IP_mask,
1347   - val, val & env->CP0_Cause & CP0Ca_IP_mask,
1348   - env->CP0_Cause);
1349   - switch (env->hflags & MIPS_HFLAG_KSU) {
1350   - case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1351   - case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1352   - case MIPS_HFLAG_KM: qemu_log("\n"); break;
1353   - default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1354   - }
1355   -}
1356   -
1357   -void do_mtc0_status_irqraise_debug(void)
1358   -{
1359   - qemu_log("Raise pending IRQs\n");
1360   -}
1361   -
1362 1353 /* MIPS MT functions */
1363   -target_ulong do_mftgpr(uint32_t sel)
  1354 +target_ulong helper_mftgpr(uint32_t sel)
1364 1355 {
1365 1356 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1366 1357  
... ... @@ -1370,7 +1361,7 @@ target_ulong do_mftgpr(uint32_t sel)
1370 1361 return env->tcs[other_tc].gpr[sel];
1371 1362 }
1372 1363  
1373   -target_ulong do_mftlo(uint32_t sel)
  1364 +target_ulong helper_mftlo(uint32_t sel)
1374 1365 {
1375 1366 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1376 1367  
... ... @@ -1380,7 +1371,7 @@ target_ulong do_mftlo(uint32_t sel)
1380 1371 return env->tcs[other_tc].LO[sel];
1381 1372 }
1382 1373  
1383   -target_ulong do_mfthi(uint32_t sel)
  1374 +target_ulong helper_mfthi(uint32_t sel)
1384 1375 {
1385 1376 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1386 1377  
... ... @@ -1390,7 +1381,7 @@ target_ulong do_mfthi(uint32_t sel)
1390 1381 return env->tcs[other_tc].HI[sel];
1391 1382 }
1392 1383  
1393   -target_ulong do_mftacx(uint32_t sel)
  1384 +target_ulong helper_mftacx(uint32_t sel)
1394 1385 {
1395 1386 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1396 1387  
... ... @@ -1400,7 +1391,7 @@ target_ulong do_mftacx(uint32_t sel)
1400 1391 return env->tcs[other_tc].ACX[sel];
1401 1392 }
1402 1393  
1403   -target_ulong do_mftdsp(void)
  1394 +target_ulong helper_mftdsp(void)
1404 1395 {
1405 1396 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1406 1397  
... ... @@ -1410,7 +1401,7 @@ target_ulong do_mftdsp(void)
1410 1401 return env->tcs[other_tc].DSPControl;
1411 1402 }
1412 1403  
1413   -void do_mttgpr(target_ulong t0, uint32_t sel)
  1404 +void helper_mttgpr(target_ulong t0, uint32_t sel)
1414 1405 {
1415 1406 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1416 1407  
... ... @@ -1420,7 +1411,7 @@ void do_mttgpr(target_ulong t0, uint32_t sel)
1420 1411 env->tcs[other_tc].gpr[sel] = t0;
1421 1412 }
1422 1413  
1423   -void do_mttlo(target_ulong t0, uint32_t sel)
  1414 +void helper_mttlo(target_ulong t0, uint32_t sel)
1424 1415 {
1425 1416 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1426 1417  
... ... @@ -1430,7 +1421,7 @@ void do_mttlo(target_ulong t0, uint32_t sel)
1430 1421 env->tcs[other_tc].LO[sel] = t0;
1431 1422 }
1432 1423  
1433   -void do_mtthi(target_ulong t0, uint32_t sel)
  1424 +void helper_mtthi(target_ulong t0, uint32_t sel)
1434 1425 {
1435 1426 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1436 1427  
... ... @@ -1440,7 +1431,7 @@ void do_mtthi(target_ulong t0, uint32_t sel)
1440 1431 env->tcs[other_tc].HI[sel] = t0;
1441 1432 }
1442 1433  
1443   -void do_mttacx(target_ulong t0, uint32_t sel)
  1434 +void helper_mttacx(target_ulong t0, uint32_t sel)
1444 1435 {
1445 1436 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1446 1437  
... ... @@ -1450,7 +1441,7 @@ void do_mttacx(target_ulong t0, uint32_t sel)
1450 1441 env->tcs[other_tc].ACX[sel] = t0;
1451 1442 }
1452 1443  
1453   -void do_mttdsp(target_ulong t0)
  1444 +void helper_mttdsp(target_ulong t0)
1454 1445 {
1455 1446 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1456 1447  
... ... @@ -1461,7 +1452,7 @@ void do_mttdsp(target_ulong t0)
1461 1452 }
1462 1453  
1463 1454 /* MIPS MT functions */
1464   -target_ulong do_dmt(target_ulong t0)
  1455 +target_ulong helper_dmt(target_ulong t0)
1465 1456 {
1466 1457 // TODO
1467 1458 t0 = 0;
... ... @@ -1470,7 +1461,7 @@ target_ulong do_dmt(target_ulong t0)
1470 1461 return t0;
1471 1462 }
1472 1463  
1473   -target_ulong do_emt(target_ulong t0)
  1464 +target_ulong helper_emt(target_ulong t0)
1474 1465 {
1475 1466 // TODO
1476 1467 t0 = 0;
... ... @@ -1479,7 +1470,7 @@ target_ulong do_emt(target_ulong t0)
1479 1470 return t0;
1480 1471 }
1481 1472  
1482   -target_ulong do_dvpe(target_ulong t0)
  1473 +target_ulong helper_dvpe(target_ulong t0)
1483 1474 {
1484 1475 // TODO
1485 1476 t0 = 0;
... ... @@ -1488,7 +1479,7 @@ target_ulong do_dvpe(target_ulong t0)
1488 1479 return t0;
1489 1480 }
1490 1481  
1491   -target_ulong do_evpe(target_ulong t0)
  1482 +target_ulong helper_evpe(target_ulong t0)
1492 1483 {
1493 1484 // TODO
1494 1485 t0 = 0;
... ... @@ -1498,14 +1489,14 @@ target_ulong do_evpe(target_ulong t0)
1498 1489 }
1499 1490 #endif /* !CONFIG_USER_ONLY */
1500 1491  
1501   -void do_fork(target_ulong t0, target_ulong t1)
  1492 +void helper_fork(target_ulong t0, target_ulong t1)
1502 1493 {
1503 1494 // t0 = rt, t1 = rs
1504 1495 t0 = 0;
1505 1496 // TODO: store to TC register
1506 1497 }
1507 1498  
1508   -target_ulong do_yield(target_ulong t0)
  1499 +target_ulong helper_yield(target_ulong t0)
1509 1500 {
1510 1501 if (t0 < 0) {
1511 1502 /* No scheduling policy implemented. */
... ... @@ -1514,13 +1505,13 @@ target_ulong do_yield(target_ulong t0)
1514 1505 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1515 1506 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1516 1507 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1517   - do_raise_exception(EXCP_THREAD);
  1508 + helper_raise_exception(EXCP_THREAD);
1518 1509 }
1519 1510 }
1520 1511 } else if (t0 == 0) {
1521 1512 if (0 /* TODO: TC underflow */) {
1522 1513 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1523   - do_raise_exception(EXCP_THREAD);
  1514 + helper_raise_exception(EXCP_THREAD);
1524 1515 } else {
1525 1516 // TODO: Deallocate TC
1526 1517 }
... ... @@ -1528,7 +1519,7 @@ target_ulong do_yield(target_ulong t0)
1528 1519 /* Yield qualifier inputs not implemented. */
1529 1520 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1530 1521 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1531   - do_raise_exception(EXCP_THREAD);
  1522 + helper_raise_exception(EXCP_THREAD);
1532 1523 }
1533 1524 return env->CP0_YQMask;
1534 1525 }
... ... @@ -1573,7 +1564,7 @@ static void r4k_fill_tlb (int idx)
1573 1564 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1574 1565 }
1575 1566  
1576   -void r4k_do_tlbwi (void)
  1567 +void r4k_helper_tlbwi (void)
1577 1568 {
1578 1569 int idx;
1579 1570  
... ... @@ -1588,7 +1579,7 @@ void r4k_do_tlbwi (void)
1588 1579 r4k_fill_tlb(idx);
1589 1580 }
1590 1581  
1591   -void r4k_do_tlbwr (void)
  1582 +void r4k_helper_tlbwr (void)
1592 1583 {
1593 1584 int r = cpu_mips_get_random(env);
1594 1585  
... ... @@ -1596,7 +1587,7 @@ void r4k_do_tlbwr (void)
1596 1587 r4k_fill_tlb(r);
1597 1588 }
1598 1589  
1599   -void r4k_do_tlbp (void)
  1590 +void r4k_helper_tlbp (void)
1600 1591 {
1601 1592 r4k_tlb_t *tlb;
1602 1593 target_ulong mask;
... ... @@ -1638,7 +1629,7 @@ void r4k_do_tlbp (void)
1638 1629 }
1639 1630 }
1640 1631  
1641   -void r4k_do_tlbr (void)
  1632 +void r4k_helper_tlbr (void)
1642 1633 {
1643 1634 r4k_tlb_t *tlb;
1644 1635 uint8_t ASID;
... ... @@ -1662,28 +1653,28 @@ void r4k_do_tlbr (void)
1662 1653 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1663 1654 }
1664 1655  
1665   -void do_tlbwi(void)
  1656 +void helper_tlbwi(void)
1666 1657 {
1667   - env->tlb->do_tlbwi();
  1658 + env->tlb->helper_tlbwi();
1668 1659 }
1669 1660  
1670   -void do_tlbwr(void)
  1661 +void helper_tlbwr(void)
1671 1662 {
1672   - env->tlb->do_tlbwr();
  1663 + env->tlb->helper_tlbwr();
1673 1664 }
1674 1665  
1675   -void do_tlbp(void)
  1666 +void helper_tlbp(void)
1676 1667 {
1677   - env->tlb->do_tlbp();
  1668 + env->tlb->helper_tlbp();
1678 1669 }
1679 1670  
1680   -void do_tlbr(void)
  1671 +void helper_tlbr(void)
1681 1672 {
1682   - env->tlb->do_tlbr();
  1673 + env->tlb->helper_tlbr();
1683 1674 }
1684 1675  
1685 1676 /* Specials */
1686   -target_ulong do_di (void)
  1677 +target_ulong helper_di (void)
1687 1678 {
1688 1679 target_ulong t0 = env->CP0_Status;
1689 1680  
... ... @@ -1693,7 +1684,7 @@ target_ulong do_di (void)
1693 1684 return t0;
1694 1685 }
1695 1686  
1696   -target_ulong do_ei (void)
  1687 +target_ulong helper_ei (void)
1697 1688 {
1698 1689 target_ulong t0 = env->CP0_Status;
1699 1690  
... ... @@ -1734,7 +1725,7 @@ static void debug_post_eret (void)
1734 1725 }
1735 1726 }
1736 1727  
1737   -void do_eret (void)
  1728 +void helper_eret (void)
1738 1729 {
1739 1730 debug_pre_eret();
1740 1731 if (env->CP0_Status & (1 << CP0St_ERL)) {
... ... @@ -1749,7 +1740,7 @@ void do_eret (void)
1749 1740 env->CP0_LLAddr = 1;
1750 1741 }
1751 1742  
1752   -void do_deret (void)
  1743 +void helper_deret (void)
1753 1744 {
1754 1745 debug_pre_eret();
1755 1746 env->active_tc.PC = env->CP0_DEPC;
... ... @@ -1760,51 +1751,51 @@ void do_deret (void)
1760 1751 }
1761 1752 #endif /* !CONFIG_USER_ONLY */
1762 1753  
1763   -target_ulong do_rdhwr_cpunum(void)
  1754 +target_ulong helper_rdhwr_cpunum(void)
1764 1755 {
1765 1756 if ((env->hflags & MIPS_HFLAG_CP0) ||
1766 1757 (env->CP0_HWREna & (1 << 0)))
1767 1758 return env->CP0_EBase & 0x3ff;
1768 1759 else
1769   - do_raise_exception(EXCP_RI);
  1760 + helper_raise_exception(EXCP_RI);
1770 1761  
1771 1762 return 0;
1772 1763 }
1773 1764  
1774   -target_ulong do_rdhwr_synci_step(void)
  1765 +target_ulong helper_rdhwr_synci_step(void)
1775 1766 {
1776 1767 if ((env->hflags & MIPS_HFLAG_CP0) ||
1777 1768 (env->CP0_HWREna & (1 << 1)))
1778 1769 return env->SYNCI_Step;
1779 1770 else
1780   - do_raise_exception(EXCP_RI);
  1771 + helper_raise_exception(EXCP_RI);
1781 1772  
1782 1773 return 0;
1783 1774 }
1784 1775  
1785   -target_ulong do_rdhwr_cc(void)
  1776 +target_ulong helper_rdhwr_cc(void)
1786 1777 {
1787 1778 if ((env->hflags & MIPS_HFLAG_CP0) ||
1788 1779 (env->CP0_HWREna & (1 << 2)))
1789 1780 return env->CP0_Count;
1790 1781 else
1791   - do_raise_exception(EXCP_RI);
  1782 + helper_raise_exception(EXCP_RI);
1792 1783  
1793 1784 return 0;
1794 1785 }
1795 1786  
1796   -target_ulong do_rdhwr_ccres(void)
  1787 +target_ulong helper_rdhwr_ccres(void)
1797 1788 {
1798 1789 if ((env->hflags & MIPS_HFLAG_CP0) ||
1799 1790 (env->CP0_HWREna & (1 << 3)))
1800 1791 return env->CCRes;
1801 1792 else
1802   - do_raise_exception(EXCP_RI);
  1793 + helper_raise_exception(EXCP_RI);
1803 1794  
1804 1795 return 0;
1805 1796 }
1806 1797  
1807   -void do_pmon (int function)
  1798 +void helper_pmon (int function)
1808 1799 {
1809 1800 function /= 2;
1810 1801 switch (function) {
... ... @@ -1830,10 +1821,10 @@ void do_pmon (int function)
1830 1821 }
1831 1822 }
1832 1823  
1833   -void do_wait (void)
  1824 +void helper_wait (void)
1834 1825 {
1835 1826 env->halted = 1;
1836   - do_raise_exception(EXCP_HLT);
  1827 + helper_raise_exception(EXCP_HLT);
1837 1828 }
1838 1829  
1839 1830 #if !defined(CONFIG_USER_ONLY)
... ... @@ -1859,7 +1850,7 @@ static void do_unaligned_access (target_ulong addr, int is_write, int is_user, v
1859 1850 {
1860 1851 env->CP0_BadVAddr = addr;
1861 1852 do_restore_state (retaddr);
1862   - do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
  1853 + helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
1863 1854 }
1864 1855  
1865 1856 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
... ... @@ -1885,7 +1876,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
1885 1876 cpu_restore_state(tb, env, pc, NULL);
1886 1877 }
1887 1878 }
1888   - do_raise_exception_err(env->exception_index, env->error_code);
  1879 + helper_raise_exception_err(env->exception_index, env->error_code);
1889 1880 }
1890 1881 env = saved_env;
1891 1882 }
... ... @@ -1894,9 +1885,9 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1894 1885 int unused, int size)
1895 1886 {
1896 1887 if (is_exec)
1897   - do_raise_exception(EXCP_IBE);
  1888 + helper_raise_exception(EXCP_IBE);
1898 1889 else
1899   - do_raise_exception(EXCP_DBE);
  1890 + helper_raise_exception(EXCP_DBE);
1900 1891 }
1901 1892 #endif /* !CONFIG_USER_ONLY */
1902 1893  
... ... @@ -1922,7 +1913,7 @@ unsigned int ieee_rm[] = {
1922 1913 #define RESTORE_ROUNDING_MODE \
1923 1914 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1924 1915  
1925   -target_ulong do_cfc1 (uint32_t reg)
  1916 +target_ulong helper_cfc1 (uint32_t reg)
1926 1917 {
1927 1918 target_ulong t0;
1928 1919  
... ... @@ -1947,7 +1938,7 @@ target_ulong do_cfc1 (uint32_t reg)
1947 1938 return t0;
1948 1939 }
1949 1940  
1950   -void do_ctc1 (target_ulong t0, uint32_t reg)
  1941 +void helper_ctc1 (target_ulong t0, uint32_t reg)
1951 1942 {
1952 1943 switch(reg) {
1953 1944 case 25:
... ... @@ -1979,7 +1970,7 @@ void do_ctc1 (target_ulong t0, uint32_t reg)
1979 1970 RESTORE_ROUNDING_MODE;
1980 1971 set_float_exception_flags(0, &env->active_fpu.fp_status);
1981 1972 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
1982   - do_raise_exception(EXCP_FPE);
  1973 + helper_raise_exception(EXCP_FPE);
1983 1974 }
1984 1975  
1985 1976 static inline char ieee_ex_to_mips(char xcpt)
... ... @@ -2006,7 +1997,7 @@ static inline void update_fcr31(void)
2006 1997  
2007 1998 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2008 1999 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
2009   - do_raise_exception(EXCP_FPE);
  2000 + helper_raise_exception(EXCP_FPE);
2010 2001 else
2011 2002 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2012 2003 }
... ... @@ -2017,17 +2008,17 @@ static inline void update_fcr31(void)
2017 2008 paired single lower "pl", paired single upper "pu". */
2018 2009  
2019 2010 /* unary operations, modifying fp status */
2020   -uint64_t do_float_sqrt_d(uint64_t fdt0)
  2011 +uint64_t helper_float_sqrt_d(uint64_t fdt0)
2021 2012 {
2022 2013 return float64_sqrt(fdt0, &env->active_fpu.fp_status);
2023 2014 }
2024 2015  
2025   -uint32_t do_float_sqrt_s(uint32_t fst0)
  2016 +uint32_t helper_float_sqrt_s(uint32_t fst0)
2026 2017 {
2027 2018 return float32_sqrt(fst0, &env->active_fpu.fp_status);
2028 2019 }
2029 2020  
2030   -uint64_t do_float_cvtd_s(uint32_t fst0)
  2021 +uint64_t helper_float_cvtd_s(uint32_t fst0)
2031 2022 {
2032 2023 uint64_t fdt2;
2033 2024  
... ... @@ -2037,7 +2028,7 @@ uint64_t do_float_cvtd_s(uint32_t fst0)
2037 2028 return fdt2;
2038 2029 }
2039 2030  
2040   -uint64_t do_float_cvtd_w(uint32_t wt0)
  2031 +uint64_t helper_float_cvtd_w(uint32_t wt0)
2041 2032 {
2042 2033 uint64_t fdt2;
2043 2034  
... ... @@ -2047,7 +2038,7 @@ uint64_t do_float_cvtd_w(uint32_t wt0)
2047 2038 return fdt2;
2048 2039 }
2049 2040  
2050   -uint64_t do_float_cvtd_l(uint64_t dt0)
  2041 +uint64_t helper_float_cvtd_l(uint64_t dt0)
2051 2042 {
2052 2043 uint64_t fdt2;
2053 2044  
... ... @@ -2057,7 +2048,7 @@ uint64_t do_float_cvtd_l(uint64_t dt0)
2057 2048 return fdt2;
2058 2049 }
2059 2050  
2060   -uint64_t do_float_cvtl_d(uint64_t fdt0)
  2051 +uint64_t helper_float_cvtl_d(uint64_t fdt0)
2061 2052 {
2062 2053 uint64_t dt2;
2063 2054  
... ... @@ -2069,7 +2060,7 @@ uint64_t do_float_cvtl_d(uint64_t fdt0)
2069 2060 return dt2;
2070 2061 }
2071 2062  
2072   -uint64_t do_float_cvtl_s(uint32_t fst0)
  2063 +uint64_t helper_float_cvtl_s(uint32_t fst0)
2073 2064 {
2074 2065 uint64_t dt2;
2075 2066  
... ... @@ -2081,7 +2072,7 @@ uint64_t do_float_cvtl_s(uint32_t fst0)
2081 2072 return dt2;
2082 2073 }
2083 2074  
2084   -uint64_t do_float_cvtps_pw(uint64_t dt0)
  2075 +uint64_t helper_float_cvtps_pw(uint64_t dt0)
2085 2076 {
2086 2077 uint32_t fst2;
2087 2078 uint32_t fsth2;
... ... @@ -2093,7 +2084,7 @@ uint64_t do_float_cvtps_pw(uint64_t dt0)
2093 2084 return ((uint64_t)fsth2 << 32) | fst2;
2094 2085 }
2095 2086  
2096   -uint64_t do_float_cvtpw_ps(uint64_t fdt0)
  2087 +uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
2097 2088 {
2098 2089 uint32_t wt2;
2099 2090 uint32_t wth2;
... ... @@ -2109,7 +2100,7 @@ uint64_t do_float_cvtpw_ps(uint64_t fdt0)
2109 2100 return ((uint64_t)wth2 << 32) | wt2;
2110 2101 }
2111 2102  
2112   -uint32_t do_float_cvts_d(uint64_t fdt0)
  2103 +uint32_t helper_float_cvts_d(uint64_t fdt0)
2113 2104 {
2114 2105 uint32_t fst2;
2115 2106  
... ... @@ -2119,7 +2110,7 @@ uint32_t do_float_cvts_d(uint64_t fdt0)
2119 2110 return fst2;
2120 2111 }
2121 2112  
2122   -uint32_t do_float_cvts_w(uint32_t wt0)
  2113 +uint32_t helper_float_cvts_w(uint32_t wt0)
2123 2114 {
2124 2115 uint32_t fst2;
2125 2116  
... ... @@ -2129,7 +2120,7 @@ uint32_t do_float_cvts_w(uint32_t wt0)
2129 2120 return fst2;
2130 2121 }
2131 2122  
2132   -uint32_t do_float_cvts_l(uint64_t dt0)
  2123 +uint32_t helper_float_cvts_l(uint64_t dt0)
2133 2124 {
2134 2125 uint32_t fst2;
2135 2126  
... ... @@ -2139,7 +2130,7 @@ uint32_t do_float_cvts_l(uint64_t dt0)
2139 2130 return fst2;
2140 2131 }
2141 2132  
2142   -uint32_t do_float_cvts_pl(uint32_t wt0)
  2133 +uint32_t helper_float_cvts_pl(uint32_t wt0)
2143 2134 {
2144 2135 uint32_t wt2;
2145 2136  
... ... @@ -2149,7 +2140,7 @@ uint32_t do_float_cvts_pl(uint32_t wt0)
2149 2140 return wt2;
2150 2141 }
2151 2142  
2152   -uint32_t do_float_cvts_pu(uint32_t wth0)
  2143 +uint32_t helper_float_cvts_pu(uint32_t wth0)
2153 2144 {
2154 2145 uint32_t wt2;
2155 2146  
... ... @@ -2159,7 +2150,7 @@ uint32_t do_float_cvts_pu(uint32_t wth0)
2159 2150 return wt2;
2160 2151 }
2161 2152  
2162   -uint32_t do_float_cvtw_s(uint32_t fst0)
  2153 +uint32_t helper_float_cvtw_s(uint32_t fst0)
2163 2154 {
2164 2155 uint32_t wt2;
2165 2156  
... ... @@ -2171,7 +2162,7 @@ uint32_t do_float_cvtw_s(uint32_t fst0)
2171 2162 return wt2;
2172 2163 }
2173 2164  
2174   -uint32_t do_float_cvtw_d(uint64_t fdt0)
  2165 +uint32_t helper_float_cvtw_d(uint64_t fdt0)
2175 2166 {
2176 2167 uint32_t wt2;
2177 2168  
... ... @@ -2183,7 +2174,7 @@ uint32_t do_float_cvtw_d(uint64_t fdt0)
2183 2174 return wt2;
2184 2175 }
2185 2176  
2186   -uint64_t do_float_roundl_d(uint64_t fdt0)
  2177 +uint64_t helper_float_roundl_d(uint64_t fdt0)
2187 2178 {
2188 2179 uint64_t dt2;
2189 2180  
... ... @@ -2196,7 +2187,7 @@ uint64_t do_float_roundl_d(uint64_t fdt0)
2196 2187 return dt2;
2197 2188 }
2198 2189  
2199   -uint64_t do_float_roundl_s(uint32_t fst0)
  2190 +uint64_t helper_float_roundl_s(uint32_t fst0)
2200 2191 {
2201 2192 uint64_t dt2;
2202 2193  
... ... @@ -2209,7 +2200,7 @@ uint64_t do_float_roundl_s(uint32_t fst0)
2209 2200 return dt2;
2210 2201 }
2211 2202  
2212   -uint32_t do_float_roundw_d(uint64_t fdt0)
  2203 +uint32_t helper_float_roundw_d(uint64_t fdt0)
2213 2204 {
2214 2205 uint32_t wt2;
2215 2206  
... ... @@ -2222,7 +2213,7 @@ uint32_t do_float_roundw_d(uint64_t fdt0)
2222 2213 return wt2;
2223 2214 }
2224 2215  
2225   -uint32_t do_float_roundw_s(uint32_t fst0)
  2216 +uint32_t helper_float_roundw_s(uint32_t fst0)
2226 2217 {
2227 2218 uint32_t wt2;
2228 2219  
... ... @@ -2235,7 +2226,7 @@ uint32_t do_float_roundw_s(uint32_t fst0)
2235 2226 return wt2;
2236 2227 }
2237 2228  
2238   -uint64_t do_float_truncl_d(uint64_t fdt0)
  2229 +uint64_t helper_float_truncl_d(uint64_t fdt0)
2239 2230 {
2240 2231 uint64_t dt2;
2241 2232  
... ... @@ -2246,7 +2237,7 @@ uint64_t do_float_truncl_d(uint64_t fdt0)
2246 2237 return dt2;
2247 2238 }
2248 2239  
2249   -uint64_t do_float_truncl_s(uint32_t fst0)
  2240 +uint64_t helper_float_truncl_s(uint32_t fst0)
2250 2241 {
2251 2242 uint64_t dt2;
2252 2243  
... ... @@ -2257,7 +2248,7 @@ uint64_t do_float_truncl_s(uint32_t fst0)
2257 2248 return dt2;
2258 2249 }
2259 2250  
2260   -uint32_t do_float_truncw_d(uint64_t fdt0)
  2251 +uint32_t helper_float_truncw_d(uint64_t fdt0)
2261 2252 {
2262 2253 uint32_t wt2;
2263 2254  
... ... @@ -2268,7 +2259,7 @@ uint32_t do_float_truncw_d(uint64_t fdt0)
2268 2259 return wt2;
2269 2260 }
2270 2261  
2271   -uint32_t do_float_truncw_s(uint32_t fst0)
  2262 +uint32_t helper_float_truncw_s(uint32_t fst0)
2272 2263 {
2273 2264 uint32_t wt2;
2274 2265  
... ... @@ -2279,7 +2270,7 @@ uint32_t do_float_truncw_s(uint32_t fst0)
2279 2270 return wt2;
2280 2271 }
2281 2272  
2282   -uint64_t do_float_ceill_d(uint64_t fdt0)
  2273 +uint64_t helper_float_ceill_d(uint64_t fdt0)
2283 2274 {
2284 2275 uint64_t dt2;
2285 2276  
... ... @@ -2292,7 +2283,7 @@ uint64_t do_float_ceill_d(uint64_t fdt0)
2292 2283 return dt2;
2293 2284 }
2294 2285  
2295   -uint64_t do_float_ceill_s(uint32_t fst0)
  2286 +uint64_t helper_float_ceill_s(uint32_t fst0)
2296 2287 {
2297 2288 uint64_t dt2;
2298 2289  
... ... @@ -2305,7 +2296,7 @@ uint64_t do_float_ceill_s(uint32_t fst0)
2305 2296 return dt2;
2306 2297 }
2307 2298  
2308   -uint32_t do_float_ceilw_d(uint64_t fdt0)
  2299 +uint32_t helper_float_ceilw_d(uint64_t fdt0)
2309 2300 {
2310 2301 uint32_t wt2;
2311 2302  
... ... @@ -2318,7 +2309,7 @@ uint32_t do_float_ceilw_d(uint64_t fdt0)
2318 2309 return wt2;
2319 2310 }
2320 2311  
2321   -uint32_t do_float_ceilw_s(uint32_t fst0)
  2312 +uint32_t helper_float_ceilw_s(uint32_t fst0)
2322 2313 {
2323 2314 uint32_t wt2;
2324 2315  
... ... @@ -2331,7 +2322,7 @@ uint32_t do_float_ceilw_s(uint32_t fst0)
2331 2322 return wt2;
2332 2323 }
2333 2324  
2334   -uint64_t do_float_floorl_d(uint64_t fdt0)
  2325 +uint64_t helper_float_floorl_d(uint64_t fdt0)
2335 2326 {
2336 2327 uint64_t dt2;
2337 2328  
... ... @@ -2344,7 +2335,7 @@ uint64_t do_float_floorl_d(uint64_t fdt0)
2344 2335 return dt2;
2345 2336 }
2346 2337  
2347   -uint64_t do_float_floorl_s(uint32_t fst0)
  2338 +uint64_t helper_float_floorl_s(uint32_t fst0)
2348 2339 {
2349 2340 uint64_t dt2;
2350 2341  
... ... @@ -2357,7 +2348,7 @@ uint64_t do_float_floorl_s(uint32_t fst0)
2357 2348 return dt2;
2358 2349 }
2359 2350  
2360   -uint32_t do_float_floorw_d(uint64_t fdt0)
  2351 +uint32_t helper_float_floorw_d(uint64_t fdt0)
2361 2352 {
2362 2353 uint32_t wt2;
2363 2354  
... ... @@ -2370,7 +2361,7 @@ uint32_t do_float_floorw_d(uint64_t fdt0)
2370 2361 return wt2;
2371 2362 }
2372 2363  
2373   -uint32_t do_float_floorw_s(uint32_t fst0)
  2364 +uint32_t helper_float_floorw_s(uint32_t fst0)
2374 2365 {
2375 2366 uint32_t wt2;
2376 2367  
... ... @@ -2385,15 +2376,15 @@ uint32_t do_float_floorw_s(uint32_t fst0)
2385 2376  
2386 2377 /* unary operations, not modifying fp status */
2387 2378 #define FLOAT_UNOP(name) \
2388   -uint64_t do_float_ ## name ## _d(uint64_t fdt0) \
  2379 +uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2389 2380 { \
2390 2381 return float64_ ## name(fdt0); \
2391 2382 } \
2392   -uint32_t do_float_ ## name ## _s(uint32_t fst0) \
  2383 +uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2393 2384 { \
2394 2385 return float32_ ## name(fst0); \
2395 2386 } \
2396   -uint64_t do_float_ ## name ## _ps(uint64_t fdt0) \
  2387 +uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2397 2388 { \
2398 2389 uint32_t wt0; \
2399 2390 uint32_t wth0; \
... ... @@ -2407,7 +2398,7 @@ FLOAT_UNOP(chs)
2407 2398 #undef FLOAT_UNOP
2408 2399  
2409 2400 /* MIPS specific unary operations */
2410   -uint64_t do_float_recip_d(uint64_t fdt0)
  2401 +uint64_t helper_float_recip_d(uint64_t fdt0)
2411 2402 {
2412 2403 uint64_t fdt2;
2413 2404  
... ... @@ -2417,7 +2408,7 @@ uint64_t do_float_recip_d(uint64_t fdt0)
2417 2408 return fdt2;
2418 2409 }
2419 2410  
2420   -uint32_t do_float_recip_s(uint32_t fst0)
  2411 +uint32_t helper_float_recip_s(uint32_t fst0)
2421 2412 {
2422 2413 uint32_t fst2;
2423 2414  
... ... @@ -2427,7 +2418,7 @@ uint32_t do_float_recip_s(uint32_t fst0)
2427 2418 return fst2;
2428 2419 }
2429 2420  
2430   -uint64_t do_float_rsqrt_d(uint64_t fdt0)
  2421 +uint64_t helper_float_rsqrt_d(uint64_t fdt0)
2431 2422 {
2432 2423 uint64_t fdt2;
2433 2424  
... ... @@ -2438,7 +2429,7 @@ uint64_t do_float_rsqrt_d(uint64_t fdt0)
2438 2429 return fdt2;
2439 2430 }
2440 2431  
2441   -uint32_t do_float_rsqrt_s(uint32_t fst0)
  2432 +uint32_t helper_float_rsqrt_s(uint32_t fst0)
2442 2433 {
2443 2434 uint32_t fst2;
2444 2435  
... ... @@ -2449,7 +2440,7 @@ uint32_t do_float_rsqrt_s(uint32_t fst0)
2449 2440 return fst2;
2450 2441 }
2451 2442  
2452   -uint64_t do_float_recip1_d(uint64_t fdt0)
  2443 +uint64_t helper_float_recip1_d(uint64_t fdt0)
2453 2444 {
2454 2445 uint64_t fdt2;
2455 2446  
... ... @@ -2459,7 +2450,7 @@ uint64_t do_float_recip1_d(uint64_t fdt0)
2459 2450 return fdt2;
2460 2451 }
2461 2452  
2462   -uint32_t do_float_recip1_s(uint32_t fst0)
  2453 +uint32_t helper_float_recip1_s(uint32_t fst0)
2463 2454 {
2464 2455 uint32_t fst2;
2465 2456  
... ... @@ -2469,7 +2460,7 @@ uint32_t do_float_recip1_s(uint32_t fst0)
2469 2460 return fst2;
2470 2461 }
2471 2462  
2472   -uint64_t do_float_recip1_ps(uint64_t fdt0)
  2463 +uint64_t helper_float_recip1_ps(uint64_t fdt0)
2473 2464 {
2474 2465 uint32_t fst2;
2475 2466 uint32_t fsth2;
... ... @@ -2481,7 +2472,7 @@ uint64_t do_float_recip1_ps(uint64_t fdt0)
2481 2472 return ((uint64_t)fsth2 << 32) | fst2;
2482 2473 }
2483 2474  
2484   -uint64_t do_float_rsqrt1_d(uint64_t fdt0)
  2475 +uint64_t helper_float_rsqrt1_d(uint64_t fdt0)
2485 2476 {
2486 2477 uint64_t fdt2;
2487 2478  
... ... @@ -2492,7 +2483,7 @@ uint64_t do_float_rsqrt1_d(uint64_t fdt0)
2492 2483 return fdt2;
2493 2484 }
2494 2485  
2495   -uint32_t do_float_rsqrt1_s(uint32_t fst0)
  2486 +uint32_t helper_float_rsqrt1_s(uint32_t fst0)
2496 2487 {
2497 2488 uint32_t fst2;
2498 2489  
... ... @@ -2503,7 +2494,7 @@ uint32_t do_float_rsqrt1_s(uint32_t fst0)
2503 2494 return fst2;
2504 2495 }
2505 2496  
2506   -uint64_t do_float_rsqrt1_ps(uint64_t fdt0)
  2497 +uint64_t helper_float_rsqrt1_ps(uint64_t fdt0)
2507 2498 {
2508 2499 uint32_t fst2;
2509 2500 uint32_t fsth2;
... ... @@ -2517,11 +2508,11 @@ uint64_t do_float_rsqrt1_ps(uint64_t fdt0)
2517 2508 return ((uint64_t)fsth2 << 32) | fst2;
2518 2509 }
2519 2510  
2520   -#define FLOAT_OP(name, p) void do_float_##name##_##p(void)
  2511 +#define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
2521 2512  
2522 2513 /* binary operations */
2523 2514 #define FLOAT_BINOP(name) \
2524   -uint64_t do_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
  2515 +uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
2525 2516 { \
2526 2517 uint64_t dt2; \
2527 2518 \
... ... @@ -2533,7 +2524,7 @@ uint64_t do_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
2533 2524 return dt2; \
2534 2525 } \
2535 2526 \
2536   -uint32_t do_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
  2527 +uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
2537 2528 { \
2538 2529 uint32_t wt2; \
2539 2530 \
... ... @@ -2545,7 +2536,7 @@ uint32_t do_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
2545 2536 return wt2; \
2546 2537 } \
2547 2538 \
2548   -uint64_t do_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
  2539 +uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
2549 2540 { \
2550 2541 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2551 2542 uint32_t fsth0 = fdt0 >> 32; \
... ... @@ -2573,21 +2564,21 @@ FLOAT_BINOP(div)
2573 2564  
2574 2565 /* ternary operations */
2575 2566 #define FLOAT_TERNOP(name1, name2) \
2576   -uint64_t do_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
  2567 +uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2577 2568 uint64_t fdt2) \
2578 2569 { \
2579 2570 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2580 2571 return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2581 2572 } \
2582 2573 \
2583   -uint32_t do_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
  2574 +uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2584 2575 uint32_t fst2) \
2585 2576 { \
2586 2577 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2587 2578 return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2588 2579 } \
2589 2580 \
2590   -uint64_t do_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
  2581 +uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
2591 2582 uint64_t fdt2) \
2592 2583 { \
2593 2584 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
... ... @@ -2610,7 +2601,7 @@ FLOAT_TERNOP(mul, sub)
2610 2601  
2611 2602 /* negated ternary operations */
2612 2603 #define FLOAT_NTERNOP(name1, name2) \
2613   -uint64_t do_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
  2604 +uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2614 2605 uint64_t fdt2) \
2615 2606 { \
2616 2607 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
... ... @@ -2618,7 +2609,7 @@ uint64_t do_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2618 2609 return float64_chs(fdt2); \
2619 2610 } \
2620 2611 \
2621   -uint32_t do_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
  2612 +uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2622 2613 uint32_t fst2) \
2623 2614 { \
2624 2615 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
... ... @@ -2626,7 +2617,7 @@ uint32_t do_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2626 2617 return float32_chs(fst2); \
2627 2618 } \
2628 2619 \
2629   -uint64_t do_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
  2620 +uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
2630 2621 uint64_t fdt2) \
2631 2622 { \
2632 2623 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
... ... @@ -2650,7 +2641,7 @@ FLOAT_NTERNOP(mul, sub)
2650 2641 #undef FLOAT_NTERNOP
2651 2642  
2652 2643 /* MIPS specific binary operations */
2653   -uint64_t do_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
  2644 +uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
2654 2645 {
2655 2646 set_float_exception_flags(0, &env->active_fpu.fp_status);
2656 2647 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
... ... @@ -2659,7 +2650,7 @@ uint64_t do_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
2659 2650 return fdt2;
2660 2651 }
2661 2652  
2662   -uint32_t do_float_recip2_s(uint32_t fst0, uint32_t fst2)
  2653 +uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2)
2663 2654 {
2664 2655 set_float_exception_flags(0, &env->active_fpu.fp_status);
2665 2656 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
... ... @@ -2668,7 +2659,7 @@ uint32_t do_float_recip2_s(uint32_t fst0, uint32_t fst2)
2668 2659 return fst2;
2669 2660 }
2670 2661  
2671   -uint64_t do_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
  2662 +uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
2672 2663 {
2673 2664 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2674 2665 uint32_t fsth0 = fdt0 >> 32;
... ... @@ -2684,7 +2675,7 @@ uint64_t do_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
2684 2675 return ((uint64_t)fsth2 << 32) | fst2;
2685 2676 }
2686 2677  
2687   -uint64_t do_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
  2678 +uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
2688 2679 {
2689 2680 set_float_exception_flags(0, &env->active_fpu.fp_status);
2690 2681 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
... ... @@ -2694,7 +2685,7 @@ uint64_t do_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
2694 2685 return fdt2;
2695 2686 }
2696 2687  
2697   -uint32_t do_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
  2688 +uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
2698 2689 {
2699 2690 set_float_exception_flags(0, &env->active_fpu.fp_status);
2700 2691 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
... ... @@ -2704,7 +2695,7 @@ uint32_t do_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
2704 2695 return fst2;
2705 2696 }
2706 2697  
2707   -uint64_t do_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
  2698 +uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
2708 2699 {
2709 2700 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2710 2701 uint32_t fsth0 = fdt0 >> 32;
... ... @@ -2722,7 +2713,7 @@ uint64_t do_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
2722 2713 return ((uint64_t)fsth2 << 32) | fst2;
2723 2714 }
2724 2715  
2725   -uint64_t do_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
  2716 +uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
2726 2717 {
2727 2718 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2728 2719 uint32_t fsth0 = fdt0 >> 32;
... ... @@ -2738,7 +2729,7 @@ uint64_t do_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
2738 2729 return ((uint64_t)fsth2 << 32) | fst2;
2739 2730 }
2740 2731  
2741   -uint64_t do_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
  2732 +uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
2742 2733 {
2743 2734 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2744 2735 uint32_t fsth0 = fdt0 >> 32;
... ... @@ -2756,7 +2747,7 @@ uint64_t do_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
2756 2747  
2757 2748 /* compare operations */
2758 2749 #define FOP_COND_D(op, cond) \
2759   -void do_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
  2750 +void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2760 2751 { \
2761 2752 int c = cond; \
2762 2753 update_fcr31(); \
... ... @@ -2765,7 +2756,7 @@ void do_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2765 2756 else \
2766 2757 CLEAR_FP_COND(cc, env->active_fpu); \
2767 2758 } \
2768   -void do_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
  2759 +void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2769 2760 { \
2770 2761 int c; \
2771 2762 fdt0 = float64_abs(fdt0); \
... ... @@ -2814,7 +2805,7 @@ FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &amp;env-&gt;active_fpu.fp_status)
2814 2805 FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2815 2806  
2816 2807 #define FOP_COND_S(op, cond) \
2817   -void do_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
  2808 +void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2818 2809 { \
2819 2810 int c = cond; \
2820 2811 update_fcr31(); \
... ... @@ -2823,7 +2814,7 @@ void do_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2823 2814 else \
2824 2815 CLEAR_FP_COND(cc, env->active_fpu); \
2825 2816 } \
2826   -void do_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
  2817 +void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2827 2818 { \
2828 2819 int c; \
2829 2820 fst0 = float32_abs(fst0); \
... ... @@ -2872,7 +2863,7 @@ FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &amp;env-&gt;active_fpu.fp_status)
2872 2863 FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
2873 2864  
2874 2865 #define FOP_COND_PS(op, condl, condh) \
2875   -void do_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
  2866 +void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2876 2867 { \
2877 2868 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2878 2869 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
... ... @@ -2891,7 +2882,7 @@ void do_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2891 2882 else \
2892 2883 CLEAR_FP_COND(cc + 1, env->active_fpu); \
2893 2884 } \
2894   -void do_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
  2885 +void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2895 2886 { \
2896 2887 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2897 2888 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
... ...
target-mips/translate.c
  View file @c01fccd
... ... @@ -5451,25 +5451,25 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5451 5451 break;
5452 5452 case OPC_TLBWI:
5453 5453 opn = "tlbwi";
5454   - if (!env->tlb->do_tlbwi)
  5454 + if (!env->tlb->helper_tlbwi)
5455 5455 goto die;
5456 5456 gen_helper_tlbwi();
5457 5457 break;
5458 5458 case OPC_TLBWR:
5459 5459 opn = "tlbwr";
5460   - if (!env->tlb->do_tlbwr)
  5460 + if (!env->tlb->helper_tlbwr)
5461 5461 goto die;
5462 5462 gen_helper_tlbwr();
5463 5463 break;
5464 5464 case OPC_TLBP:
5465 5465 opn = "tlbp";
5466   - if (!env->tlb->do_tlbp)
  5466 + if (!env->tlb->helper_tlbp)
5467 5467 goto die;
5468 5468 gen_helper_tlbp();
5469 5469 break;
5470 5470 case OPC_TLBR:
5471 5471 opn = "tlbr";
5472   - if (!env->tlb->do_tlbr)
  5472 + if (!env->tlb->helper_tlbr)
5473 5473 goto die;
5474 5474 gen_helper_tlbr();
5475 5475 break;
... ...
target-mips/translate_init.c
  View file @c01fccd
... ... @@ -456,10 +456,10 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
456 456 {
457 457 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
458 458 env->tlb->map_address = &r4k_map_address;
459   - env->tlb->do_tlbwi = r4k_do_tlbwi;
460   - env->tlb->do_tlbwr = r4k_do_tlbwr;
461   - env->tlb->do_tlbp = r4k_do_tlbp;
462   - env->tlb->do_tlbr = r4k_do_tlbr;
  459 + env->tlb->helper_tlbwi = r4k_helper_tlbwi;
  460 + env->tlb->helper_tlbwr = r4k_helper_tlbwr;
  461 + env->tlb->helper_tlbp = r4k_helper_tlbp;
  462 + env->tlb->helper_tlbr = r4k_helper_tlbr;
463 463 }
464 464  
465 465 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
... ...