gwj / at91sam9263 · Commits

Commit bf8d8ded57a6c54d9ff8a55c35201301ff61ece7

Authored by aurel32
1 parent e343da72

Add lvs{l,r} instructions. 

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6169 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 52 additions and 0 deletions
target-ppc/helper.h
  View file @bf8d8de
@@ -150,6 +150,8 @@ DEF_HELPER_3(vslo, void, avr, avr, avr) @@ -150,6 +150,8 @@ DEF_HELPER_3(vslo, void, avr, avr, avr)
150 DEF_HELPER_3(vsro, void, avr, avr, avr) 150 DEF_HELPER_3(vsro, void, avr, avr, avr)
151 DEF_HELPER_3(vaddcuw, void, avr, avr, avr) 151 DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
152 DEF_HELPER_3(vsubcuw, void, avr, avr, avr) 152 DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
  153 +DEF_HELPER_2(lvsl, void, avr, tl);
  154 +DEF_HELPER_2(lvsr, void, avr, tl);
153 155
154 DEF_HELPER_1(efscfsi, i32, i32) 156 DEF_HELPER_1(efscfsi, i32, i32)
155 DEF_HELPER_1(efscfui, i32, i32) 157 DEF_HELPER_1(efscfui, i32, i32)
target-ppc/op_helper.c
  View file @bf8d8de
@@ -1972,6 +1972,24 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_ @@ -1972,6 +1972,24 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_
1972 for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--) 1972 for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
1973 #endif 1973 #endif
1974 1974
  1975 +void helper_lvsl (ppc_avr_t *r, target_ulong sh)
  1976 +{
  1977 + int i, j = (sh & 0xf);
  1978 +
  1979 + VECTOR_FOR_INORDER_I (i, u8) {
  1980 + r->u8[i] = j++;
  1981 + }
  1982 +}
  1983 +
  1984 +void helper_lvsr (ppc_avr_t *r, target_ulong sh)
  1985 +{
  1986 + int i, j = 0x10 - (sh & 0xf);
  1987 +
  1988 + VECTOR_FOR_INORDER_I (i, u8) {
  1989 + r->u8[i] = j++;
  1990 + }
  1991 +}
  1992 +
1975 void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) 1993 void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
1976 { 1994 {
1977 int i; 1995 int i;
target-ppc/translate.c
  View file @bf8d8de
@@ -6146,6 +6146,38 @@ GEN_VR_STX(svx, 0x07, 0x07); @@ -6146,6 +6146,38 @@ GEN_VR_STX(svx, 0x07, 0x07);
6146 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ 6146 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6147 GEN_VR_STX(svxl, 0x07, 0x0F); 6147 GEN_VR_STX(svxl, 0x07, 0x0F);
6148 6148
  6149 +GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
  6150 +{
  6151 + TCGv_ptr rd;
  6152 + TCGv EA;
  6153 + if (unlikely(!ctx->altivec_enabled)) {
  6154 + gen_exception(ctx, POWERPC_EXCP_VPU);
  6155 + return;
  6156 + }
  6157 + EA = tcg_temp_new();
  6158 + gen_addr_reg_index(ctx, EA);
  6159 + rd = gen_avr_ptr(rD(ctx->opcode));
  6160 + gen_helper_lvsl(rd, EA);
  6161 + tcg_temp_free(EA);
  6162 + tcg_temp_free_ptr(rd);
  6163 +}
  6164 +
  6165 +GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
  6166 +{
  6167 + TCGv_ptr rd;
  6168 + TCGv EA;
  6169 + if (unlikely(!ctx->altivec_enabled)) {
  6170 + gen_exception(ctx, POWERPC_EXCP_VPU);
  6171 + return;
  6172 + }
  6173 + EA = tcg_temp_new();
  6174 + gen_addr_reg_index(ctx, EA);
  6175 + rd = gen_avr_ptr(rD(ctx->opcode));
  6176 + gen_helper_lvsr(rd, EA);
  6177 + tcg_temp_free(EA);
  6178 + tcg_temp_free_ptr(rd);
  6179 +}
  6180 +
6149 /* Logical operations */ 6181 /* Logical operations */
6150 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ 6182 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6151 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \ 6183 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \