Commit bf5b74230819b27c43d479409df6851077392801

Authored by aurel32
1 parent ea2b542a

SH4 serial controler improvements

(Shin-ichiro KAWASAKI)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4397 c046a42c-6fe2-441c-8c8c-71466251a162
@@ -35,7 +35,12 @@ void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq, @@ -35,7 +35,12 @@ void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
35 /* sh_serial.c */ 35 /* sh_serial.c */
36 #define SH_SERIAL_FEAT_SCIF (1 << 0) 36 #define SH_SERIAL_FEAT_SCIF (1 << 0)
37 void sh_serial_init (target_phys_addr_t base, int feat, 37 void sh_serial_init (target_phys_addr_t base, int feat,
38 - uint32_t freq, CharDriverState *chr); 38 + uint32_t freq, CharDriverState *chr,
  39 + struct intc_source *eri_source,
  40 + struct intc_source *rxi_source,
  41 + struct intc_source *txi_source,
  42 + struct intc_source *tei_source,
  43 + struct intc_source *bri_source);
39 44
40 /* tc58128.c */ 45 /* tc58128.c */
41 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2); 46 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
hw/sh7750.c
@@ -556,9 +556,19 @@ SH7750State *sh7750_init(CPUSH4State * cpu) @@ -556,9 +556,19 @@ SH7750State *sh7750_init(CPUSH4State * cpu)
556 556
557 cpu->intc_handle = &s->intc; 557 cpu->intc_handle = &s->intc;
558 558
559 - sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0]); 559 + sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0],
  560 + sh_intc_source(&s->intc, SCI1_ERI),
  561 + sh_intc_source(&s->intc, SCI1_RXI),
  562 + sh_intc_source(&s->intc, SCI1_TXI),
  563 + sh_intc_source(&s->intc, SCI1_TEI),
  564 + NULL);
560 sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF, 565 sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
561 - s->periph_freq, serial_hds[1]); 566 + s->periph_freq, serial_hds[1],
  567 + sh_intc_source(&s->intc, SCIF_ERI),
  568 + sh_intc_source(&s->intc, SCIF_RXI),
  569 + sh_intc_source(&s->intc, SCIF_TXI),
  570 + NULL,
  571 + sh_intc_source(&s->intc, SCIF_BRI));
562 572
563 tmu012_init(0x1fd80000, 573 tmu012_init(0x1fd80000,
564 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, 574 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
hw/sh_serial.c
@@ -55,6 +55,12 @@ typedef struct { @@ -55,6 +55,12 @@ typedef struct {
55 int flags; 55 int flags;
56 56
57 CharDriverState *chr; 57 CharDriverState *chr;
  58 +
  59 + struct intc_source *eri;
  60 + struct intc_source *rxi;
  61 + struct intc_source *txi;
  62 + struct intc_source *tei;
  63 + struct intc_source *bri;
58 } sh_serial_state; 64 } sh_serial_state;
59 65
60 static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val) 66 static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val)
@@ -74,9 +80,15 @@ static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val) @@ -74,9 +80,15 @@ static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val)
74 s->brr = val; 80 s->brr = val;
75 return; 81 return;
76 case 0x08: /* SCR */ 82 case 0x08: /* SCR */
77 - s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfb : 0xff); 83 + s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
78 if (!(val & (1 << 5))) 84 if (!(val & (1 << 5)))
79 s->flags |= SH_SERIAL_FLAG_TEND; 85 s->flags |= SH_SERIAL_FLAG_TEND;
  86 + if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
  87 + if ((val & (1 << 7)) && !(s->txi->asserted))
  88 + sh_intc_toggle_source(s->txi, 0, 1);
  89 + else if (!(val & (1 << 7)) && s->txi->asserted)
  90 + sh_intc_toggle_source(s->txi, 0, -1);
  91 + }
80 return; 92 return;
81 case 0x0c: /* FTDR / TDR */ 93 case 0x0c: /* FTDR / TDR */
82 if (s->chr) { 94 if (s->chr) {
@@ -159,6 +171,12 @@ static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs) @@ -159,6 +171,12 @@ static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs)
159 #endif 171 #endif
160 if (s->feat & SH_SERIAL_FEAT_SCIF) { 172 if (s->feat & SH_SERIAL_FEAT_SCIF) {
161 switch(offs) { 173 switch(offs) {
  174 + case 0x00: /* SMR */
  175 + ret = s->smr;
  176 + break;
  177 + case 0x08: /* SCR */
  178 + ret = s->scr;
  179 + break;
162 case 0x10: /* FSR */ 180 case 0x10: /* FSR */
163 ret = 0; 181 ret = 0;
164 if (s->flags & SH_SERIAL_FLAG_TEND) 182 if (s->flags & SH_SERIAL_FLAG_TEND)
@@ -278,7 +296,12 @@ static CPUWriteMemoryFunc *sh_serial_writefn[] = { @@ -278,7 +296,12 @@ static CPUWriteMemoryFunc *sh_serial_writefn[] = {
278 }; 296 };
279 297
280 void sh_serial_init (target_phys_addr_t base, int feat, 298 void sh_serial_init (target_phys_addr_t base, int feat,
281 - uint32_t freq, CharDriverState *chr) 299 + uint32_t freq, CharDriverState *chr,
  300 + struct intc_source *eri_source,
  301 + struct intc_source *rxi_source,
  302 + struct intc_source *txi_source,
  303 + struct intc_source *tei_source,
  304 + struct intc_source *bri_source)
282 { 305 {
283 sh_serial_state *s; 306 sh_serial_state *s;
284 int s_io_memory; 307 int s_io_memory;
@@ -314,4 +337,10 @@ void sh_serial_init (target_phys_addr_t base, int feat, @@ -314,4 +337,10 @@ void sh_serial_init (target_phys_addr_t base, int feat,
314 if (chr) 337 if (chr)
315 qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1, 338 qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,
316 sh_serial_event, s); 339 sh_serial_event, s);
  340 +
  341 + s->eri = eri_source;
  342 + s->rxi = rxi_source;
  343 + s->txi = txi_source;
  344 + s->tei = tei_source;
  345 + s->bri = bri_source;
317 } 346 }