gwj / at91sam9263 · Commits

Commit bf079a1e703f8d58ba7dcd9b0bcd793e66c962f4

Authored by bellard
1 parent 9df217a3

enabled MMX, PAE and SEP 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1284 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 9 additions and 3 deletions
target-i386/helper2.c
  View file @bf079a1
@@ -98,7 +98,7 @@ CPUX86State *cpu_x86_init(void) @@ -98,7 +98,7 @@ CPUX86State *cpu_x86_init(void)
98 #else 98 #else
99 /* pentium pro */ 99 /* pentium pro */
100 family = 6; 100 family = 6;
101 - model = 1; 101 + model = 3;
102 stepping = 3; 102 stepping = 3;
103 #endif 103 #endif
104 #endif 104 #endif
@@ -106,14 +106,18 @@ CPUX86State *cpu_x86_init(void) @@ -106,14 +106,18 @@ CPUX86State *cpu_x86_init(void)
106 env->cpuid_features = (CPUID_FP87 | CPUID_DE | CPUID_PSE | 106 env->cpuid_features = (CPUID_FP87 | CPUID_DE | CPUID_PSE |
107 CPUID_TSC | CPUID_MSR | CPUID_MCE | 107 CPUID_TSC | CPUID_MSR | CPUID_MCE |
108 CPUID_CX8 | CPUID_PGE | CPUID_CMOV); 108 CPUID_CX8 | CPUID_PGE | CPUID_CMOV);
  109 + env->cpuid_ext_features = 0;
  110 + env->cpuid_features |= CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | CPUID_PAE | CPUID_SEP;
109 #ifdef TARGET_X86_64 111 #ifdef TARGET_X86_64
110 /* currently not enabled for std i386 because not fully tested */ 112 /* currently not enabled for std i386 because not fully tested */
111 - env->cpuid_features |= CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2;  
112 - env->cpuid_features |= CPUID_APIC | CPUID_PAE; 113 + env->cpuid_features |= CPUID_APIC;
113 #endif 114 #endif
114 } 115 }
115 cpu_single_env = env; 116 cpu_single_env = env;
116 cpu_reset(env); 117 cpu_reset(env);
  118 +#ifdef USE_KQEMU
  119 + kqemu_init(env);
  120 +#endif
117 return env; 121 return env;
118 } 122 }
119 123
@@ -453,6 +457,8 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) @@ -453,6 +457,8 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
453 ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)); 457 ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
454 } 458 }
455 459
  460 +/* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
  461 + the PDPT */
456 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3) 462 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
457 { 463 {
458 env->cr[3] = new_cr3; 464 env->cr[3] = new_cr3;