Commit beddab753d0b3e971bfe46f165524a1c24229c29
1 parent
512176db
arm load/store half word fix (Ulrich Hecht)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@785 c046a42c-6fe2-441c-8c8c-71466251a162
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target-arm/translate.c
| @@ -543,7 +543,8 @@ static void disas_arm_insn(DisasContext *s) | @@ -543,7 +543,8 @@ static void disas_arm_insn(DisasContext *s) | ||
| 543 | rn = (insn >> 16) & 0xf; | 543 | rn = (insn >> 16) & 0xf; |
| 544 | rd = (insn >> 12) & 0xf; | 544 | rd = (insn >> 12) & 0xf; |
| 545 | gen_movl_T1_reg(s, rn); | 545 | gen_movl_T1_reg(s, rn); |
| 546 | - gen_add_datah_offset(s, insn); | 546 | + if (insn & (1 << 24)) |
| 547 | + gen_add_datah_offset(s, insn); | ||
| 547 | if (insn & (1 << 20)) { | 548 | if (insn & (1 << 20)) { |
| 548 | /* load */ | 549 | /* load */ |
| 549 | switch(sh) { | 550 | switch(sh) { |