gwj / at91sam9263 · Commits

Commit bd928ebafe5a5e318d5ec71c1aec4400721179ae

Authored by j_mayer
1 parent 325e651f

Fix PowerPC 7xx definitions. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3713 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 630 additions and 133 deletions
target-ppc/cpu.h
  View file @bd928eb
@@ -357,6 +357,7 @@ union ppc_tlb_t { @@ -357,6 +357,7 @@ union ppc_tlb_t {
357 /*****************************************************************************/ 357 /*****************************************************************************/
358 /* Machine state register bits definition */ 358 /* Machine state register bits definition */
359 #define MSR_SF 63 /* Sixty-four-bit mode hflags */ 359 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
  360 +#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
360 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ 361 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
361 #define MSR_SHV 60 /* hypervisor state hflags */ 362 #define MSR_SHV 60 /* hypervisor state hflags */
362 #define MSR_CM 31 /* Computation mode for BookE hflags */ 363 #define MSR_CM 31 /* Computation mode for BookE hflags */
@@ -1115,16 +1116,29 @@ static inline int cpu_mmu_index (CPUState *env) @@ -1115,16 +1116,29 @@ static inline int cpu_mmu_index (CPUState *env)
1115 #define SPR_440_CCR1 (0x378) 1116 #define SPR_440_CCR1 (0x378)
1116 #define SPR_DCRIPR (0x37B) 1117 #define SPR_DCRIPR (0x37B)
1117 #define SPR_PPR (0x380) 1118 #define SPR_PPR (0x380)
  1119 +#define SPR_750_GQR0 (0x390)
1118 #define SPR_440_DNV0 (0x390) 1120 #define SPR_440_DNV0 (0x390)
  1121 +#define SPR_750_GQR1 (0x391)
1119 #define SPR_440_DNV1 (0x391) 1122 #define SPR_440_DNV1 (0x391)
  1123 +#define SPR_750_GQR2 (0x392)
1120 #define SPR_440_DNV2 (0x392) 1124 #define SPR_440_DNV2 (0x392)
  1125 +#define SPR_750_GQR3 (0x393)
1121 #define SPR_440_DNV3 (0x393) 1126 #define SPR_440_DNV3 (0x393)
  1127 +#define SPR_750_GQR4 (0x394)
1122 #define SPR_440_DTV0 (0x394) 1128 #define SPR_440_DTV0 (0x394)
  1129 +#define SPR_750_GQR5 (0x395)
1123 #define SPR_440_DTV1 (0x395) 1130 #define SPR_440_DTV1 (0x395)
  1131 +#define SPR_750_GQR6 (0x396)
1124 #define SPR_440_DTV2 (0x396) 1132 #define SPR_440_DTV2 (0x396)
  1133 +#define SPR_750_GQR7 (0x397)
1125 #define SPR_440_DTV3 (0x397) 1134 #define SPR_440_DTV3 (0x397)
  1135 +#define SPR_750_THRM4 (0x398)
  1136 +#define SPR_750CL_HID2 (0x398)
1126 #define SPR_440_DVLIM (0x398) 1137 #define SPR_440_DVLIM (0x398)
  1138 +#define SPR_750_WPAR (0x399)
1127 #define SPR_440_IVLIM (0x399) 1139 #define SPR_440_IVLIM (0x399)
  1140 +#define SPR_750_DMAU (0x39A)
  1141 +#define SPR_750_DMAL (0x39B)
1128 #define SPR_440_RSTCFG (0x39B) 1142 #define SPR_440_RSTCFG (0x39B)
1129 #define SPR_BOOKE_DCDBTRL (0x39C) 1143 #define SPR_BOOKE_DCDBTRL (0x39C)
1130 #define SPR_BOOKE_DCDBTRH (0x39D) 1144 #define SPR_BOOKE_DCDBTRH (0x39D)
@@ -1231,9 +1245,11 @@ static inline int cpu_mmu_index (CPUState *env) @@ -1231,9 +1245,11 @@ static inline int cpu_mmu_index (CPUState *env)
1231 #define SPR_Exxx_L1CSR0 (0x3F2) 1245 #define SPR_Exxx_L1CSR0 (0x3F2)
1232 #define SPR_ICTRL (0x3F3) 1246 #define SPR_ICTRL (0x3F3)
1233 #define SPR_HID2 (0x3F3) 1247 #define SPR_HID2 (0x3F3)
  1248 +#define SPR_750CL_HID4 (0x3F3)
1234 #define SPR_Exxx_L1CSR1 (0x3F3) 1249 #define SPR_Exxx_L1CSR1 (0x3F3)
1235 #define SPR_440_DBDR (0x3F3) 1250 #define SPR_440_DBDR (0x3F3)
1236 #define SPR_LDSTDB (0x3F4) 1251 #define SPR_LDSTDB (0x3F4)
  1252 +#define SPR_750_TDCL (0x3F4)
1237 #define SPR_40x_IAC1 (0x3F4) 1253 #define SPR_40x_IAC1 (0x3F4)
1238 #define SPR_MMUCSR0 (0x3F4) 1254 #define SPR_MMUCSR0 (0x3F4)
1239 #define SPR_DABR (0x3F5) 1255 #define SPR_DABR (0x3F5)
@@ -1250,12 +1266,13 @@ static inline int cpu_mmu_index (CPUState *env) @@ -1250,12 +1266,13 @@ static inline int cpu_mmu_index (CPUState *env)
1250 #define SPR_MMUCFG (0x3F7) 1266 #define SPR_MMUCFG (0x3F7)
1251 #define SPR_LDSTCR (0x3F8) 1267 #define SPR_LDSTCR (0x3F8)
1252 #define SPR_L2PMCR (0x3F8) 1268 #define SPR_L2PMCR (0x3F8)
1253 -#define SPR_750_HID2 (0x3F8) 1269 +#define SPR_750FX_HID2 (0x3F8)
1254 #define SPR_620_BUSCSR (0x3F8) 1270 #define SPR_620_BUSCSR (0x3F8)
1255 #define SPR_Exxx_L1FINV0 (0x3F8) 1271 #define SPR_Exxx_L1FINV0 (0x3F8)
1256 #define SPR_L2CR (0x3F9) 1272 #define SPR_L2CR (0x3F9)
1257 #define SPR_620_L2CR (0x3F9) 1273 #define SPR_620_L2CR (0x3F9)
1258 #define SPR_L3CR (0x3FA) 1274 #define SPR_L3CR (0x3FA)
  1275 +#define SPR_750_TDCH (0x3FA)
1259 #define SPR_IABR2 (0x3FA) 1276 #define SPR_IABR2 (0x3FA)
1260 #define SPR_40x_DCCR (0x3FA) 1277 #define SPR_40x_DCCR (0x3FA)
1261 #define SPR_620_L2SR (0x3FA) 1278 #define SPR_620_L2SR (0x3FA)
target-ppc/translate_init.c
  View file @bd928eb
@@ -764,12 +764,6 @@ static void gen_spr_G2_755 (CPUPPCState *env) @@ -764,12 +764,6 @@ static void gen_spr_G2_755 (CPUPPCState *env)
764 SPR_NOACCESS, SPR_NOACCESS, 764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_generic, &spr_write_generic, 765 &spr_read_generic, &spr_write_generic,
766 0x00000000); 766 0x00000000);
767 - /* External access control */  
768 - /* XXX : not implemented */  
769 - spr_register(env, SPR_EAR, "EAR",  
770 - SPR_NOACCESS, SPR_NOACCESS,  
771 - &spr_read_generic, &spr_write_generic,  
772 - 0x00000000);  
773 } 767 }
774 768
775 /* SPR common to all 7xx PowerPC implementations */ 769 /* SPR common to all 7xx PowerPC implementations */
@@ -792,11 +786,6 @@ static void gen_spr_7xx (CPUPPCState *env) @@ -792,11 +786,6 @@ static void gen_spr_7xx (CPUPPCState *env)
792 SPR_NOACCESS, SPR_NOACCESS, 786 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_generic, &spr_write_generic, 787 &spr_read_generic, &spr_write_generic,
794 0x00000000); 788 0x00000000);
795 - /* XXX : not implemented */  
796 - spr_register(env, SPR_L2CR, "L2CR",  
797 - SPR_NOACCESS, SPR_NOACCESS,  
798 - &spr_read_generic, &spr_write_generic,  
799 - 0x00000000);  
800 /* Performance monitors */ 789 /* Performance monitors */
801 /* XXX : not implemented */ 790 /* XXX : not implemented */
802 spr_register(env, SPR_MMCR0, "MMCR0", 791 spr_register(env, SPR_MMCR0, "MMCR0",
@@ -1185,6 +1174,11 @@ static void gen_spr_74xx (CPUPPCState *env) @@ -1185,6 +1174,11 @@ static void gen_spr_74xx (CPUPPCState *env)
1185 &spr_read_generic, &spr_write_generic, 1174 &spr_read_generic, &spr_write_generic,
1186 &spr_read_generic, &spr_write_generic, 1175 &spr_read_generic, &spr_write_generic,
1187 0x00000000); 1176 0x00000000);
  1177 + /* XXX : not implemented */
  1178 + spr_register(env, SPR_L2CR, "L2CR",
  1179 + SPR_NOACCESS, SPR_NOACCESS,
  1180 + &spr_read_generic, &spr_write_generic,
  1181 + 0x00000000);
1188 } 1182 }
1189 1183
1190 static void gen_l3_ctrl (CPUPPCState *env) 1184 static void gen_l3_ctrl (CPUPPCState *env)
@@ -2871,6 +2865,7 @@ static void init_excp_7x0 (CPUPPCState *env) @@ -2871,6 +2865,7 @@ static void init_excp_7x0 (CPUPPCState *env)
2871 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2865 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2872 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2866 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2873 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2867 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
  2868 + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2874 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2869 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2875 env->excp_prefix = 0x00000000UL; 2870 env->excp_prefix = 0x00000000UL;
2876 /* Hardware reset vector */ 2871 /* Hardware reset vector */
@@ -2878,7 +2873,7 @@ static void init_excp_7x0 (CPUPPCState *env) @@ -2878,7 +2873,7 @@ static void init_excp_7x0 (CPUPPCState *env)
2878 #endif 2873 #endif
2879 } 2874 }
2880 2875
2881 -static void init_excp_750FX (CPUPPCState *env) 2876 +static void init_excp_750cl (CPUPPCState *env)
2882 { 2877 {
2883 #if !defined(CONFIG_USER_ONLY) 2878 #if !defined(CONFIG_USER_ONLY)
2884 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2879 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
@@ -2895,6 +2890,28 @@ static void init_excp_750FX (CPUPPCState *env) @@ -2895,6 +2890,28 @@ static void init_excp_750FX (CPUPPCState *env)
2895 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2890 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2896 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2891 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2897 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2892 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
  2893 + env->excp_prefix = 0x00000000UL;
  2894 + /* Hardware reset vector */
  2895 + env->hreset_vector = 0xFFFFFFFCUL;
  2896 +#endif
  2897 +}
  2898 +
  2899 +static void init_excp_750cx (CPUPPCState *env)
  2900 +{
  2901 +#if !defined(CONFIG_USER_ONLY)
  2902 + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
  2903 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
  2904 + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
  2905 + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
  2906 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
  2907 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
  2908 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
  2909 + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
  2910 + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
  2911 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
  2912 + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
  2913 + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
  2914 + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2898 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2915 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2899 env->excp_prefix = 0x00000000UL; 2916 env->excp_prefix = 0x00000000UL;
2900 /* Hardware reset vector */ 2917 /* Hardware reset vector */
@@ -2917,12 +2934,13 @@ static void init_excp_7x5 (CPUPPCState *env) @@ -2917,12 +2934,13 @@ static void init_excp_7x5 (CPUPPCState *env)
2917 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2934 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2918 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2935 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2919 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2936 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
  2937 + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2920 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2938 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2921 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2939 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2922 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2940 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2923 - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;  
2924 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2941 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2925 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2942 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
  2943 + env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2926 env->excp_prefix = 0x00000000UL; 2944 env->excp_prefix = 0x00000000UL;
2927 /* Hardware reset vector */ 2945 /* Hardware reset vector */
2928 env->hreset_vector = 0xFFFFFFFCUL; 2946 env->hreset_vector = 0xFFFFFFFCUL;
@@ -3196,10 +3214,6 @@ static void init_proc_403 (CPUPPCState *env) @@ -3196,10 +3214,6 @@ static void init_proc_403 (CPUPPCState *env)
3196 env->icache_line_size = 32; 3214 env->icache_line_size = 32;
3197 /* Allocate hardware IRQ controller */ 3215 /* Allocate hardware IRQ controller */
3198 ppc40x_irq_init(env); 3216 ppc40x_irq_init(env);
3199 -#if !defined(CONFIG_USER_ONLY)  
3200 - /* Hardware reset vector */  
3201 - env->hreset_vector = 0xFFFFFFFCUL;  
3202 -#endif  
3203 } 3217 }
3204 3218
3205 /* PowerPC 403 GCX */ 3219 /* PowerPC 403 GCX */
@@ -3834,6 +3848,12 @@ static void init_proc_G2 (CPUPPCState *env) @@ -3834,6 +3848,12 @@ static void init_proc_G2 (CPUPPCState *env)
3834 gen_spr_G2(env); 3848 gen_spr_G2(env);
3835 /* Time base */ 3849 /* Time base */
3836 gen_tbl(env); 3850 gen_tbl(env);
  3851 + /* External access control */
  3852 + /* XXX : not implemented */
  3853 + spr_register(env, SPR_EAR, "EAR",
  3854 + SPR_NOACCESS, SPR_NOACCESS,
  3855 + &spr_read_generic, &spr_write_generic,
  3856 + 0x00000000);
3837 /* Hardware implementation register */ 3857 /* Hardware implementation register */
3838 /* XXX : not implemented */ 3858 /* XXX : not implemented */
3839 spr_register(env, SPR_HID0, "HID0", 3859 spr_register(env, SPR_HID0, "HID0",
@@ -3885,6 +3905,12 @@ static void init_proc_G2LE (CPUPPCState *env) @@ -3885,6 +3905,12 @@ static void init_proc_G2LE (CPUPPCState *env)
3885 gen_spr_G2(env); 3905 gen_spr_G2(env);
3886 /* Time base */ 3906 /* Time base */
3887 gen_tbl(env); 3907 gen_tbl(env);
  3908 + /* External access control */
  3909 + /* XXX : not implemented */
  3910 + spr_register(env, SPR_EAR, "EAR",
  3911 + SPR_NOACCESS, SPR_NOACCESS,
  3912 + &spr_read_generic, &spr_write_generic,
  3913 + 0x00000000);
3888 /* Hardware implementation register */ 3914 /* Hardware implementation register */
3889 /* XXX : not implemented */ 3915 /* XXX : not implemented */
3890 spr_register(env, SPR_HID0, "HID0", 3916 spr_register(env, SPR_HID0, "HID0",
@@ -4529,25 +4555,24 @@ static void init_proc_604E (CPUPPCState *env) @@ -4529,25 +4555,24 @@ static void init_proc_604E (CPUPPCState *env)
4529 ppc6xx_irq_init(env); 4555 ppc6xx_irq_init(env);
4530 } 4556 }
4531 4557
4532 -/* PowerPC 740/750 (aka G3) */  
4533 -#define POWERPC_INSNS_7x0 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ 4558 +/* PowerPC 740 */
  4559 +#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4534 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ 4560 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4535 - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \  
4536 - PPC_FLOAT_STFIWX | \ 4561 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4537 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ 4562 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4538 PPC_MEM_SYNC | PPC_MEM_EIEIO | \ 4563 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4539 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ 4564 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4540 PPC_SEGMENT | PPC_EXTERN) 4565 PPC_SEGMENT | PPC_EXTERN)
4541 -#define POWERPC_MSRM_7x0 (0x000000000005FF77ULL)  
4542 -#define POWERPC_MMU_7x0 (POWERPC_MMU_32B)  
4543 -//#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)  
4544 -#define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)  
4545 -#define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)  
4546 -#define POWERPC_FLAG_7x0 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ 4566 +#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
  4567 +#define POWERPC_MMU_740 (POWERPC_MMU_32B)
  4568 +#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
  4569 +#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
  4570 +#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
  4571 +#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4547 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) 4572 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4548 -#define check_pow_7x0 check_pow_hid0 4573 +#define check_pow_740 check_pow_hid0
4549 4574
4550 -static void init_proc_7x0 (CPUPPCState *env) 4575 +static void init_proc_740 (CPUPPCState *env)
4551 { 4576 {
4552 gen_spr_ne_601(env); 4577 gen_spr_ne_601(env);
4553 gen_spr_7xx(env); 4578 gen_spr_7xx(env);
@@ -4575,11 +4600,296 @@ static void init_proc_7x0 (CPUPPCState *env) @@ -4575,11 +4600,296 @@ static void init_proc_7x0 (CPUPPCState *env)
4575 ppc6xx_irq_init(env); 4600 ppc6xx_irq_init(env);
4576 } 4601 }
4577 4602
4578 -/* PowerPC 750FX/GX */ 4603 +/* PowerPC 750 */
  4604 +#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4605 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4606 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
  4607 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4608 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4609 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  4610 + PPC_SEGMENT | PPC_EXTERN)
  4611 +#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
  4612 +#define POWERPC_MMU_750 (POWERPC_MMU_32B)
  4613 +#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
  4614 +#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
  4615 +#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
  4616 +#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
  4617 + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
  4618 +#define check_pow_750 check_pow_hid0
  4619 +
  4620 +static void init_proc_750 (CPUPPCState *env)
  4621 +{
  4622 + gen_spr_ne_601(env);
  4623 + gen_spr_7xx(env);
  4624 + /* XXX : not implemented */
  4625 + spr_register(env, SPR_L2CR, "L2CR",
  4626 + SPR_NOACCESS, SPR_NOACCESS,
  4627 + &spr_read_generic, &spr_write_generic,
  4628 + 0x00000000);
  4629 + /* Time base */
  4630 + gen_tbl(env);
  4631 + /* Thermal management */
  4632 + gen_spr_thrm(env);
  4633 + /* Hardware implementation registers */
  4634 + /* XXX : not implemented */
  4635 + spr_register(env, SPR_HID0, "HID0",
  4636 + SPR_NOACCESS, SPR_NOACCESS,
  4637 + &spr_read_generic, &spr_write_generic,
  4638 + 0x00000000);
  4639 + /* XXX : not implemented */
  4640 + spr_register(env, SPR_HID1, "HID1",
  4641 + SPR_NOACCESS, SPR_NOACCESS,
  4642 + &spr_read_generic, &spr_write_generic,
  4643 + 0x00000000);
  4644 + /* Memory management */
  4645 + gen_low_BATs(env);
  4646 + /* XXX: high BATs are also present but are known to be bugged on
  4647 + * die version 1.x
  4648 + */
  4649 + init_excp_7x0(env);
  4650 + env->dcache_line_size = 32;
  4651 + env->icache_line_size = 32;
  4652 + /* Allocate hardware IRQ controller */
  4653 + ppc6xx_irq_init(env);
  4654 +}
  4655 +
  4656 +/* PowerPC 750 CL */
  4657 +/* XXX: not implemented:
  4658 + * cache lock instructions:
  4659 + * dcbz_l
  4660 + * floating point paired instructions
  4661 + * psq_lux
  4662 + * psq_lx
  4663 + * psq_stux
  4664 + * psq_stx
  4665 + * ps_abs
  4666 + * ps_add
  4667 + * ps_cmpo0
  4668 + * ps_cmpo1
  4669 + * ps_cmpu0
  4670 + * ps_cmpu1
  4671 + * ps_div
  4672 + * ps_madd
  4673 + * ps_madds0
  4674 + * ps_madds1
  4675 + * ps_merge00
  4676 + * ps_merge01
  4677 + * ps_merge10
  4678 + * ps_merge11
  4679 + * ps_mr
  4680 + * ps_msub
  4681 + * ps_mul
  4682 + * ps_muls0
  4683 + * ps_muls1
  4684 + * ps_nabs
  4685 + * ps_neg
  4686 + * ps_nmadd
  4687 + * ps_nmsub
  4688 + * ps_res
  4689 + * ps_rsqrte
  4690 + * ps_sel
  4691 + * ps_sub
  4692 + * ps_sum0
  4693 + * ps_sum1
  4694 + */
  4695 +#define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4696 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4697 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
  4698 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4699 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4700 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  4701 + PPC_SEGMENT | PPC_EXTERN)
  4702 +#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
  4703 +#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
  4704 +#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
  4705 +#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
  4706 +#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
  4707 +#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
  4708 + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
  4709 +#define check_pow_750cl check_pow_hid0
  4710 +
  4711 +static void init_proc_750cl (CPUPPCState *env)
  4712 +{
  4713 + gen_spr_ne_601(env);
  4714 + gen_spr_7xx(env);
  4715 + /* XXX : not implemented */
  4716 + spr_register(env, SPR_L2CR, "L2CR",
  4717 + SPR_NOACCESS, SPR_NOACCESS,
  4718 + &spr_read_generic, &spr_write_generic,
  4719 + 0x00000000);
  4720 + /* Time base */
  4721 + gen_tbl(env);
  4722 + /* Thermal management */
  4723 + /* Those registers are fake on 750CL */
  4724 + spr_register(env, SPR_THRM1, "THRM1",
  4725 + SPR_NOACCESS, SPR_NOACCESS,
  4726 + &spr_read_generic, &spr_write_generic,
  4727 + 0x00000000);
  4728 + spr_register(env, SPR_THRM2, "THRM2",
  4729 + SPR_NOACCESS, SPR_NOACCESS,
  4730 + &spr_read_generic, &spr_write_generic,
  4731 + 0x00000000);
  4732 + spr_register(env, SPR_THRM3, "THRM3",
  4733 + SPR_NOACCESS, SPR_NOACCESS,
  4734 + &spr_read_generic, &spr_write_generic,
  4735 + 0x00000000);
  4736 + /* XXX: not implemented */
  4737 + spr_register(env, SPR_750_TDCL, "TDCL",
  4738 + SPR_NOACCESS, SPR_NOACCESS,
  4739 + &spr_read_generic, &spr_write_generic,
  4740 + 0x00000000);
  4741 + spr_register(env, SPR_750_TDCH, "TDCH",
  4742 + SPR_NOACCESS, SPR_NOACCESS,
  4743 + &spr_read_generic, &spr_write_generic,
  4744 + 0x00000000);
  4745 + /* DMA */
  4746 + /* XXX : not implemented */
  4747 + spr_register(env, SPR_750_WPAR, "WPAR",
  4748 + SPR_NOACCESS, SPR_NOACCESS,
  4749 + &spr_read_generic, &spr_write_generic,
  4750 + 0x00000000);
  4751 + spr_register(env, SPR_750_DMAL, "DMAL",
  4752 + SPR_NOACCESS, SPR_NOACCESS,
  4753 + &spr_read_generic, &spr_write_generic,
  4754 + 0x00000000);
  4755 + spr_register(env, SPR_750_DMAU, "DMAU",
  4756 + SPR_NOACCESS, SPR_NOACCESS,
  4757 + &spr_read_generic, &spr_write_generic,
  4758 + 0x00000000);
  4759 + /* Hardware implementation registers */
  4760 + /* XXX : not implemented */
  4761 + spr_register(env, SPR_HID0, "HID0",
  4762 + SPR_NOACCESS, SPR_NOACCESS,
  4763 + &spr_read_generic, &spr_write_generic,
  4764 + 0x00000000);
  4765 + /* XXX : not implemented */
  4766 + spr_register(env, SPR_HID1, "HID1",
  4767 + SPR_NOACCESS, SPR_NOACCESS,
  4768 + &spr_read_generic, &spr_write_generic,
  4769 + 0x00000000);
  4770 + /* XXX : not implemented */
  4771 + spr_register(env, SPR_750CL_HID2, "HID2",
  4772 + SPR_NOACCESS, SPR_NOACCESS,
  4773 + &spr_read_generic, &spr_write_generic,
  4774 + 0x00000000);
  4775 + /* XXX : not implemented */
  4776 + spr_register(env, SPR_750CL_HID4, "HID4",
  4777 + SPR_NOACCESS, SPR_NOACCESS,
  4778 + &spr_read_generic, &spr_write_generic,
  4779 + 0x00000000);
  4780 + /* Quantization registers */
  4781 + /* XXX : not implemented */
  4782 + spr_register(env, SPR_750_GQR0, "GQR0",
  4783 + SPR_NOACCESS, SPR_NOACCESS,
  4784 + &spr_read_generic, &spr_write_generic,
  4785 + 0x00000000);
  4786 + /* XXX : not implemented */
  4787 + spr_register(env, SPR_750_GQR1, "GQR1",
  4788 + SPR_NOACCESS, SPR_NOACCESS,
  4789 + &spr_read_generic, &spr_write_generic,
  4790 + 0x00000000);
  4791 + /* XXX : not implemented */
  4792 + spr_register(env, SPR_750_GQR2, "GQR2",
  4793 + SPR_NOACCESS, SPR_NOACCESS,
  4794 + &spr_read_generic, &spr_write_generic,
  4795 + 0x00000000);
  4796 + /* XXX : not implemented */
  4797 + spr_register(env, SPR_750_GQR3, "GQR3",
  4798 + SPR_NOACCESS, SPR_NOACCESS,
  4799 + &spr_read_generic, &spr_write_generic,
  4800 + 0x00000000);
  4801 + /* XXX : not implemented */
  4802 + spr_register(env, SPR_750_GQR4, "GQR4",
  4803 + SPR_NOACCESS, SPR_NOACCESS,
  4804 + &spr_read_generic, &spr_write_generic,
  4805 + 0x00000000);
  4806 + /* XXX : not implemented */
  4807 + spr_register(env, SPR_750_GQR5, "GQR5",
  4808 + SPR_NOACCESS, SPR_NOACCESS,
  4809 + &spr_read_generic, &spr_write_generic,
  4810 + 0x00000000);
  4811 + /* XXX : not implemented */
  4812 + spr_register(env, SPR_750_GQR6, "GQR6",
  4813 + SPR_NOACCESS, SPR_NOACCESS,
  4814 + &spr_read_generic, &spr_write_generic,
  4815 + 0x00000000);
  4816 + /* XXX : not implemented */
  4817 + spr_register(env, SPR_750_GQR7, "GQR7",
  4818 + SPR_NOACCESS, SPR_NOACCESS,
  4819 + &spr_read_generic, &spr_write_generic,
  4820 + 0x00000000);
  4821 + /* Memory management */
  4822 + gen_low_BATs(env);
  4823 + /* PowerPC 750cl has 8 DBATs and 8 IBATs */
  4824 + gen_high_BATs(env);
  4825 + init_excp_750cl(env);
  4826 + env->dcache_line_size = 32;
  4827 + env->icache_line_size = 32;
  4828 + /* Allocate hardware IRQ controller */
  4829 + ppc6xx_irq_init(env);
  4830 +}
  4831 +
  4832 +#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  4833 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  4834 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
  4835 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4836 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4837 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  4838 + PPC_SEGMENT | PPC_EXTERN)
  4839 +#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
  4840 +#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
  4841 +#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
  4842 +#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
  4843 +#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
  4844 +#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
  4845 + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
  4846 +#define check_pow_750cx check_pow_hid0
  4847 +
  4848 +static void init_proc_750cx (CPUPPCState *env)
  4849 +{
  4850 + gen_spr_ne_601(env);
  4851 + gen_spr_7xx(env);
  4852 + /* XXX : not implemented */
  4853 + spr_register(env, SPR_L2CR, "L2CR",
  4854 + SPR_NOACCESS, SPR_NOACCESS,
  4855 + &spr_read_generic, &spr_write_generic,
  4856 + 0x00000000);
  4857 + /* Time base */
  4858 + gen_tbl(env);
  4859 + /* Thermal management */
  4860 + gen_spr_thrm(env);
  4861 + /* This register is not implemented but is present for compatibility */
  4862 + spr_register(env, SPR_SDA, "SDA",
  4863 + SPR_NOACCESS, SPR_NOACCESS,
  4864 + &spr_read_generic, &spr_write_generic,
  4865 + 0x00000000);
  4866 + /* Hardware implementation registers */
  4867 + /* XXX : not implemented */
  4868 + spr_register(env, SPR_HID0, "HID0",
  4869 + SPR_NOACCESS, SPR_NOACCESS,
  4870 + &spr_read_generic, &spr_write_generic,
  4871 + 0x00000000);
  4872 + /* XXX : not implemented */
  4873 + spr_register(env, SPR_HID1, "HID1",
  4874 + SPR_NOACCESS, SPR_NOACCESS,
  4875 + &spr_read_generic, &spr_write_generic,
  4876 + 0x00000000);
  4877 + /* Memory management */
  4878 + gen_low_BATs(env);
  4879 + /* XXX: high BATs are also present but are known to be bugged on
  4880 + * die version 1.x
  4881 + */
  4882 + init_excp_750cx(env);
  4883 + env->dcache_line_size = 32;
  4884 + env->icache_line_size = 32;
  4885 + /* Allocate hardware IRQ controller */
  4886 + ppc6xx_irq_init(env);
  4887 +}
  4888 +
  4889 +/* PowerPC 750FX */
4579 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ 4890 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4580 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ 4891 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4581 - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \  
4582 - PPC_FLOAT_STFIWX | \ 4892 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4583 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ 4893 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4584 PPC_MEM_SYNC | PPC_MEM_EIEIO | \ 4894 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4585 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ 4895 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
@@ -4597,10 +4907,20 @@ static void init_proc_750fx (CPUPPCState *env) @@ -4597,10 +4907,20 @@ static void init_proc_750fx (CPUPPCState *env)
4597 { 4907 {
4598 gen_spr_ne_601(env); 4908 gen_spr_ne_601(env);
4599 gen_spr_7xx(env); 4909 gen_spr_7xx(env);
  4910 + /* XXX : not implemented */
  4911 + spr_register(env, SPR_L2CR, "L2CR",
  4912 + SPR_NOACCESS, SPR_NOACCESS,
  4913 + &spr_read_generic, &spr_write_generic,
  4914 + 0x00000000);
4600 /* Time base */ 4915 /* Time base */
4601 gen_tbl(env); 4916 gen_tbl(env);
4602 /* Thermal management */ 4917 /* Thermal management */
4603 gen_spr_thrm(env); 4918 gen_spr_thrm(env);
  4919 + /* XXX : not implemented */
  4920 + spr_register(env, SPR_750_THRM4, "THRM4",
  4921 + SPR_NOACCESS, SPR_NOACCESS,
  4922 + &spr_read_generic, &spr_write_generic,
  4923 + 0x00000000);
4604 /* Hardware implementation registers */ 4924 /* Hardware implementation registers */
4605 /* XXX : not implemented */ 4925 /* XXX : not implemented */
4606 spr_register(env, SPR_HID0, "HID0", 4926 spr_register(env, SPR_HID0, "HID0",
@@ -4613,7 +4933,7 @@ static void init_proc_750fx (CPUPPCState *env) @@ -4613,7 +4933,7 @@ static void init_proc_750fx (CPUPPCState *env)
4613 &spr_read_generic, &spr_write_generic, 4933 &spr_read_generic, &spr_write_generic,
4614 0x00000000); 4934 0x00000000);
4615 /* XXX : not implemented */ 4935 /* XXX : not implemented */
4616 - spr_register(env, SPR_750_HID2, "HID2", 4936 + spr_register(env, SPR_750FX_HID2, "HID2",
4617 SPR_NOACCESS, SPR_NOACCESS, 4937 SPR_NOACCESS, SPR_NOACCESS,
4618 &spr_read_generic, &spr_write_generic, 4938 &spr_read_generic, &spr_write_generic,
4619 0x00000000); 4939 0x00000000);
@@ -4621,40 +4941,155 @@ static void init_proc_750fx (CPUPPCState *env) @@ -4621,40 +4941,155 @@ static void init_proc_750fx (CPUPPCState *env)
4621 gen_low_BATs(env); 4941 gen_low_BATs(env);
4622 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4942 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4623 gen_high_BATs(env); 4943 gen_high_BATs(env);
4624 - init_excp_750FX(env); 4944 + init_excp_7x0(env);
4625 env->dcache_line_size = 32; 4945 env->dcache_line_size = 32;
4626 env->icache_line_size = 32; 4946 env->icache_line_size = 32;
4627 /* Allocate hardware IRQ controller */ 4947 /* Allocate hardware IRQ controller */
4628 ppc6xx_irq_init(env); 4948 ppc6xx_irq_init(env);
4629 } 4949 }
4630 4950
4631 -/* PowerPC 745/755 */  
4632 -#define POWERPC_INSNS_7x5 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ 4951 +/* PowerPC 750GX */
  4952 +#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4633 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ 4953 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4634 - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \  
4635 - PPC_FLOAT_STFIWX | \ 4954 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
  4955 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  4956 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  4957 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  4958 + PPC_SEGMENT | PPC_EXTERN)
  4959 +#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
  4960 +#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
  4961 +#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
  4962 +#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
  4963 +#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
  4964 +#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
  4965 + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
  4966 +#define check_pow_750gx check_pow_hid0
  4967 +
  4968 +static void init_proc_750gx (CPUPPCState *env)
  4969 +{
  4970 + gen_spr_ne_601(env);
  4971 + gen_spr_7xx(env);
  4972 + /* XXX : not implemented (XXX: different from 750fx) */
  4973 + spr_register(env, SPR_L2CR, "L2CR",
  4974 + SPR_NOACCESS, SPR_NOACCESS,
  4975 + &spr_read_generic, &spr_write_generic,
  4976 + 0x00000000);
  4977 + /* Time base */
  4978 + gen_tbl(env);
  4979 + /* Thermal management */
  4980 + gen_spr_thrm(env);
  4981 + /* XXX : not implemented */
  4982 + spr_register(env, SPR_750_THRM4, "THRM4",
  4983 + SPR_NOACCESS, SPR_NOACCESS,
  4984 + &spr_read_generic, &spr_write_generic,
  4985 + 0x00000000);
  4986 + /* Hardware implementation registers */
  4987 + /* XXX : not implemented (XXX: different from 750fx) */
  4988 + spr_register(env, SPR_HID0, "HID0",
  4989 + SPR_NOACCESS, SPR_NOACCESS,
  4990 + &spr_read_generic, &spr_write_generic,
  4991 + 0x00000000);
  4992 + /* XXX : not implemented */
  4993 + spr_register(env, SPR_HID1, "HID1",
  4994 + SPR_NOACCESS, SPR_NOACCESS,
  4995 + &spr_read_generic, &spr_write_generic,
  4996 + 0x00000000);
  4997 + /* XXX : not implemented (XXX: different from 750fx) */
  4998 + spr_register(env, SPR_750FX_HID2, "HID2",
  4999 + SPR_NOACCESS, SPR_NOACCESS,
  5000 + &spr_read_generic, &spr_write_generic,
  5001 + 0x00000000);
  5002 + /* Memory management */
  5003 + gen_low_BATs(env);
  5004 + /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
  5005 + gen_high_BATs(env);
  5006 + init_excp_7x0(env);
  5007 + env->dcache_line_size = 32;
  5008 + env->icache_line_size = 32;
  5009 + /* Allocate hardware IRQ controller */
  5010 + ppc6xx_irq_init(env);
  5011 +}
  5012 +
  5013 +/* PowerPC 745 */
  5014 +#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  5015 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  5016 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
  5017 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
  5018 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  5019 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
  5020 + PPC_SEGMENT | PPC_EXTERN)
  5021 +#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
  5022 +#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
  5023 +#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
  5024 +#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
  5025 +#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
  5026 +#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
  5027 + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
  5028 +#define check_pow_745 check_pow_hid0
  5029 +
  5030 +static void init_proc_745 (CPUPPCState *env)
  5031 +{
  5032 + gen_spr_ne_601(env);
  5033 + gen_spr_7xx(env);
  5034 + gen_spr_G2_755(env);
  5035 + /* Time base */
  5036 + gen_tbl(env);
  5037 + /* Thermal management */
  5038 + gen_spr_thrm(env);
  5039 + /* Hardware implementation registers */
  5040 + /* XXX : not implemented */
  5041 + spr_register(env, SPR_HID0, "HID0",
  5042 + SPR_NOACCESS, SPR_NOACCESS,
  5043 + &spr_read_generic, &spr_write_generic,
  5044 + 0x00000000);
  5045 + /* XXX : not implemented */
  5046 + spr_register(env, SPR_HID1, "HID1",
  5047 + SPR_NOACCESS, SPR_NOACCESS,
  5048 + &spr_read_generic, &spr_write_generic,
  5049 + 0x00000000);
  5050 + /* XXX : not implemented */
  5051 + spr_register(env, SPR_HID2, "HID2",
  5052 + SPR_NOACCESS, SPR_NOACCESS,
  5053 + &spr_read_generic, &spr_write_generic,
  5054 + 0x00000000);
  5055 + /* Memory management */
  5056 + gen_low_BATs(env);
  5057 + gen_high_BATs(env);
  5058 + gen_6xx_7xx_soft_tlb(env, 64, 2);
  5059 + init_excp_7x5(env);
  5060 + env->dcache_line_size = 32;
  5061 + env->icache_line_size = 32;
  5062 + /* Allocate hardware IRQ controller */
  5063 + ppc6xx_irq_init(env);
  5064 +}
  5065 +
  5066 +/* PowerPC 755 */
  5067 +#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  5068 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  5069 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4636 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ 5070 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4637 PPC_MEM_SYNC | PPC_MEM_EIEIO | \ 5071 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4638 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ 5072 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4639 PPC_SEGMENT | PPC_EXTERN) 5073 PPC_SEGMENT | PPC_EXTERN)
4640 -#define POWERPC_MSRM_7x5 (0x000000000005FF77ULL)  
4641 -#define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)  
4642 -//#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)  
4643 -#define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)  
4644 -#define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)  
4645 -#define POWERPC_FLAG_7x5 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ 5074 +#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
  5075 +#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
  5076 +#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
  5077 +#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
  5078 +#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
  5079 +#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4646 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) 5080 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4647 -#define check_pow_7x5 check_pow_hid0 5081 +#define check_pow_755 check_pow_hid0
4648 5082
4649 -static void init_proc_7x5 (CPUPPCState *env) 5083 +static void init_proc_755 (CPUPPCState *env)
4650 { 5084 {
4651 gen_spr_ne_601(env); 5085 gen_spr_ne_601(env);
  5086 + gen_spr_7xx(env);
4652 gen_spr_G2_755(env); 5087 gen_spr_G2_755(env);
4653 /* Time base */ 5088 /* Time base */
4654 gen_tbl(env); 5089 gen_tbl(env);
4655 /* L2 cache control */ 5090 /* L2 cache control */
4656 /* XXX : not implemented */ 5091 /* XXX : not implemented */
4657 - spr_register(env, SPR_ICTC, "ICTC", 5092 + spr_register(env, SPR_L2CR, "L2CR",
4658 SPR_NOACCESS, SPR_NOACCESS, 5093 SPR_NOACCESS, SPR_NOACCESS,
4659 &spr_read_generic, &spr_write_generic, 5094 &spr_read_generic, &spr_write_generic,
4660 0x00000000); 5095 0x00000000);
@@ -4663,6 +5098,8 @@ static void init_proc_7x5 (CPUPPCState *env) @@ -4663,6 +5098,8 @@ static void init_proc_7x5 (CPUPPCState *env)
4663 SPR_NOACCESS, SPR_NOACCESS, 5098 SPR_NOACCESS, SPR_NOACCESS,
4664 &spr_read_generic, &spr_write_generic, 5099 &spr_read_generic, &spr_write_generic,
4665 0x00000000); 5100 0x00000000);
  5101 + /* Thermal management */
  5102 + gen_spr_thrm(env);
4666 /* Hardware implementation registers */ 5103 /* Hardware implementation registers */
4667 /* XXX : not implemented */ 5104 /* XXX : not implemented */
4668 spr_register(env, SPR_HID0, "HID0", 5105 spr_register(env, SPR_HID0, "HID0",
@@ -4688,10 +5125,6 @@ static void init_proc_7x5 (CPUPPCState *env) @@ -4688,10 +5125,6 @@ static void init_proc_7x5 (CPUPPCState *env)
4688 env->icache_line_size = 32; 5125 env->icache_line_size = 32;
4689 /* Allocate hardware IRQ controller */ 5126 /* Allocate hardware IRQ controller */
4690 ppc6xx_irq_init(env); 5127 ppc6xx_irq_init(env);
4691 -#if !defined(CONFIG_USER_ONLY)  
4692 - /* Hardware reset vector */  
4693 - env->hreset_vector = 0xFFFFFFFCUL;  
4694 -#endif  
4695 } 5128 }
4696 5129
4697 /* PowerPC 7400 (aka G4) */ 5130 /* PowerPC 7400 (aka G4) */
@@ -5232,7 +5665,7 @@ static void init_proc_970 (CPUPPCState *env) @@ -5232,7 +5665,7 @@ static void init_proc_970 (CPUPPCState *env)
5232 &spr_read_generic, &spr_write_generic, 5665 &spr_read_generic, &spr_write_generic,
5233 0x00000000); 5666 0x00000000);
5234 /* XXX : not implemented */ 5667 /* XXX : not implemented */
5235 - spr_register(env, SPR_750_HID2, "HID2", 5668 + spr_register(env, SPR_750FX_HID2, "HID2",
5236 SPR_NOACCESS, SPR_NOACCESS, 5669 SPR_NOACCESS, SPR_NOACCESS,
5237 &spr_read_generic, &spr_write_generic, 5670 &spr_read_generic, &spr_write_generic,
5238 0x00000000); 5671 0x00000000);
@@ -5241,6 +5674,11 @@ static void init_proc_970 (CPUPPCState *env) @@ -5241,6 +5674,11 @@ static void init_proc_970 (CPUPPCState *env)
5241 SPR_NOACCESS, SPR_NOACCESS, 5674 SPR_NOACCESS, SPR_NOACCESS,
5242 &spr_read_generic, &spr_write_generic, 5675 &spr_read_generic, &spr_write_generic,
5243 POWERPC970_HID5_INIT); 5676 POWERPC970_HID5_INIT);
  5677 + /* XXX : not implemented */
  5678 + spr_register(env, SPR_L2CR, "L2CR",
  5679 + SPR_NOACCESS, SPR_NOACCESS,
  5680 + &spr_read_generic, &spr_write_generic,
  5681 + 0x00000000);
5244 /* Memory management */ 5682 /* Memory management */
5245 /* XXX: not correct */ 5683 /* XXX: not correct */
5246 gen_low_BATs(env); 5684 gen_low_BATs(env);
@@ -5313,7 +5751,7 @@ static void init_proc_970FX (CPUPPCState *env) @@ -5313,7 +5751,7 @@ static void init_proc_970FX (CPUPPCState *env)
5313 &spr_read_generic, &spr_write_generic, 5751 &spr_read_generic, &spr_write_generic,
5314 0x00000000); 5752 0x00000000);
5315 /* XXX : not implemented */ 5753 /* XXX : not implemented */
5316 - spr_register(env, SPR_750_HID2, "HID2", 5754 + spr_register(env, SPR_750FX_HID2, "HID2",
5317 SPR_NOACCESS, SPR_NOACCESS, 5755 SPR_NOACCESS, SPR_NOACCESS,
5318 &spr_read_generic, &spr_write_generic, 5756 &spr_read_generic, &spr_write_generic,
5319 0x00000000); 5757 0x00000000);
@@ -5322,6 +5760,11 @@ static void init_proc_970FX (CPUPPCState *env) @@ -5322,6 +5760,11 @@ static void init_proc_970FX (CPUPPCState *env)
5322 SPR_NOACCESS, SPR_NOACCESS, 5760 SPR_NOACCESS, SPR_NOACCESS,
5323 &spr_read_generic, &spr_write_generic, 5761 &spr_read_generic, &spr_write_generic,
5324 POWERPC970_HID5_INIT); 5762 POWERPC970_HID5_INIT);
  5763 + /* XXX : not implemented */
  5764 + spr_register(env, SPR_L2CR, "L2CR",
  5765 + SPR_NOACCESS, SPR_NOACCESS,
  5766 + &spr_read_generic, &spr_write_generic,
  5767 + 0x00000000);
5325 /* Memory management */ 5768 /* Memory management */
5326 /* XXX: not correct */ 5769 /* XXX: not correct */
5327 gen_low_BATs(env); 5770 gen_low_BATs(env);
@@ -5394,7 +5837,7 @@ static void init_proc_970GX (CPUPPCState *env) @@ -5394,7 +5837,7 @@ static void init_proc_970GX (CPUPPCState *env)
5394 &spr_read_generic, &spr_write_generic, 5837 &spr_read_generic, &spr_write_generic,
5395 0x00000000); 5838 0x00000000);
5396 /* XXX : not implemented */ 5839 /* XXX : not implemented */
5397 - spr_register(env, SPR_750_HID2, "HID2", 5840 + spr_register(env, SPR_750FX_HID2, "HID2",
5398 SPR_NOACCESS, SPR_NOACCESS, 5841 SPR_NOACCESS, SPR_NOACCESS,
5399 &spr_read_generic, &spr_write_generic, 5842 &spr_read_generic, &spr_write_generic,
5400 0x00000000); 5843 0x00000000);
@@ -5403,6 +5846,11 @@ static void init_proc_970GX (CPUPPCState *env) @@ -5403,6 +5846,11 @@ static void init_proc_970GX (CPUPPCState *env)
5403 SPR_NOACCESS, SPR_NOACCESS, 5846 SPR_NOACCESS, SPR_NOACCESS,
5404 &spr_read_generic, &spr_write_generic, 5847 &spr_read_generic, &spr_write_generic,
5405 POWERPC970_HID5_INIT); 5848 POWERPC970_HID5_INIT);
  5849 + /* XXX : not implemented */
  5850 + spr_register(env, SPR_L2CR, "L2CR",
  5851 + SPR_NOACCESS, SPR_NOACCESS,
  5852 + &spr_read_generic, &spr_write_generic,
  5853 + 0x00000000);
5406 /* Memory management */ 5854 /* Memory management */
5407 /* XXX: not correct */ 5855 /* XXX: not correct */
5408 gen_low_BATs(env); 5856 gen_low_BATs(env);
@@ -5475,7 +5923,7 @@ static void init_proc_970MP (CPUPPCState *env) @@ -5475,7 +5923,7 @@ static void init_proc_970MP (CPUPPCState *env)
5475 &spr_read_generic, &spr_write_generic, 5923 &spr_read_generic, &spr_write_generic,
5476 0x00000000); 5924 0x00000000);
5477 /* XXX : not implemented */ 5925 /* XXX : not implemented */
5478 - spr_register(env, SPR_750_HID2, "HID2", 5926 + spr_register(env, SPR_750FX_HID2, "HID2",
5479 SPR_NOACCESS, SPR_NOACCESS, 5927 SPR_NOACCESS, SPR_NOACCESS,
5480 &spr_read_generic, &spr_write_generic, 5928 &spr_read_generic, &spr_write_generic,
5481 0x00000000); 5929 0x00000000);
@@ -5484,6 +5932,11 @@ static void init_proc_970MP (CPUPPCState *env) @@ -5484,6 +5932,11 @@ static void init_proc_970MP (CPUPPCState *env)
5484 SPR_NOACCESS, SPR_NOACCESS, 5932 SPR_NOACCESS, SPR_NOACCESS,
5485 &spr_read_generic, &spr_write_generic, 5933 &spr_read_generic, &spr_write_generic,
5486 POWERPC970_HID5_INIT); 5934 POWERPC970_HID5_INIT);
  5935 + /* XXX : not implemented */
  5936 + spr_register(env, SPR_L2CR, "L2CR",
  5937 + SPR_NOACCESS, SPR_NOACCESS,
  5938 + &spr_read_generic, &spr_write_generic,
  5939 + 0x00000000);
5487 /* Memory management */ 5940 /* Memory management */
5488 /* XXX: not correct */ 5941 /* XXX: not correct */
5489 gen_low_BATs(env); 5942 gen_low_BATs(env);
@@ -6092,6 +6545,7 @@ enum { @@ -6092,6 +6545,7 @@ enum {
6092 #define CPU_POWERPC_601 CPU_POWERPC_601_v2 6545 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
6093 CPU_POWERPC_601_v0 = 0x00010001, 6546 CPU_POWERPC_601_v0 = 0x00010001,
6094 CPU_POWERPC_601_v1 = 0x00010001, 6547 CPU_POWERPC_601_v1 = 0x00010001,
  6548 +#define CPU_POWERPC_601v CPU_POWERPC_601_v2
6095 CPU_POWERPC_601_v2 = 0x00010002, 6549 CPU_POWERPC_601_v2 = 0x00010002,
6096 CPU_POWERPC_602 = 0x00050100, 6550 CPU_POWERPC_602 = 0x00050100,
6097 CPU_POWERPC_603 = 0x00030100, 6551 CPU_POWERPC_603 = 0x00030100,
@@ -6129,16 +6583,22 @@ enum { @@ -6129,16 +6583,22 @@ enum {
6129 /* PowerPC 740/750 cores (aka G3) */ 6583 /* PowerPC 740/750 cores (aka G3) */
6130 /* XXX: missing 0x00084202 */ 6584 /* XXX: missing 0x00084202 */
6131 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31 6585 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
  6586 + CPU_POWERPC_7x0_v10 = 0x00080100,
6132 CPU_POWERPC_7x0_v20 = 0x00080200, 6587 CPU_POWERPC_7x0_v20 = 0x00080200,
6133 CPU_POWERPC_7x0_v21 = 0x00080201, 6588 CPU_POWERPC_7x0_v21 = 0x00080201,
6134 CPU_POWERPC_7x0_v22 = 0x00080202, 6589 CPU_POWERPC_7x0_v22 = 0x00080202,
6135 CPU_POWERPC_7x0_v30 = 0x00080300, 6590 CPU_POWERPC_7x0_v30 = 0x00080300,
6136 CPU_POWERPC_7x0_v31 = 0x00080301, 6591 CPU_POWERPC_7x0_v31 = 0x00080301,
6137 CPU_POWERPC_740E = 0x00080100, 6592 CPU_POWERPC_740E = 0x00080100,
  6593 + CPU_POWERPC_750E = 0x00080200,
6138 CPU_POWERPC_7x0P = 0x10080000, 6594 CPU_POWERPC_7x0P = 0x10080000,
6139 /* XXX: missing 0x00087010 (CL ?) */ 6595 /* XXX: missing 0x00087010 (CL ?) */
6140 - CPU_POWERPC_750CL = 0x00087200, 6596 +#define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
  6597 + CPU_POWERPC_750CL_v10 = 0x00087200,
  6598 + CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
6141 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22 6599 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
  6600 + CPU_POWERPC_750CX_v10 = 0x00082100,
  6601 + CPU_POWERPC_750CX_v20 = 0x00082200,
6142 CPU_POWERPC_750CX_v21 = 0x00082201, 6602 CPU_POWERPC_750CX_v21 = 0x00082201,
6143 CPU_POWERPC_750CX_v22 = 0x00082202, 6603 CPU_POWERPC_750CX_v22 = 0x00082202,
6144 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b 6604 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
@@ -6147,11 +6607,11 @@ enum { @@ -6147,11 +6607,11 @@ enum {
6147 CPU_POWERPC_750CXE_v23 = 0x00082213, 6607 CPU_POWERPC_750CXE_v23 = 0x00082213,
6148 CPU_POWERPC_750CXE_v24 = 0x00082214, 6608 CPU_POWERPC_750CXE_v24 = 0x00082214,
6149 CPU_POWERPC_750CXE_v24b = 0x00083214, 6609 CPU_POWERPC_750CXE_v24b = 0x00083214,
6150 - CPU_POWERPC_750CXE_v31 = 0x00083211, 6610 + CPU_POWERPC_750CXE_v30 = 0x00082310,
  6611 + CPU_POWERPC_750CXE_v31 = 0x00082311,
6151 CPU_POWERPC_750CXE_v31b = 0x00083311, 6612 CPU_POWERPC_750CXE_v31b = 0x00083311,
6152 CPU_POWERPC_750CXR = 0x00083410, 6613 CPU_POWERPC_750CXR = 0x00083410,
6153 - CPU_POWERPC_750E = 0x00080200,  
6154 - CPU_POWERPC_750FL = 0x700A0203, 6614 + CPU_POWERPC_750FL = 0x70000203,
6155 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23 6615 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
6156 CPU_POWERPC_750FX_v10 = 0x70000100, 6616 CPU_POWERPC_750FX_v10 = 0x70000100,
6157 CPU_POWERPC_750FX_v20 = 0x70000200, 6617 CPU_POWERPC_750FX_v20 = 0x70000200,
@@ -6164,6 +6624,8 @@ enum { @@ -6164,6 +6624,8 @@ enum {
6164 CPU_POWERPC_750GX_v11 = 0x70020101, 6624 CPU_POWERPC_750GX_v11 = 0x70020101,
6165 CPU_POWERPC_750GX_v12 = 0x70020102, 6625 CPU_POWERPC_750GX_v12 = 0x70020102,
6166 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */ 6626 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
  6627 + CPU_POWERPC_750L_v20 = 0x00088200,
  6628 + CPU_POWERPC_750L_v21 = 0x00088201,
6167 CPU_POWERPC_750L_v22 = 0x00088202, 6629 CPU_POWERPC_750L_v22 = 0x00088202,
6168 CPU_POWERPC_750L_v30 = 0x00088300, 6630 CPU_POWERPC_750L_v30 = 0x00088300,
6169 CPU_POWERPC_750L_v32 = 0x00088302, 6631 CPU_POWERPC_750L_v32 = 0x00088302,
@@ -7577,13 +8039,13 @@ static const ppc_def_t ppc_defs[] = { @@ -7577,13 +8039,13 @@ static const ppc_def_t ppc_defs[] = {
7577 /* 32 bits "classic" PowerPC */ 8039 /* 32 bits "classic" PowerPC */
7578 /* PowerPC 6xx family */ 8040 /* PowerPC 6xx family */
7579 /* PowerPC 601 */ 8041 /* PowerPC 601 */
7580 - POWERPC_DEF("601", CPU_POWERPC_601, 601), 8042 + POWERPC_DEF("601", CPU_POWERPC_601, 601v),
7581 /* PowerPC 601v0 */ 8043 /* PowerPC 601v0 */
7582 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601), 8044 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
7583 /* PowerPC 601v1 */ 8045 /* PowerPC 601v1 */
7584 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601), 8046 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
7585 /* PowerPC 601v */ 8047 /* PowerPC 601v */
7586 - POWERPC_DEF("601v", CPU_POWERPC_601, 601v), 8048 + POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
7587 /* PowerPC 601v2 */ 8049 /* PowerPC 601v2 */
7588 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v), 8050 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
7589 /* PowerPC 602 */ 8051 /* PowerPC 602 */
@@ -7652,71 +8114,85 @@ static const ppc_def_t ppc_defs[] = { @@ -7652,71 +8114,85 @@ static const ppc_def_t ppc_defs[] = {
7652 #endif 8114 #endif
7653 /* PowerPC 7xx family */ 8115 /* PowerPC 7xx family */
7654 /* Generic PowerPC 740 (G3) */ 8116 /* Generic PowerPC 740 (G3) */
7655 - POWERPC_DEF("740", CPU_POWERPC_7x0, 7x0), 8117 + POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
7656 /* Code name for PowerPC 740 */ 8118 /* Code name for PowerPC 740 */
7657 - POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 7x0), 8119 + POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
7658 /* Generic PowerPC 750 (G3) */ 8120 /* Generic PowerPC 750 (G3) */
7659 - POWERPC_DEF("750", CPU_POWERPC_7x0, 7x0), 8121 + POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
7660 /* Code name for PowerPC 750 */ 8122 /* Code name for PowerPC 750 */
7661 - POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 7x0), 8123 + POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
7662 /* PowerPC 740/750 is also known as G3 */ 8124 /* PowerPC 740/750 is also known as G3 */
7663 - POWERPC_DEF("G3", CPU_POWERPC_7x0, 7x0), 8125 + POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
  8126 + /* PowerPC 740 v1.0 (G3) */
  8127 + POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
  8128 + /* PowerPC 750 v1.0 (G3) */
  8129 + POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
7664 /* PowerPC 740 v2.0 (G3) */ 8130 /* PowerPC 740 v2.0 (G3) */
7665 - POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 7x0), 8131 + POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
7666 /* PowerPC 750 v2.0 (G3) */ 8132 /* PowerPC 750 v2.0 (G3) */
7667 - POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 7x0), 8133 + POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
7668 /* PowerPC 740 v2.1 (G3) */ 8134 /* PowerPC 740 v2.1 (G3) */
7669 - POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 7x0), 8135 + POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
7670 /* PowerPC 750 v2.1 (G3) */ 8136 /* PowerPC 750 v2.1 (G3) */
7671 - POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 7x0), 8137 + POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
7672 /* PowerPC 740 v2.2 (G3) */ 8138 /* PowerPC 740 v2.2 (G3) */
7673 - POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 7x0), 8139 + POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
7674 /* PowerPC 750 v2.2 (G3) */ 8140 /* PowerPC 750 v2.2 (G3) */
7675 - POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 7x0), 8141 + POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
7676 /* PowerPC 740 v3.0 (G3) */ 8142 /* PowerPC 740 v3.0 (G3) */
7677 - POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 7x0), 8143 + POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
7678 /* PowerPC 750 v3.0 (G3) */ 8144 /* PowerPC 750 v3.0 (G3) */
7679 - POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 7x0), 8145 + POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
7680 /* PowerPC 740 v3.1 (G3) */ 8146 /* PowerPC 740 v3.1 (G3) */
7681 - POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 7x0), 8147 + POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
7682 /* PowerPC 750 v3.1 (G3) */ 8148 /* PowerPC 750 v3.1 (G3) */
7683 - POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 7x0), 8149 + POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
7684 /* PowerPC 740E (G3) */ 8150 /* PowerPC 740E (G3) */
7685 - POWERPC_DEF("740e", CPU_POWERPC_740E, 7x0), 8151 + POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
  8152 + /* PowerPC 750E (G3) */
  8153 + POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
7686 /* PowerPC 740P (G3) */ 8154 /* PowerPC 740P (G3) */
7687 - POWERPC_DEF("740p", CPU_POWERPC_7x0P, 7x0), 8155 + POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
7688 /* PowerPC 750P (G3) */ 8156 /* PowerPC 750P (G3) */
7689 - POWERPC_DEF("750p", CPU_POWERPC_7x0P, 7x0), 8157 + POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
7690 /* Code name for PowerPC 740P/750P (G3) */ 8158 /* Code name for PowerPC 740P/750P (G3) */
7691 - POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 7x0), 8159 + POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
7692 /* PowerPC 750CL (G3 embedded) */ 8160 /* PowerPC 750CL (G3 embedded) */
7693 - POWERPC_DEF("750cl", CPU_POWERPC_750CL, 7x0), 8161 + POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
  8162 + /* PowerPC 750CL v1.0 */
  8163 + POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
  8164 + /* PowerPC 750CL v2.0 */
  8165 + POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
7694 /* PowerPC 750CX (G3 embedded) */ 8166 /* PowerPC 750CX (G3 embedded) */
7695 - POWERPC_DEF("750cx", CPU_POWERPC_750CX, 7x0), 8167 + POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
  8168 + /* PowerPC 750CX v1.0 (G3 embedded) */
  8169 + POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
  8170 + /* PowerPC 750CX v2.1 (G3 embedded) */
  8171 + POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
7696 /* PowerPC 750CX v2.1 (G3 embedded) */ 8172 /* PowerPC 750CX v2.1 (G3 embedded) */
7697 - POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 7x0), 8173 + POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
7698 /* PowerPC 750CX v2.2 (G3 embedded) */ 8174 /* PowerPC 750CX v2.2 (G3 embedded) */
7699 - POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 7x0), 8175 + POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
7700 /* PowerPC 750CXe (G3 embedded) */ 8176 /* PowerPC 750CXe (G3 embedded) */
7701 - POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 7x0), 8177 + POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
7702 /* PowerPC 750CXe v2.1 (G3 embedded) */ 8178 /* PowerPC 750CXe v2.1 (G3 embedded) */
7703 - POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 7x0), 8179 + POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
7704 /* PowerPC 750CXe v2.2 (G3 embedded) */ 8180 /* PowerPC 750CXe v2.2 (G3 embedded) */
7705 - POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 7x0), 8181 + POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
7706 /* PowerPC 750CXe v2.3 (G3 embedded) */ 8182 /* PowerPC 750CXe v2.3 (G3 embedded) */
7707 - POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 7x0), 8183 + POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
7708 /* PowerPC 750CXe v2.4 (G3 embedded) */ 8184 /* PowerPC 750CXe v2.4 (G3 embedded) */
7709 - POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 7x0), 8185 + POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
7710 /* PowerPC 750CXe v2.4b (G3 embedded) */ 8186 /* PowerPC 750CXe v2.4b (G3 embedded) */
7711 - POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 7x0), 8187 + POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
  8188 + /* PowerPC 750CXe v3.0 (G3 embedded) */
  8189 + POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
7712 /* PowerPC 750CXe v3.1 (G3 embedded) */ 8190 /* PowerPC 750CXe v3.1 (G3 embedded) */
7713 - POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 7x0), 8191 + POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
7714 /* PowerPC 750CXe v3.1b (G3 embedded) */ 8192 /* PowerPC 750CXe v3.1b (G3 embedded) */
7715 - POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 7x0), 8193 + POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
7716 /* PowerPC 750CXr (G3 embedded) */ 8194 /* PowerPC 750CXr (G3 embedded) */
7717 - POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 7x0),  
7718 - /* PowerPC 750E (G3) */  
7719 - POWERPC_DEF("750e", CPU_POWERPC_750E, 7x0), 8195 + POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
7720 /* PowerPC 750FL (G3 embedded) */ 8196 /* PowerPC 750FL (G3 embedded) */
7721 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx), 8197 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
7722 /* PowerPC 750FX (G3 embedded) */ 8198 /* PowerPC 750FX (G3 embedded) */
@@ -7732,80 +8208,84 @@ static const ppc_def_t ppc_defs[] = { @@ -7732,80 +8208,84 @@ static const ppc_def_t ppc_defs[] = {
7732 /* PowerPC 750FX v2.3 (G3 embedded) */ 8208 /* PowerPC 750FX v2.3 (G3 embedded) */
7733 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx), 8209 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
7734 /* PowerPC 750GL (G3 embedded) */ 8210 /* PowerPC 750GL (G3 embedded) */
7735 - POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750fx), 8211 + POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
7736 /* PowerPC 750GX (G3 embedded) */ 8212 /* PowerPC 750GX (G3 embedded) */
7737 - POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750fx), 8213 + POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
7738 /* PowerPC 750GX v1.0 (G3 embedded) */ 8214 /* PowerPC 750GX v1.0 (G3 embedded) */
7739 - POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750fx), 8215 + POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
7740 /* PowerPC 750GX v1.1 (G3 embedded) */ 8216 /* PowerPC 750GX v1.1 (G3 embedded) */
7741 - POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750fx), 8217 + POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
7742 /* PowerPC 750GX v1.2 (G3 embedded) */ 8218 /* PowerPC 750GX v1.2 (G3 embedded) */
7743 - POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750fx), 8219 + POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
7744 /* PowerPC 750L (G3 embedded) */ 8220 /* PowerPC 750L (G3 embedded) */
7745 - POWERPC_DEF("750l", CPU_POWERPC_750L, 7x0), 8221 + POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
7746 /* Code name for PowerPC 750L (G3 embedded) */ 8222 /* Code name for PowerPC 750L (G3 embedded) */
7747 - POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 7x0), 8223 + POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
  8224 + /* PowerPC 750L v2.0 (G3 embedded) */
  8225 + POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
  8226 + /* PowerPC 750L v2.1 (G3 embedded) */
  8227 + POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
7748 /* PowerPC 750L v2.2 (G3 embedded) */ 8228 /* PowerPC 750L v2.2 (G3 embedded) */
7749 - POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 7x0), 8229 + POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
7750 /* PowerPC 750L v3.0 (G3 embedded) */ 8230 /* PowerPC 750L v3.0 (G3 embedded) */
7751 - POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 7x0), 8231 + POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
7752 /* PowerPC 750L v3.2 (G3 embedded) */ 8232 /* PowerPC 750L v3.2 (G3 embedded) */
7753 - POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 7x0), 8233 + POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
7754 /* Generic PowerPC 745 */ 8234 /* Generic PowerPC 745 */
7755 - POWERPC_DEF("745", CPU_POWERPC_7x5, 7x5), 8235 + POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
7756 /* Generic PowerPC 755 */ 8236 /* Generic PowerPC 755 */
7757 - POWERPC_DEF("755", CPU_POWERPC_7x5, 7x5), 8237 + POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
7758 /* Code name for PowerPC 745/755 */ 8238 /* Code name for PowerPC 745/755 */
7759 - POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 7x5), 8239 + POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
7760 /* PowerPC 745 v1.0 */ 8240 /* PowerPC 745 v1.0 */
7761 - POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 7x5), 8241 + POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
7762 /* PowerPC 755 v1.0 */ 8242 /* PowerPC 755 v1.0 */
7763 - POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 7x5), 8243 + POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
7764 /* PowerPC 745 v1.1 */ 8244 /* PowerPC 745 v1.1 */
7765 - POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 7x5), 8245 + POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
7766 /* PowerPC 755 v1.1 */ 8246 /* PowerPC 755 v1.1 */
7767 - POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 7x5), 8247 + POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
7768 /* PowerPC 745 v2.0 */ 8248 /* PowerPC 745 v2.0 */
7769 - POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 7x5), 8249 + POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
7770 /* PowerPC 755 v2.0 */ 8250 /* PowerPC 755 v2.0 */
7771 - POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 7x5), 8251 + POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
7772 /* PowerPC 745 v2.1 */ 8252 /* PowerPC 745 v2.1 */
7773 - POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 7x5), 8253 + POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
7774 /* PowerPC 755 v2.1 */ 8254 /* PowerPC 755 v2.1 */
7775 - POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 7x5), 8255 + POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
7776 /* PowerPC 745 v2.2 */ 8256 /* PowerPC 745 v2.2 */
7777 - POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 7x5), 8257 + POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
7778 /* PowerPC 755 v2.2 */ 8258 /* PowerPC 755 v2.2 */
7779 - POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 7x5), 8259 + POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
7780 /* PowerPC 745 v2.3 */ 8260 /* PowerPC 745 v2.3 */
7781 - POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 7x5), 8261 + POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
7782 /* PowerPC 755 v2.3 */ 8262 /* PowerPC 755 v2.3 */
7783 - POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 7x5), 8263 + POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
7784 /* PowerPC 745 v2.4 */ 8264 /* PowerPC 745 v2.4 */
7785 - POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 7x5), 8265 + POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
7786 /* PowerPC 755 v2.4 */ 8266 /* PowerPC 755 v2.4 */
7787 - POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 7x5), 8267 + POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
7788 /* PowerPC 745 v2.5 */ 8268 /* PowerPC 745 v2.5 */
7789 - POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 7x5), 8269 + POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
7790 /* PowerPC 755 v2.5 */ 8270 /* PowerPC 755 v2.5 */
7791 - POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 7x5), 8271 + POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
7792 /* PowerPC 745 v2.6 */ 8272 /* PowerPC 745 v2.6 */
7793 - POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 7x5), 8273 + POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
7794 /* PowerPC 755 v2.6 */ 8274 /* PowerPC 755 v2.6 */
7795 - POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 7x5), 8275 + POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
7796 /* PowerPC 745 v2.7 */ 8276 /* PowerPC 745 v2.7 */
7797 - POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 7x5), 8277 + POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
7798 /* PowerPC 755 v2.7 */ 8278 /* PowerPC 755 v2.7 */
7799 - POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 7x5), 8279 + POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
7800 /* PowerPC 745 v2.8 */ 8280 /* PowerPC 745 v2.8 */
7801 - POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 7x5), 8281 + POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
7802 /* PowerPC 755 v2.8 */ 8282 /* PowerPC 755 v2.8 */
7803 - POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 7x5), 8283 + POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
7804 #if defined (TODO) 8284 #if defined (TODO)
7805 /* PowerPC 745P (G3) */ 8285 /* PowerPC 745P (G3) */
7806 - POWERPC_DEF("745p", CPU_POWERPC_7x5P, 7x5), 8286 + POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
7807 /* PowerPC 755P (G3) */ 8287 /* PowerPC 755P (G3) */
7808 - POWERPC_DEF("755p", CPU_POWERPC_7x5P, 7x5), 8288 + POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
7809 #endif 8289 #endif
7810 /* PowerPC 74xx family */ 8290 /* PowerPC 74xx family */
7811 /* PowerPC 7400 (G4) */ 8291 /* PowerPC 7400 (G4) */