gwj / at91sam9263 · Commits

Commit bd497938895ec4fd7b327aac4de390e34f543509

Authored by bellard
1 parent 16d17fdb

use generic GenOpFunc 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@543 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 4 additions and 36 deletions
target-arm/translate.c
  View file @bd49793
... ... @@ -51,11 +51,6 @@ enum {
51 51  
52 52 #include "gen-op.h"
53 53  
54   -typedef void (GenOpFunc)(void);
55   -typedef void (GenOpFunc1)(long);
56   -typedef void (GenOpFunc2)(long, long);
57   -typedef void (GenOpFunc3)(long, long, long);
58   -
59 54 static GenOpFunc2 *gen_test_cc[14] = {
60 55 gen_op_test_eq,
61 56 gen_op_test_ne,
... ...
target-i386/translate.c
  View file @bd49793
... ... @@ -128,11 +128,6 @@ enum {
128 128 NB_OREGS,
129 129 };
130 130  
131   -typedef void (GenOpFunc)(void);
132   -typedef void (GenOpFunc1)(long);
133   -typedef void (GenOpFunc2)(long, long);
134   -typedef void (GenOpFunc3)(long, long, long);
135   -
136 131 static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
137 132 [OT_BYTE] = {
138 133 gen_op_movb_EAX_T0,
... ...
target-sparc/translate.c
  View file @bd49793
... ... @@ -2,6 +2,7 @@
2 2 SPARC translation
3 3  
4 4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
  5 + Copyright (C) 2003 Fabrice Bellard
5 6  
6 7 This library is free software; you can redistribute it and/or
7 8 modify it under the terms of the GNU Lesser General Public
... ... @@ -19,33 +20,15 @@
19 20 */
20 21  
21 22 /*
22   - SPARC has two pitfalls: Delay slots and (a)nullification.
23   - This is currently solved as follows:
24   -
25   - 'call' instructions simply execute the delay slot before the actual
26   - control transfer instructions.
27   -
28   - 'jmpl' instructions execute calculate the destination, then execute
29   - the delay slot and then do the control transfer.
30   -
31   - (conditional) branch instructions are the most difficult ones, as the
32   - delay slot may be nullified (ie. not executed). This happens when a
33   - conditional branch is not executed (thus no control transfer happens)
34   - and the 'anull' bit in the branch instruction opcode is set. This is
35   - currently solved by doing a jump after the delay slot instruction.
36   -
37 23 TODO-list:
38 24  
39   - Register window overflow/underflow check
  25 + NPC/PC static optimisations (use JUMP_TB when possible)
40 26 FPU-Instructions
41   - Coprocessor-Instructions
42   - Check signedness issues
43 27 Privileged instructions
  28 + Coprocessor-Instructions
44 29 Optimize synthetic instructions
45 30 Optional alignment and privileged instruction check
46   -
47   - -- TMO, 09/03/03
48   - */
  31 +*/
49 32  
50 33 #include <stdarg.h>
51 34 #include <stdlib.h>
... ... @@ -87,11 +70,6 @@ enum {
87 70  
88 71 static void disas_sparc_insn(DisasContext * dc);
89 72  
90   -typedef void (GenOpFunc) (void);
91   -typedef void (GenOpFunc1) (long);
92   -typedef void (GenOpFunc2) (long, long);
93   -typedef void (GenOpFunc3) (long, long, long);
94   -
95 73 static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
96 74 {
97 75 gen_op_movl_g0_T0,
... ...