gwj / at91sam9263 · Commits

Commit bc24a225af2464dc30f88d6f930779cbf0e22b67

Authored by Paul Brook
1 parent d4ec5228

Follow coding conventions 

Remove explicit struct qualifiers and rename structure types.

Signed-off-by: Paul Brook <paul@codesourcery.com>
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console.h
  View file @bc24a22
... ... @@ -35,7 +35,7 @@ void kbd_put_keycode(int keycode);
35 35 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
36 36 int kbd_mouse_is_absolute(void);
37 37  
38   -struct mouse_transform_info_s {
  38 +struct MouseTransformInfo {
39 39 /* Touchscreen resolution */
40 40 int x;
41 41 int y;
... ...
hw/ads7846.c
  View file @bc24a22
... ... @@ -11,7 +11,7 @@
11 11 #include "devices.h"
12 12 #include "console.h"
13 13  
14   -struct ads7846_state_s {
  14 +struct ADS7846State {
15 15 qemu_irq interrupt;
16 16  
17 17 int input[8];
... ... @@ -46,7 +46,7 @@ struct ads7846_state_s {
46 46 #define ADS_Z1POS(x, y) 600
47 47 #define ADS_Z2POS(x, y) (600 + 6000 / ADS_XPOS(x, y))
48 48  
49   -static void ads7846_int_update(struct ads7846_state_s *s)
  49 +static void ads7846_int_update(ADS7846State *s)
50 50 {
51 51 if (s->interrupt)
52 52 qemu_set_irq(s->interrupt, s->pressure == 0);
... ... @@ -54,14 +54,14 @@ static void ads7846_int_update(struct ads7846_state_s *s)
54 54  
55 55 uint32_t ads7846_read(void *opaque)
56 56 {
57   - struct ads7846_state_s *s = (struct ads7846_state_s *) opaque;
  57 + ADS7846State *s = (ADS7846State *) opaque;
58 58  
59 59 return s->output;
60 60 }
61 61  
62 62 void ads7846_write(void *opaque, uint32_t value)
63 63 {
64   - struct ads7846_state_s *s = (struct ads7846_state_s *) opaque;
  64 + ADS7846State *s = (ADS7846State *) opaque;
65 65  
66 66 switch (s->cycle ++) {
67 67 case 0:
... ... @@ -94,7 +94,7 @@ void ads7846_write(void *opaque, uint32_t value)
94 94 static void ads7846_ts_event(void *opaque,
95 95 int x, int y, int z, int buttons_state)
96 96 {
97   - struct ads7846_state_s *s = opaque;
  97 + ADS7846State *s = opaque;
98 98  
99 99 if (buttons_state) {
100 100 x = 0x7fff - x;
... ... @@ -113,7 +113,7 @@ static void ads7846_ts_event(void *opaque,
113 113  
114 114 static void ads7846_save(QEMUFile *f, void *opaque)
115 115 {
116   - struct ads7846_state_s *s = (struct ads7846_state_s *) opaque;
  116 + ADS7846State *s = (ADS7846State *) opaque;
117 117 int i;
118 118  
119 119 for (i = 0; i < 8; i ++)
... ... @@ -125,7 +125,7 @@ static void ads7846_save(QEMUFile *f, void *opaque)
125 125  
126 126 static int ads7846_load(QEMUFile *f, void *opaque, int version_id)
127 127 {
128   - struct ads7846_state_s *s = (struct ads7846_state_s *) opaque;
  128 + ADS7846State *s = (ADS7846State *) opaque;
129 129 int i;
130 130  
131 131 for (i = 0; i < 8; i ++)
... ... @@ -140,12 +140,12 @@ static int ads7846_load(QEMUFile *f, void *opaque, int version_id)
140 140 return 0;
141 141 }
142 142  
143   -struct ads7846_state_s *ads7846_init(qemu_irq penirq)
  143 +ADS7846State *ads7846_init(qemu_irq penirq)
144 144 {
145   - struct ads7846_state_s *s;
146   - s = (struct ads7846_state_s *)
147   - qemu_mallocz(sizeof(struct ads7846_state_s));
148   - memset(s, 0, sizeof(struct ads7846_state_s));
  145 + ADS7846State *s;
  146 + s = (ADS7846State *)
  147 + qemu_mallocz(sizeof(ADS7846State));
  148 + memset(s, 0, sizeof(ADS7846State));
149 149  
150 150 s->interrupt = penirq;
151 151  
... ...
hw/axis_dev88.c
  View file @bc24a22
... ... @@ -37,7 +37,7 @@
37 37  
38 38 struct nand_state_t
39 39 {
40   - struct nand_flash_s *nand;
  40 + NANDFlashState *nand;
41 41 unsigned int rdy:1;
42 42 unsigned int ale:1;
43 43 unsigned int cle:1;
... ...
hw/blizzard.c
  View file @bc24a22
... ... @@ -28,7 +28,7 @@
28 28  
29 29 typedef void (*blizzard_fn_t)(uint8_t *, const uint8_t *, unsigned int);
30 30  
31   -struct blizzard_s {
  31 +typedef struct {
32 32 uint8_t reg;
33 33 uint32_t addr;
34 34 int swallow;
... ... @@ -120,7 +120,7 @@ struct blizzard_s {
120 120 int pitch;
121 121 blizzard_fn_t line_fn;
122 122 } data;
123   -};
  123 +} BlizzardState;
124 124  
125 125 /* Bytes(!) per pixel */
126 126 static const int blizzard_iformat_bpp[0x10] = {
... ... @@ -144,7 +144,7 @@ static inline void blizzard_rgb2yuv(int r, int g, int b,
144 144 *v = 0x80 + ((0xe0e * r - 0x0bc7 * g - 0x247 * b) >> 13);
145 145 }
146 146  
147   -static void blizzard_window(struct blizzard_s *s)
  147 +static void blizzard_window(BlizzardState *s)
148 148 {
149 149 uint8_t *src, *dst;
150 150 int bypp[2];
... ... @@ -175,7 +175,7 @@ static void blizzard_window(struct blizzard_s *s)
175 175 fn(dst, src, bypl[2]);
176 176 }
177 177  
178   -static int blizzard_transfer_setup(struct blizzard_s *s)
  178 +static int blizzard_transfer_setup(BlizzardState *s)
179 179 {
180 180 if (s->source > 3 || !s->bpp ||
181 181 s->ix[1] < s->ix[0] || s->iy[1] < s->iy[0])
... ... @@ -199,7 +199,7 @@ static int blizzard_transfer_setup(struct blizzard_s *s)
199 199 return 1;
200 200 }
201 201  
202   -static void blizzard_reset(struct blizzard_s *s)
  202 +static void blizzard_reset(BlizzardState *s)
203 203 {
204 204 s->reg = 0;
205 205 s->swallow = 0;
... ... @@ -280,14 +280,14 @@ static void blizzard_reset(struct blizzard_s *s)
280 280 }
281 281  
282 282 static inline void blizzard_invalidate_display(void *opaque) {
283   - struct blizzard_s *s = (struct blizzard_s *) opaque;
  283 + BlizzardState *s = (BlizzardState *) opaque;
284 284  
285 285 s->invalidate = 1;
286 286 }
287 287  
288 288 static uint16_t blizzard_reg_read(void *opaque, uint8_t reg)
289 289 {
290   - struct blizzard_s *s = (struct blizzard_s *) opaque;
  290 + BlizzardState *s = (BlizzardState *) opaque;
291 291  
292 292 switch (reg) {
293 293 case 0x00: /* Revision Code */
... ... @@ -490,7 +490,7 @@ static uint16_t blizzard_reg_read(void *opaque, uint8_t reg)
490 490  
491 491 static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
492 492 {
493   - struct blizzard_s *s = (struct blizzard_s *) opaque;
  493 + BlizzardState *s = (BlizzardState *) opaque;
494 494  
495 495 switch (reg) {
496 496 case 0x04: /* PLL M-Divider */
... ... @@ -831,7 +831,7 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
831 831  
832 832 uint16_t s1d13745_read(void *opaque, int dc)
833 833 {
834   - struct blizzard_s *s = (struct blizzard_s *) opaque;
  834 + BlizzardState *s = (BlizzardState *) opaque;
835 835 uint16_t value = blizzard_reg_read(s, s->reg);
836 836  
837 837 if (s->swallow -- > 0)
... ... @@ -844,7 +844,7 @@ uint16_t s1d13745_read(void *opaque, int dc)
844 844  
845 845 void s1d13745_write(void *opaque, int dc, uint16_t value)
846 846 {
847   - struct blizzard_s *s = (struct blizzard_s *) opaque;
  847 + BlizzardState *s = (BlizzardState *) opaque;
848 848  
849 849 if (s->swallow -- > 0)
850 850 return;
... ... @@ -860,7 +860,7 @@ void s1d13745_write(void *opaque, int dc, uint16_t value)
860 860 void s1d13745_write_block(void *opaque, int dc,
861 861 void *buf, size_t len, int pitch)
862 862 {
863   - struct blizzard_s *s = (struct blizzard_s *) opaque;
  863 + BlizzardState *s = (BlizzardState *) opaque;
864 864  
865 865 while (len > 0) {
866 866 if (s->reg == 0x90 && dc &&
... ... @@ -886,7 +886,7 @@ void s1d13745_write_block(void *opaque, int dc,
886 886  
887 887 static void blizzard_update_display(void *opaque)
888 888 {
889   - struct blizzard_s *s = (struct blizzard_s *) opaque;
  889 + BlizzardState *s = (BlizzardState *) opaque;
890 890 int y, bypp, bypl, bwidth;
891 891 uint8_t *src, *dst;
892 892  
... ... @@ -935,7 +935,7 @@ static void blizzard_update_display(void *opaque)
935 935 }
936 936  
937 937 static void blizzard_screen_dump(void *opaque, const char *filename) {
938   - struct blizzard_s *s = (struct blizzard_s *) opaque;
  938 + BlizzardState *s = (BlizzardState *) opaque;
939 939  
940 940 blizzard_update_display(opaque);
941 941 if (s && ds_get_data(s->state))
... ... @@ -955,7 +955,7 @@ static void blizzard_screen_dump(void *opaque, const char *filename) {
955 955  
956 956 void *s1d13745_init(qemu_irq gpio_int)
957 957 {
958   - struct blizzard_s *s = (struct blizzard_s *) qemu_mallocz(sizeof(*s));
  958 + BlizzardState *s = (BlizzardState *) qemu_mallocz(sizeof(*s));
959 959  
960 960 s->fb = qemu_malloc(0x180000);
961 961  
... ...
hw/cbus.c
  View file @bc24a22
... ... @@ -28,9 +28,14 @@
28 28  
29 29 //#define DEBUG
30 30  
31   -struct cbus_slave_s;
32   -struct cbus_priv_s {
33   - struct cbus_s cbus;
  31 +typedef struct {
  32 + void *opaque;
  33 + void (*io)(void *opaque, int rw, int reg, uint16_t *val);
  34 + int addr;
  35 +} CBusSlave;
  36 +
  37 +typedef struct {
  38 + CBus cbus;
34 39  
35 40 int sel;
36 41 int dat;
... ... @@ -48,16 +53,10 @@ struct cbus_priv_s {
48 53 cbus_value,
49 54 } cycle;
50 55  
51   - struct cbus_slave_s *slave[8];
52   -};
53   -
54   -struct cbus_slave_s {
55   - void *opaque;
56   - void (*io)(void *opaque, int rw, int reg, uint16_t *val);
57   - int addr;
58   -};
  56 + CBusSlave *slave[8];
  57 +} CBusPriv;
59 58  
60   -static void cbus_io(struct cbus_priv_s *s)
  59 +static void cbus_io(CBusPriv *s)
61 60 {
62 61 if (s->slave[s->addr])
63 62 s->slave[s->addr]->io(s->slave[s->addr]->opaque,
... ... @@ -66,7 +65,7 @@ static void cbus_io(struct cbus_priv_s *s)
66 65 hw_error("%s: bad slave address %i\n", __FUNCTION__, s->addr);
67 66 }
68 67  
69   -static void cbus_cycle(struct cbus_priv_s *s)
  68 +static void cbus_cycle(CBusPriv *s)
70 69 {
71 70 switch (s->cycle) {
72 71 case cbus_address:
... ... @@ -97,7 +96,7 @@ static void cbus_cycle(struct cbus_priv_s *s)
97 96  
98 97 static void cbus_clk(void *opaque, int line, int level)
99 98 {
100   - struct cbus_priv_s *s = (struct cbus_priv_s *) opaque;
  99 + CBusPriv *s = (CBusPriv *) opaque;
101 100  
102 101 if (!s->sel && level && !s->clk) {
103 102 if (s->dir)
... ... @@ -114,14 +113,14 @@ static void cbus_clk(void *opaque, int line, int level)
114 113  
115 114 static void cbus_dat(void *opaque, int line, int level)
116 115 {
117   - struct cbus_priv_s *s = (struct cbus_priv_s *) opaque;
  116 + CBusPriv *s = (CBusPriv *) opaque;
118 117  
119 118 s->dat = level;
120 119 }
121 120  
122 121 static void cbus_sel(void *opaque, int line, int level)
123 122 {
124   - struct cbus_priv_s *s = (struct cbus_priv_s *) opaque;
  123 + CBusPriv *s = (CBusPriv *) opaque;
125 124  
126 125 if (!level) {
127 126 s->dir = 1;
... ... @@ -132,9 +131,9 @@ static void cbus_sel(void *opaque, int line, int level)
132 131 s->sel = level;
133 132 }
134 133  
135   -struct cbus_s *cbus_init(qemu_irq dat)
  134 +CBus *cbus_init(qemu_irq dat)
136 135 {
137   - struct cbus_priv_s *s = (struct cbus_priv_s *) qemu_mallocz(sizeof(*s));
  136 + CBusPriv *s = (CBusPriv *) qemu_mallocz(sizeof(*s));
138 137  
139 138 s->dat_out = dat;
140 139 s->cbus.clk = qemu_allocate_irqs(cbus_clk, s, 1)[0];
... ... @@ -148,16 +147,16 @@ struct cbus_s *cbus_init(qemu_irq dat)
148 147 return &s->cbus;
149 148 }
150 149  
151   -void cbus_attach(struct cbus_s *bus, void *slave_opaque)
  150 +void cbus_attach(CBus *bus, void *slave_opaque)
152 151 {
153   - struct cbus_slave_s *slave = (struct cbus_slave_s *) slave_opaque;
154   - struct cbus_priv_s *s = (struct cbus_priv_s *) bus;
  152 + CBusSlave *slave = (CBusSlave *) slave_opaque;
  153 + CBusPriv *s = (CBusPriv *) bus;
155 154  
156 155 s->slave[slave->addr] = slave;
157 156 }
158 157  
159 158 /* Retu/Vilma */
160   -struct cbus_retu_s {
  159 +typedef struct {
161 160 uint16_t irqst;
162 161 uint16_t irqen;
163 162 uint16_t cc[2];
... ... @@ -172,10 +171,10 @@ struct cbus_retu_s {
172 171  
173 172 int is_vilma;
174 173 qemu_irq irq;
175   - struct cbus_slave_s cbus;
176   -};
  174 + CBusSlave cbus;
  175 +} CBusRetu;
177 176  
178   -static void retu_interrupt_update(struct cbus_retu_s *s)
  177 +static void retu_interrupt_update(CBusRetu *s)
179 178 {
180 179 qemu_set_irq(s->irq, s->irqst & ~s->irqen);
181 180 }
... ... @@ -237,7 +236,7 @@ enum {
237 236 retu_adc_self_temp = 13, /* RETU temperature */
238 237 };
239 238  
240   -static inline uint16_t retu_read(struct cbus_retu_s *s, int reg)
  239 +static inline uint16_t retu_read(CBusRetu *s, int reg)
241 240 {
242 241 #ifdef DEBUG
243 242 printf("RETU read at %02x\n", reg);
... ... @@ -304,7 +303,7 @@ static inline uint16_t retu_read(struct cbus_retu_s *s, int reg)
304 303 }
305 304 }
306 305  
307   -static inline void retu_write(struct cbus_retu_s *s, int reg, uint16_t val)
  306 +static inline void retu_write(CBusRetu *s, int reg, uint16_t val)
308 307 {
309 308 #ifdef DEBUG
310 309 printf("RETU write of %04x at %02x\n", val, reg);
... ... @@ -379,7 +378,7 @@ static inline void retu_write(struct cbus_retu_s *s, int reg, uint16_t val)
379 378  
380 379 static void retu_io(void *opaque, int rw, int reg, uint16_t *val)
381 380 {
382   - struct cbus_retu_s *s = (struct cbus_retu_s *) opaque;
  381 + CBusRetu *s = (CBusRetu *) opaque;
383 382  
384 383 if (rw)
385 384 *val = retu_read(s, reg);
... ... @@ -389,7 +388,7 @@ static void retu_io(void *opaque, int rw, int reg, uint16_t *val)
389 388  
390 389 void *retu_init(qemu_irq irq, int vilma)
391 390 {
392   - struct cbus_retu_s *s = (struct cbus_retu_s *) qemu_mallocz(sizeof(*s));
  391 + CBusRetu *s = (CBusRetu *) qemu_mallocz(sizeof(*s));
393 392  
394 393 s->irq = irq;
395 394 s->irqen = 0xffff;
... ... @@ -419,8 +418,8 @@ void *retu_init(qemu_irq irq, int vilma)
419 418  
420 419 void retu_key_event(void *retu, int state)
421 420 {
422   - struct cbus_slave_s *slave = (struct cbus_slave_s *) retu;
423   - struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque;
  421 + CBusSlave *slave = (CBusSlave *) retu;
  422 + CBusRetu *s = (CBusRetu *) slave->opaque;
424 423  
425 424 s->irqst |= 1 << retu_int_pwr;
426 425 retu_interrupt_update(s);
... ... @@ -434,8 +433,8 @@ void retu_key_event(void *retu, int state)
434 433 #if 0
435 434 static void retu_head_event(void *retu, int state)
436 435 {
437   - struct cbus_slave_s *slave = (struct cbus_slave_s *) retu;
438   - struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque;
  436 + CBusSlave *slave = (CBusSlave *) retu;
  437 + CBusRetu *s = (CBusRetu *) slave->opaque;
439 438  
440 439 if ((s->cc[0] & 0x500) == 0x500) { /* TODO: Which bits? */
441 440 /* TODO: reissue the interrupt every 100ms or so. */
... ... @@ -451,8 +450,8 @@ static void retu_head_event(void *retu, int state)
451 450  
452 451 static void retu_hook_event(void *retu, int state)
453 452 {
454   - struct cbus_slave_s *slave = (struct cbus_slave_s *) retu;
455   - struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque;
  453 + CBusSlave *slave = (CBusSlave *) retu;
  454 + CBusRetu *s = (CBusRetu *) slave->opaque;
456 455  
457 456 if ((s->cc[0] & 0x500) == 0x500) {
458 457 /* TODO: reissue the interrupt every 100ms or so. */
... ... @@ -468,7 +467,7 @@ static void retu_hook_event(void *retu, int state)
468 467 #endif
469 468  
470 469 /* Tahvo/Betty */
471   -struct cbus_tahvo_s {
  470 +typedef struct {
472 471 uint16_t irqst;
473 472 uint16_t irqen;
474 473 uint8_t charger;
... ... @@ -478,10 +477,10 @@ struct cbus_tahvo_s {
478 477  
479 478 int is_betty;
480 479 qemu_irq irq;
481   - struct cbus_slave_s cbus;
482   -};
  480 + CBusSlave cbus;
  481 +} CBusTahvo;
483 482  
484   -static void tahvo_interrupt_update(struct cbus_tahvo_s *s)
  483 +static void tahvo_interrupt_update(CBusTahvo *s)
485 484 {
486 485 qemu_set_irq(s->irq, s->irqst & ~s->irqen);
487 486 }
... ... @@ -501,7 +500,7 @@ static void tahvo_interrupt_update(struct cbus_tahvo_s *s)
501 500 #define TAHVO_REG_NOPR 0x0c /* (RW) Number of periods */
502 501 #define TAHVO_REG_FRR 0x0d /* (RO) FR */
503 502  
504   -static inline uint16_t tahvo_read(struct cbus_tahvo_s *s, int reg)
  503 +static inline uint16_t tahvo_read(CBusTahvo *s, int reg)
505 504 {
506 505 #ifdef DEBUG
507 506 printf("TAHVO read at %02x\n", reg);
... ... @@ -543,7 +542,7 @@ static inline uint16_t tahvo_read(struct cbus_tahvo_s *s, int reg)
543 542 }
544 543 }
545 544  
546   -static inline void tahvo_write(struct cbus_tahvo_s *s, int reg, uint16_t val)
  545 +static inline void tahvo_write(CBusTahvo *s, int reg, uint16_t val)
547 546 {
548 547 #ifdef DEBUG
549 548 printf("TAHVO write of %04x at %02x\n", val, reg);
... ... @@ -595,7 +594,7 @@ static inline void tahvo_write(struct cbus_tahvo_s *s, int reg, uint16_t val)
595 594  
596 595 static void tahvo_io(void *opaque, int rw, int reg, uint16_t *val)
597 596 {
598   - struct cbus_tahvo_s *s = (struct cbus_tahvo_s *) opaque;
  597 + CBusTahvo *s = (CBusTahvo *) opaque;
599 598  
600 599 if (rw)
601 600 *val = tahvo_read(s, reg);
... ... @@ -605,7 +604,7 @@ static void tahvo_io(void *opaque, int rw, int reg, uint16_t *val)
605 604  
606 605 void *tahvo_init(qemu_irq irq, int betty)
607 606 {
608   - struct cbus_tahvo_s *s = (struct cbus_tahvo_s *) qemu_mallocz(sizeof(*s));
  607 + CBusTahvo *s = (CBusTahvo *) qemu_mallocz(sizeof(*s));
609 608  
610 609 s->irq = irq;
611 610 s->irqen = 0xffff;
... ...
hw/devices.h
  View file @bc24a22
... ... @@ -11,27 +11,25 @@ int ssd0323_xfer_ssi(void *opaque, int data);
11 11 void *ssd0323_init(qemu_irq *cmd_p);
12 12  
13 13 /* ads7846.c */
14   -struct ads7846_state_s;
  14 +typedef struct ADS7846State ADS7846State;
15 15 uint32_t ads7846_read(void *opaque);
16 16 void ads7846_write(void *opaque, uint32_t value);
17   -struct ads7846_state_s *ads7846_init(qemu_irq penirq);
  17 +ADS7846State *ads7846_init(qemu_irq penirq);
18 18  
19 19 /* tsc210x.c */
20   -struct uwire_slave_s;
21   -struct mouse_transform_info_s;
22   -struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
23   -struct uwire_slave_s *tsc2301_init(qemu_irq penirq, qemu_irq kbirq,
  20 +uWireSlave *tsc2102_init(qemu_irq pint, AudioState *audio);
  21 +uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq,
24 22 qemu_irq dav, AudioState *audio);
25   -struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip);
  23 +I2SCodec *tsc210x_codec(uWireSlave *chip);
26 24 uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len);
27   -void tsc210x_set_transform(struct uwire_slave_s *chip,
28   - struct mouse_transform_info_s *info);
29   -void tsc210x_key_event(struct uwire_slave_s *chip, int key, int down);
  25 +void tsc210x_set_transform(uWireSlave *chip,
  26 + MouseTransformInfo *info);
  27 +void tsc210x_key_event(uWireSlave *chip, int key, int down);
30 28  
31 29 /* tsc2005.c */
32 30 void *tsc2005_init(qemu_irq pintdav);
33 31 uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len);
34   -void tsc2005_set_transform(void *opaque, struct mouse_transform_info_s *info);
  32 +void tsc2005_set_transform(void *opaque, MouseTransformInfo *info);
35 33  
36 34 /* stellaris_input.c */
37 35 void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);
... ... @@ -44,13 +42,13 @@ void s1d13745_write_block(void *opaque, int dc,
44 42 uint16_t s1d13745_read(void *opaque, int dc);
45 43  
46 44 /* cbus.c */
47   -struct cbus_s {
  45 +typedef struct {
48 46 qemu_irq clk;
49 47 qemu_irq dat;
50 48 qemu_irq sel;
51   -};
52   -struct cbus_s *cbus_init(qemu_irq dat_out);
53   -void cbus_attach(struct cbus_s *bus, void *slave_opaque);
  49 +} CBus;
  50 +CBus *cbus_init(qemu_irq dat_out);
  51 +void cbus_attach(CBus *bus, void *slave_opaque);
54 52  
55 53 void *retu_init(qemu_irq irq, int vilma);
56 54 void *tahvo_init(qemu_irq irq, int betty);
... ... @@ -58,20 +56,20 @@ void *tahvo_init(qemu_irq irq, int betty);
58 56 void retu_key_event(void *retu, int state);
59 57  
60 58 /* tusb6010.c */
61   -struct tusb_s;
62   -struct tusb_s *tusb6010_init(qemu_irq intr);
63   -int tusb6010_sync_io(struct tusb_s *s);
64   -int tusb6010_async_io(struct tusb_s *s);
65   -void tusb6010_power(struct tusb_s *s, int on);
  59 +typedef struct TUSBState TUSBState;
  60 +TUSBState *tusb6010_init(qemu_irq intr);
  61 +int tusb6010_sync_io(TUSBState *s);
  62 +int tusb6010_async_io(TUSBState *s);
  63 +void tusb6010_power(TUSBState *s, int on);
66 64  
67 65 /* tc6393xb.c */
68   -struct tc6393xb_s;
  66 +typedef struct TC6393xbState TC6393xbState;
69 67 #define TC6393XB_RAM 0x110000 /* amount of ram for Video and USB */
70   -struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq);
71   -void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line,
  68 +TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq);
  69 +void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
72 70 qemu_irq handler);
73   -qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s);
74   -qemu_irq tc6393xb_l3v_get(struct tc6393xb_s *s);
  71 +qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s);
  72 +qemu_irq tc6393xb_l3v_get(TC6393xbState *s);
75 73  
76 74 /* sm501.c */
77 75 void sm501_init(uint32_t base, uint32_t local_mem_bytes, qemu_irq irq,
... ...
hw/ecc.c
  View file @bc24a22
... ... @@ -50,7 +50,7 @@ static const uint8_t nand_ecc_precalc_table[] = {
50 50 };
51 51  
52 52 /* Update ECC parity count. */
53   -uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample)
  53 +uint8_t ecc_digest(ECCState *s, uint8_t sample)
54 54 {
55 55 uint8_t idx = nand_ecc_precalc_table[sample];
56 56  
... ... @@ -65,7 +65,7 @@ uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample)
65 65 }
66 66  
67 67 /* Reinitialise the counters. */
68   -void ecc_reset(struct ecc_state_s *s)
  68 +void ecc_reset(ECCState *s)
69 69 {
70 70 s->lp[0] = 0x0000;
71 71 s->lp[1] = 0x0000;
... ... @@ -74,7 +74,7 @@ void ecc_reset(struct ecc_state_s *s)
74 74 }
75 75  
76 76 /* Save/restore */
77   -void ecc_put(QEMUFile *f, struct ecc_state_s *s)
  77 +void ecc_put(QEMUFile *f, ECCState *s)
78 78 {
79 79 qemu_put_8s(f, &s->cp);
80 80 qemu_put_be16s(f, &s->lp[0]);
... ... @@ -82,7 +82,7 @@ void ecc_put(QEMUFile *f, struct ecc_state_s *s)
82 82 qemu_put_be16s(f, &s->count);
83 83 }
84 84  
85   -void ecc_get(QEMUFile *f, struct ecc_state_s *s)
  85 +void ecc_get(QEMUFile *f, ECCState *s)
86 86 {
87 87 qemu_get_8s(f, &s->cp);
88 88 qemu_get_be16s(f, &s->lp[0]);
... ...
hw/flash.h
  View file @bc24a22
... ... @@ -17,14 +17,14 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
17 17 uint16_t unlock_addr0, uint16_t unlock_addr1);
18 18  
19 19 /* nand.c */
20   -struct nand_flash_s;
21   -struct nand_flash_s *nand_init(int manf_id, int chip_id);
22   -void nand_done(struct nand_flash_s *s);
23   -void nand_setpins(struct nand_flash_s *s,
  20 +typedef struct NANDFlashState NANDFlashState;
  21 +NANDFlashState *nand_init(int manf_id, int chip_id);
  22 +void nand_done(NANDFlashState *s);
  23 +void nand_setpins(NANDFlashState *s,
24 24 int cle, int ale, int ce, int wp, int gnd);
25   -void nand_getpins(struct nand_flash_s *s, int *rb);
26   -void nand_setio(struct nand_flash_s *s, uint8_t value);
27   -uint8_t nand_getio(struct nand_flash_s *s);
  25 +void nand_getpins(NANDFlashState *s, int *rb);
  26 +void nand_setio(NANDFlashState *s, uint8_t value);
  27 +uint8_t nand_getio(NANDFlashState *s);
28 28  
29 29 #define NAND_MFR_TOSHIBA 0x98
30 30 #define NAND_MFR_SAMSUNG 0xec
... ... @@ -42,13 +42,13 @@ void *onenand_init(uint32_t id, int regshift, qemu_irq irq);
42 42 void *onenand_raw_otp(void *opaque);
43 43  
44 44 /* ecc.c */
45   -struct ecc_state_s {
  45 +typedef struct {
46 46 uint8_t cp; /* Column parity */
47 47 uint16_t lp[2]; /* Line parity */
48 48 uint16_t count;
49   -};
  49 +} ECCState;
50 50  
51   -uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
52   -void ecc_reset(struct ecc_state_s *s);
53   -void ecc_put(QEMUFile *f, struct ecc_state_s *s);
54   -void ecc_get(QEMUFile *f, struct ecc_state_s *s);
  51 +uint8_t ecc_digest(ECCState *s, uint8_t sample);
  52 +void ecc_reset(ECCState *s);
  53 +void ecc_put(QEMUFile *f, ECCState *s);
  54 +void ecc_get(QEMUFile *f, ECCState *s);
... ...
hw/gumstix.c
  View file @bc24a22
... ... @@ -46,7 +46,7 @@ static void connex_init(ram_addr_t ram_size, int vga_ram_size,
46 46 const char *kernel_filename, const char *kernel_cmdline,
47 47 const char *initrd_filename, const char *cpu_model)
48 48 {
49   - struct pxa2xx_state_s *cpu;
  49 + PXA2xxState *cpu;
50 50 int index;
51 51  
52 52 uint32_t connex_rom = 0x01000000;
... ... @@ -80,7 +80,7 @@ static void verdex_init(ram_addr_t ram_size, int vga_ram_size,
80 80 const char *kernel_filename, const char *kernel_cmdline,
81 81 const char *initrd_filename, const char *cpu_model)
82 82 {
83   - struct pxa2xx_state_s *cpu;
  83 + PXA2xxState *cpu;
84 84 int index;
85 85  
86 86 uint32_t verdex_rom = 0x02000000;
... ...
hw/i2c.h
  View file @bc24a22
... ... @@ -46,12 +46,12 @@ void i2c_slave_save(QEMUFile *f, i2c_slave *dev);
46 46 void i2c_slave_load(QEMUFile *f, i2c_slave *dev);
47 47  
48 48 /* max111x.c */
49   -struct max111x_s;
  49 +typedef struct MAX111xState MAX111xState;
50 50 uint32_t max111x_read(void *opaque);
51 51 void max111x_write(void *opaque, uint32_t value);
52   -struct max111x_s *max1110_init(qemu_irq cb);
53   -struct max111x_s *max1111_init(qemu_irq cb);
54   -void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
  52 +MAX111xState *max1110_init(qemu_irq cb);
  53 +MAX111xState *max1111_init(qemu_irq cb);
  54 +void max111x_set_input(MAX111xState *s, int line, uint8_t value);
55 55  
56 56 /* max7310.c */
57 57 i2c_slave *max7310_init(i2c_bus *bus);
... ...
hw/ide.c
  View file @bc24a22
... ... @@ -3859,9 +3859,9 @@ void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
3859 3859 #define METADATA_SIZE 0x20
3860 3860  
3861 3861 /* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
3862   -struct md_s {
  3862 +typedef struct {
3863 3863 IDEState ide[2];
3864   - struct pcmcia_card_s card;
  3864 + PCMCIACardState card;
3865 3865 uint32_t attr_base;
3866 3866 uint32_t io_base;
3867 3867  
... ... @@ -3873,7 +3873,7 @@ struct md_s {
3873 3873 uint8_t ctrl;
3874 3874 uint16_t io;
3875 3875 int cycle;
3876   -};
  3876 +} MicroDriveState;
3877 3877  
3878 3878 /* Register bitfields */
3879 3879 enum md_opt {
... ... @@ -3902,7 +3902,7 @@ enum md_ctrl {
3902 3902 CTRL_SRST = 0x04,
3903 3903 };
3904 3904  
3905   -static inline void md_interrupt_update(struct md_s *s)
  3905 +static inline void md_interrupt_update(MicroDriveState *s)
3906 3906 {
3907 3907 if (!s->card.slot)
3908 3908 return;
... ... @@ -3915,7 +3915,7 @@ static inline void md_interrupt_update(struct md_s *s)
3915 3915  
3916 3916 static void md_set_irq(void *opaque, int irq, int level)
3917 3917 {
3918   - struct md_s *s = (struct md_s *) opaque;
  3918 + MicroDriveState *s = (MicroDriveState *) opaque;
3919 3919 if (level)
3920 3920 s->stat |= STAT_INT;
3921 3921 else
... ... @@ -3924,7 +3924,7 @@ static void md_set_irq(void *opaque, int irq, int level)
3924 3924 md_interrupt_update(s);
3925 3925 }
3926 3926  
3927   -static void md_reset(struct md_s *s)
  3927 +static void md_reset(MicroDriveState *s)
3928 3928 {
3929 3929 s->opt = OPT_MODE_MMAP;
3930 3930 s->stat = 0;
... ... @@ -3936,7 +3936,7 @@ static void md_reset(struct md_s *s)
3936 3936  
3937 3937 static uint8_t md_attr_read(void *opaque, uint32_t at)
3938 3938 {
3939   - struct md_s *s = (struct md_s *) opaque;
  3939 + MicroDriveState *s = (MicroDriveState *) opaque;
3940 3940 if (at < s->attr_base) {
3941 3941 if (at < s->card.cis_len)
3942 3942 return s->card.cis[at];
... ... @@ -3969,7 +3969,7 @@ static uint8_t md_attr_read(void *opaque, uint32_t at)
3969 3969  
3970 3970 static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
3971 3971 {
3972   - struct md_s *s = (struct md_s *) opaque;
  3972 + MicroDriveState *s = (MicroDriveState *) opaque;
3973 3973 at -= s->attr_base;
3974 3974  
3975 3975 switch (at) {
... ... @@ -4000,7 +4000,7 @@ static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
4000 4000  
4001 4001 static uint16_t md_common_read(void *opaque, uint32_t at)
4002 4002 {
4003   - struct md_s *s = (struct md_s *) opaque;
  4003 + MicroDriveState *s = (MicroDriveState *) opaque;
4004 4004 uint16_t ret;
4005 4005 at -= s->io_base;
4006 4006  
... ... @@ -4059,7 +4059,7 @@ static uint16_t md_common_read(void *opaque, uint32_t at)
4059 4059  
4060 4060 static void md_common_write(void *opaque, uint32_t at, uint16_t value)
4061 4061 {
4062   - struct md_s *s = (struct md_s *) opaque;
  4062 + MicroDriveState *s = (MicroDriveState *) opaque;
4063 4063 at -= s->io_base;
4064 4064  
4065 4065 switch (s->opt & OPT_MODE) {
... ... @@ -4120,7 +4120,7 @@ static void md_common_write(void *opaque, uint32_t at, uint16_t value)
4120 4120  
4121 4121 static void md_save(QEMUFile *f, void *opaque)
4122 4122 {
4123   - struct md_s *s = (struct md_s *) opaque;
  4123 + MicroDriveState *s = (MicroDriveState *) opaque;
4124 4124 int i;
4125 4125 uint8_t drive1_selected;
4126 4126  
... ... @@ -4142,7 +4142,7 @@ static void md_save(QEMUFile *f, void *opaque)
4142 4142  
4143 4143 static int md_load(QEMUFile *f, void *opaque, int version_id)
4144 4144 {
4145   - struct md_s *s = (struct md_s *) opaque;
  4145 + MicroDriveState *s = (MicroDriveState *) opaque;
4146 4146 int i;
4147 4147 uint8_t drive1_selected;
4148 4148  
... ... @@ -4351,7 +4351,7 @@ static const uint8_t dscm1xxxx_cis[0x14a] = {
4351 4351  
4352 4352 static int dscm1xxxx_attach(void *opaque)
4353 4353 {
4354   - struct md_s *md = (struct md_s *) opaque;
  4354 + MicroDriveState *md = (MicroDriveState *) opaque;
4355 4355 md->card.attr_read = md_attr_read;
4356 4356 md->card.attr_write = md_attr_write;
4357 4357 md->card.common_read = md_common_read;
... ... @@ -4371,14 +4371,14 @@ static int dscm1xxxx_attach(void *opaque)
4371 4371  
4372 4372 static int dscm1xxxx_detach(void *opaque)
4373 4373 {
4374   - struct md_s *md = (struct md_s *) opaque;
  4374 + MicroDriveState *md = (MicroDriveState *) opaque;
4375 4375 md_reset(md);
4376 4376 return 0;
4377 4377 }
4378 4378  
4379   -struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv)
  4379 +PCMCIACardState *dscm1xxxx_init(BlockDriverState *bdrv)
4380 4380 {
4381   - struct md_s *md = (struct md_s *) qemu_mallocz(sizeof(struct md_s));
  4381 + MicroDriveState *md = (MicroDriveState *) qemu_mallocz(sizeof(MicroDriveState));
4382 4382 md->card.state = md;
4383 4383 md->card.attach = dscm1xxxx_attach;
4384 4384 md->card.detach = dscm1xxxx_detach;
... ...
hw/lm832x.c
  View file @bc24a22
... ... @@ -24,7 +24,7 @@
24 24 #include "qemu-timer.h"
25 25 #include "console.h"
26 26  
27   -struct lm_kbd_s {
  27 +typedef struct {
28 28 i2c_slave i2c;
29 29 int i2c_dir;
30 30 int i2c_cycle;
... ... @@ -66,7 +66,7 @@ struct lm_kbd_s {
66 66 uint8_t addr[3];
67 67 QEMUTimer *tm[3];
68 68 } pwm;
69   -};
  69 +} LM823KbdState;
70 70  
71 71 #define INT_KEYPAD (1 << 0)
72 72 #define INT_ERROR (1 << 3)
... ... @@ -78,16 +78,16 @@ struct lm_kbd_s {
78 78 #define ERR_KEYOVR (1 << 2)
79 79 #define ERR_FIFOOVR (1 << 6)
80 80  
81   -static void lm_kbd_irq_update(struct lm_kbd_s *s)
  81 +static void lm_kbd_irq_update(LM823KbdState *s)
82 82 {
83 83 qemu_set_irq(s->nirq, !s->status);
84 84 }
85 85  
86   -static void lm_kbd_gpio_update(struct lm_kbd_s *s)
  86 +static void lm_kbd_gpio_update(LM823KbdState *s)
87 87 {
88 88 }
89 89  
90   -static void lm_kbd_reset(struct lm_kbd_s *s)
  90 +static void lm_kbd_reset(LM823KbdState *s)
91 91 {
92 92 s->config = 0x80;
93 93 s->status = INT_NOINIT;
... ... @@ -100,18 +100,18 @@ static void lm_kbd_reset(struct lm_kbd_s *s)
100 100 lm_kbd_gpio_update(s);
101 101 }
102 102  
103   -static void lm_kbd_error(struct lm_kbd_s *s, int err)
  103 +static void lm_kbd_error(LM823KbdState *s, int err)
104 104 {
105 105 s->error |= err;
106 106 s->status |= INT_ERROR;
107 107 lm_kbd_irq_update(s);
108 108 }
109 109  
110   -static void lm_kbd_pwm_tick(struct lm_kbd_s *s, int line)
  110 +static void lm_kbd_pwm_tick(LM823KbdState *s, int line)
111 111 {
112 112 }
113 113  
114   -static void lm_kbd_pwm_start(struct lm_kbd_s *s, int line)
  114 +static void lm_kbd_pwm_start(LM823KbdState *s, int line)
115 115 {
116 116 lm_kbd_pwm_tick(s, line);
117 117 }
... ... @@ -158,7 +158,7 @@ enum {
158 158 #define LM832x_MAX_KPX 8
159 159 #define LM832x_MAX_KPY 12
160 160  
161   -static uint8_t lm_kbd_read(struct lm_kbd_s *s, int reg, int byte)
  161 +static uint8_t lm_kbd_read(LM823KbdState *s, int reg, int byte)
162 162 {
163 163 int ret;
164 164  
... ... @@ -239,7 +239,7 @@ static uint8_t lm_kbd_read(struct lm_kbd_s *s, int reg, int byte)
239 239 return ret >> (byte << 3);
240 240 }
241 241  
242   -static void lm_kbd_write(struct lm_kbd_s *s, int reg, int byte, uint8_t value)
  242 +static void lm_kbd_write(LM823KbdState *s, int reg, int byte, uint8_t value)
243 243 {
244 244 switch (reg) {
245 245 case LM832x_CMD_WRITE_CFG:
... ... @@ -378,7 +378,7 @@ static void lm_kbd_write(struct lm_kbd_s *s, int reg, int byte, uint8_t value)
378 378  
379 379 static void lm_i2c_event(i2c_slave *i2c, enum i2c_event event)
380 380 {
381   - struct lm_kbd_s *s = (struct lm_kbd_s *) i2c;
  381 + LM823KbdState *s = (LM823KbdState *) i2c;
382 382  
383 383 switch (event) {
384 384 case I2C_START_RECV:
... ... @@ -394,14 +394,14 @@ static void lm_i2c_event(i2c_slave *i2c, enum i2c_event event)
394 394  
395 395 static int lm_i2c_rx(i2c_slave *i2c)
396 396 {
397   - struct lm_kbd_s *s = (struct lm_kbd_s *) i2c;
  397 + LM823KbdState *s = (LM823KbdState *) i2c;
398 398  
399 399 return lm_kbd_read(s, s->reg, s->i2c_cycle ++);
400 400 }
401 401  
402 402 static int lm_i2c_tx(i2c_slave *i2c, uint8_t data)
403 403 {
404   - struct lm_kbd_s *s = (struct lm_kbd_s *) i2c;
  404 + LM823KbdState *s = (LM823KbdState *) i2c;
405 405  
406 406 if (!s->i2c_cycle)
407 407 s->reg = data;
... ... @@ -414,7 +414,7 @@ static int lm_i2c_tx(i2c_slave *i2c, uint8_t data)
414 414  
415 415 static void lm_kbd_save(QEMUFile *f, void *opaque)
416 416 {
417   - struct lm_kbd_s *s = (struct lm_kbd_s *) opaque;
  417 + LM823KbdState *s = (LM823KbdState *) opaque;
418 418 int i;
419 419  
420 420 i2c_slave_save(f, &s->i2c);
... ... @@ -450,7 +450,7 @@ static void lm_kbd_save(QEMUFile *f, void *opaque)
450 450  
451 451 static int lm_kbd_load(QEMUFile *f, void *opaque, int version_id)
452 452 {
453   - struct lm_kbd_s *s = (struct lm_kbd_s *) opaque;
  453 + LM823KbdState *s = (LM823KbdState *) opaque;
454 454 int i;
455 455  
456 456 i2c_slave_load(f, &s->i2c);
... ... @@ -489,11 +489,11 @@ static int lm_kbd_load(QEMUFile *f, void *opaque, int version_id)
489 489 return 0;
490 490 }
491 491  
492   -struct i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq)
  492 +i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq)
493 493 {
494   - struct lm_kbd_s *s;
  494 + LM823KbdState *s;
495 495  
496   - s = (struct lm_kbd_s *) i2c_slave_init(bus, 0, sizeof(struct lm_kbd_s));
  496 + s = (LM823KbdState *) i2c_slave_init(bus, 0, sizeof(LM823KbdState));
497 497 s->model = 0x8323;
498 498 s->pwm.tm[0] = qemu_new_timer(vm_clock, lm_kbd_pwm0_tick, s);
499 499 s->pwm.tm[1] = qemu_new_timer(vm_clock, lm_kbd_pwm1_tick, s);
... ... @@ -514,7 +514,7 @@ struct i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq)
514 514  
515 515 void lm832x_key_event(struct i2c_slave *i2c, int key, int state)
516 516 {
517   - struct lm_kbd_s *s = (struct lm_kbd_s *) i2c;
  517 + LM823KbdState *s = (LM823KbdState *) i2c;
518 518  
519 519 if ((s->status & INT_ERROR) && (s->error & ERR_FIFOOVR))
520 520 return;
... ...
hw/mainstone.c
  View file @bc24a22
... ... @@ -75,7 +75,7 @@ static void mainstone_common_init(ram_addr_t ram_size, int vga_ram_size,
75 75 {
76 76 uint32_t sector_len = 256 * 1024;
77 77 target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
78   - struct pxa2xx_state_s *cpu;
  78 + PXA2xxState *cpu;
79 79 qemu_irq *mst_irq;
80 80 int i, index;
81 81  
... ...
hw/mainstone.h
  View file @bc24a22
... ... @@ -33,6 +33,6 @@
33 33 #define S1_IRQ 15
34 34  
35 35 extern qemu_irq
36   -*mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq);
  36 +*mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq);
37 37  
38 38 #endif /* __MAINSTONE_H__ */
... ...
hw/max111x.c
  View file @bc24a22
... ... @@ -10,7 +10,7 @@
10 10 #include "hw.h"
11 11 #include "i2c.h"
12 12  
13   -struct max111x_s {
  13 +struct MAX111xState {
14 14 qemu_irq interrupt;
15 15 uint8_t tb1, rb2, rb3;
16 16 int cycle;
... ... @@ -36,7 +36,7 @@ struct max111x_s {
36 36  
37 37 uint32_t max111x_read(void *opaque)
38 38 {
39   - struct max111x_s *s = (struct max111x_s *) opaque;
  39 + MAX111xState *s = (MAX111xState *) opaque;
40 40  
41 41 if (!s->tb1)
42 42 return 0;
... ... @@ -54,7 +54,7 @@ uint32_t max111x_read(void *opaque)
54 54 /* Interpret a control-byte */
55 55 void max111x_write(void *opaque, uint32_t value)
56 56 {
57   - struct max111x_s *s = (struct max111x_s *) opaque;
  57 + MAX111xState *s = (MAX111xState *) opaque;
58 58 int measure, chan;
59 59  
60 60 /* Ignore the value if START bit is zero */
... ... @@ -92,7 +92,7 @@ void max111x_write(void *opaque, uint32_t value)
92 92  
93 93 static void max111x_save(QEMUFile *f, void *opaque)
94 94 {
95   - struct max111x_s *s = (struct max111x_s *) opaque;
  95 + MAX111xState *s = (MAX111xState *) opaque;
96 96 int i;
97 97  
98 98 qemu_put_8s(f, &s->tb1);
... ... @@ -106,7 +106,7 @@ static void max111x_save(QEMUFile *f, void *opaque)
106 106  
107 107 static int max111x_load(QEMUFile *f, void *opaque, int version_id)
108 108 {
109   - struct max111x_s *s = (struct max111x_s *) opaque;
  109 + MAX111xState *s = (MAX111xState *) opaque;
110 110 int i;
111 111  
112 112 qemu_get_8s(f, &s->tb1);
... ... @@ -121,12 +121,12 @@ static int max111x_load(QEMUFile *f, void *opaque, int version_id)
121 121 return 0;
122 122 }
123 123  
124   -static struct max111x_s *max111x_init(qemu_irq cb)
  124 +static MAX111xState *max111x_init(qemu_irq cb)
125 125 {
126   - struct max111x_s *s;
127   - s = (struct max111x_s *)
128   - qemu_mallocz(sizeof(struct max111x_s));
129   - memset(s, 0, sizeof(struct max111x_s));
  126 + MAX111xState *s;
  127 + s = (MAX111xState *)
  128 + qemu_mallocz(sizeof(MAX111xState));
  129 + memset(s, 0, sizeof(MAX111xState));
130 130  
131 131 s->interrupt = cb;
132 132  
... ... @@ -146,21 +146,21 @@ static struct max111x_s *max111x_init(qemu_irq cb)
146 146 return s;
147 147 }
148 148  
149   -struct max111x_s *max1110_init(qemu_irq cb)
  149 +MAX111xState *max1110_init(qemu_irq cb)
150 150 {
151   - struct max111x_s *s = max111x_init(cb);
  151 + MAX111xState *s = max111x_init(cb);
152 152 s->inputs = 8;
153 153 return s;
154 154 }
155 155  
156   -struct max111x_s *max1111_init(qemu_irq cb)
  156 +MAX111xState *max1111_init(qemu_irq cb)
157 157 {
158   - struct max111x_s *s = max111x_init(cb);
  158 + MAX111xState *s = max111x_init(cb);
159 159 s->inputs = 4;
160 160 return s;
161 161 }
162 162  
163   -void max111x_set_input(struct max111x_s *s, int line, uint8_t value)
  163 +void max111x_set_input(MAX111xState *s, int line, uint8_t value)
164 164 {
165 165 if (line >= s->inputs) {
166 166 printf("%s: There's no input %i\n", __FUNCTION__, line);
... ...
hw/max7310.c
  View file @bc24a22
... ... @@ -10,7 +10,7 @@
10 10 #include "hw.h"
11 11 #include "i2c.h"
12 12  
13   -struct max7310_s {
  13 +typedef struct {
14 14 i2c_slave i2c;
15 15 int i2c_command_byte;
16 16 int len;
... ... @@ -22,11 +22,11 @@ struct max7310_s {
22 22 uint8_t command;
23 23 qemu_irq handler[8];
24 24 qemu_irq *gpio_in;
25   -};
  25 +} MAX7310State;
26 26  
27 27 void max7310_reset(i2c_slave *i2c)
28 28 {
29   - struct max7310_s *s = (struct max7310_s *) i2c;
  29 + MAX7310State *s = (MAX7310State *) i2c;
30 30 s->level &= s->direction;
31 31 s->direction = 0xff;
32 32 s->polarity = 0xf0;
... ... @@ -36,7 +36,7 @@ void max7310_reset(i2c_slave *i2c)
36 36  
37 37 static int max7310_rx(i2c_slave *i2c)
38 38 {
39   - struct max7310_s *s = (struct max7310_s *) i2c;
  39 + MAX7310State *s = (MAX7310State *) i2c;
40 40  
41 41 switch (s->command) {
42 42 case 0x00: /* Input port */
... ... @@ -71,7 +71,7 @@ static int max7310_rx(i2c_slave *i2c)
71 71  
72 72 static int max7310_tx(i2c_slave *i2c, uint8_t data)
73 73 {
74   - struct max7310_s *s = (struct max7310_s *) i2c;
  74 + MAX7310State *s = (MAX7310State *) i2c;
75 75 uint8_t diff;
76 76 int line;
77 77  
... ... @@ -126,7 +126,7 @@ static int max7310_tx(i2c_slave *i2c, uint8_t data)
126 126  
127 127 static void max7310_event(i2c_slave *i2c, enum i2c_event event)
128 128 {
129   - struct max7310_s *s = (struct max7310_s *) i2c;
  129 + MAX7310State *s = (MAX7310State *) i2c;
130 130 s->len = 0;
131 131  
132 132 switch (event) {
... ... @@ -146,7 +146,7 @@ static void max7310_event(i2c_slave *i2c, enum i2c_event event)
146 146  
147 147 static void max7310_save(QEMUFile *f, void *opaque)
148 148 {
149   - struct max7310_s *s = (struct max7310_s *) opaque;
  149 + MAX7310State *s = (MAX7310State *) opaque;
150 150  
151 151 qemu_put_be32(f, s->i2c_command_byte);
152 152 qemu_put_be32(f, s->len);
... ... @@ -162,7 +162,7 @@ static void max7310_save(QEMUFile *f, void *opaque)
162 162  
163 163 static int max7310_load(QEMUFile *f, void *opaque, int version_id)
164 164 {
165   - struct max7310_s *s = (struct max7310_s *) opaque;
  165 + MAX7310State *s = (MAX7310State *) opaque;
166 166  
167 167 s->i2c_command_byte = qemu_get_be32(f);
168 168 s->len = qemu_get_be32(f);
... ... @@ -179,7 +179,7 @@ static int max7310_load(QEMUFile *f, void *opaque, int version_id)
179 179  
180 180 static void max7310_gpio_set(void *opaque, int line, int level)
181 181 {
182   - struct max7310_s *s = (struct max7310_s *) opaque;
  182 + MAX7310State *s = (MAX7310State *) opaque;
183 183 if (line >= ARRAY_SIZE(s->handler) || line < 0)
184 184 hw_error("bad GPIO line");
185 185  
... ... @@ -191,10 +191,10 @@ static void max7310_gpio_set(void *opaque, int line, int level)
191 191  
192 192 /* MAX7310 is SMBus-compatible (can be used with only SMBus protocols),
193 193 * but also accepts sequences that are not SMBus so return an I2C device. */
194   -struct i2c_slave *max7310_init(i2c_bus *bus)
  194 +i2c_slave *max7310_init(i2c_bus *bus)
195 195 {
196   - struct max7310_s *s = (struct max7310_s *)
197   - i2c_slave_init(bus, 0, sizeof(struct max7310_s));
  196 + MAX7310State *s = (MAX7310State *)
  197 + i2c_slave_init(bus, 0, sizeof(MAX7310State));
198 198 s->i2c.event = max7310_event;
199 199 s->i2c.recv = max7310_rx;
200 200 s->i2c.send = max7310_tx;
... ... @@ -210,13 +210,13 @@ struct i2c_slave *max7310_init(i2c_bus *bus)
210 210  
211 211 qemu_irq *max7310_gpio_in_get(i2c_slave *i2c)
212 212 {
213   - struct max7310_s *s = (struct max7310_s *) i2c;
  213 + MAX7310State *s = (MAX7310State *) i2c;
214 214 return s->gpio_in;
215 215 }
216 216  
217 217 void max7310_gpio_out_set(i2c_slave *i2c, int line, qemu_irq handler)
218 218 {
219   - struct max7310_s *s = (struct max7310_s *) i2c;
  219 + MAX7310State *s = (MAX7310State *) i2c;
220 220 if (line >= ARRAY_SIZE(s->handler) || line < 0)
221 221 hw_error("bad GPIO line");
222 222  
... ...
hw/mst_fpga.c
  View file @bc24a22
... ... @@ -216,7 +216,7 @@ mst_fpga_load(QEMUFile *f, void *opaque, int version_id)
216 216 return 0;
217 217 }
218 218  
219   -qemu_irq *mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq)
  219 +qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq)
220 220 {
221 221 mst_irq_state *s;
222 222 int iomemtype;
... ...
hw/nand.c
  View file @bc24a22
... ... @@ -45,7 +45,7 @@
45 45 # define MAX_PAGE 0x800
46 46 # define MAX_OOB 0x40
47 47  
48   -struct nand_flash_s {
  48 +struct NANDFlashState {
49 49 uint8_t manf_id, chip_id;
50 50 int size, pages;
51 51 int page_shift, oob_shift, erase_shift, addr_shift;
... ... @@ -64,9 +64,9 @@ struct nand_flash_s {
64 64 int status;
65 65 int offset;
66 66  
67   - void (*blk_write)(struct nand_flash_s *s);
68   - void (*blk_erase)(struct nand_flash_s *s);
69   - void (*blk_load)(struct nand_flash_s *s, uint32_t addr, int offset);
  67 + void (*blk_write)(NANDFlashState *s);
  68 + void (*blk_erase)(NANDFlashState *s);
  69 + void (*blk_load)(NANDFlashState *s, uint32_t addr, int offset);
70 70 };
71 71  
72 72 # define NAND_NO_AUTOINCR 0x00000001
... ... @@ -106,7 +106,7 @@ struct nand_flash_s {
106 106 # include "nand.c"
107 107  
108 108 /* Information based on Linux drivers/mtd/nand/nand_ids.c */
109   -static const struct nand_info_s {
  109 +static const struct {
110 110 int size;
111 111 int width;
112 112 int page_shift;
... ... @@ -200,7 +200,7 @@ static const struct nand_info_s {
200 200 [0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
201 201 };
202 202  
203   -static void nand_reset(struct nand_flash_s *s)
  203 +static void nand_reset(NANDFlashState *s)
204 204 {
205 205 s->cmd = NAND_CMD_READ0;
206 206 s->addr = 0;
... ... @@ -210,7 +210,7 @@ static void nand_reset(struct nand_flash_s *s)
210 210 s->status &= NAND_IOSTATUS_UNPROTCT;
211 211 }
212 212  
213   -static void nand_command(struct nand_flash_s *s)
  213 +static void nand_command(NANDFlashState *s)
214 214 {
215 215 switch (s->cmd) {
216 216 case NAND_CMD_READ0:
... ... @@ -279,7 +279,7 @@ static void nand_command(struct nand_flash_s *s)
279 279  
280 280 static void nand_save(QEMUFile *f, void *opaque)
281 281 {
282   - struct nand_flash_s *s = (struct nand_flash_s *) opaque;
  282 + NANDFlashState *s = (NANDFlashState *) opaque;
283 283 qemu_put_byte(f, s->cle);
284 284 qemu_put_byte(f, s->ale);
285 285 qemu_put_byte(f, s->ce);
... ... @@ -299,7 +299,7 @@ static void nand_save(QEMUFile *f, void *opaque)
299 299  
300 300 static int nand_load(QEMUFile *f, void *opaque, int version_id)
301 301 {
302   - struct nand_flash_s *s = (struct nand_flash_s *) opaque;
  302 + NANDFlashState *s = (NANDFlashState *) opaque;
303 303 s->cle = qemu_get_byte(f);
304 304 s->ale = qemu_get_byte(f);
305 305 s->ce = qemu_get_byte(f);
... ... @@ -325,7 +325,7 @@ static int nand_load(QEMUFile *f, void *opaque, int version_id)
325 325 *
326 326 * CE, WP and R/B are active low.
327 327 */
328   -void nand_setpins(struct nand_flash_s *s,
  328 +void nand_setpins(NANDFlashState *s,
329 329 int cle, int ale, int ce, int wp, int gnd)
330 330 {
331 331 s->cle = cle;
... ... @@ -339,12 +339,12 @@ void nand_setpins(struct nand_flash_s *s,
339 339 s->status &= ~NAND_IOSTATUS_UNPROTCT;
340 340 }
341 341  
342   -void nand_getpins(struct nand_flash_s *s, int *rb)
  342 +void nand_getpins(NANDFlashState *s, int *rb)
343 343 {
344 344 *rb = 1;
345 345 }
346 346  
347   -void nand_setio(struct nand_flash_s *s, uint8_t value)
  347 +void nand_setio(NANDFlashState *s, uint8_t value)
348 348 {
349 349 if (!s->ce && s->cle) {
350 350 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
... ... @@ -415,7 +415,7 @@ void nand_setio(struct nand_flash_s *s, uint8_t value)
415 415 }
416 416 }
417 417  
418   -uint8_t nand_getio(struct nand_flash_s *s)
  418 +uint8_t nand_getio(NANDFlashState *s)
419 419 {
420 420 int offset;
421 421  
... ... @@ -438,17 +438,17 @@ uint8_t nand_getio(struct nand_flash_s *s)
438 438 return *(s->ioaddr ++);
439 439 }
440 440  
441   -struct nand_flash_s *nand_init(int manf_id, int chip_id)
  441 +NANDFlashState *nand_init(int manf_id, int chip_id)
442 442 {
443 443 int pagesize;
444   - struct nand_flash_s *s;
  444 + NANDFlashState *s;
445 445 int index;
446 446  
447 447 if (nand_flash_ids[chip_id].size == 0) {
448 448 hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
449 449 }
450 450  
451   - s = (struct nand_flash_s *) qemu_mallocz(sizeof(struct nand_flash_s));
  451 + s = (NANDFlashState *) qemu_mallocz(sizeof(NANDFlashState));
452 452 index = drive_get_index(IF_MTD, 0, 0);
453 453 if (index != -1)
454 454 s->bdrv = drives_table[index].bdrv;
... ... @@ -499,7 +499,7 @@ struct nand_flash_s *nand_init(int manf_id, int chip_id)
499 499 return s;
500 500 }
501 501  
502   -void nand_done(struct nand_flash_s *s)
  502 +void nand_done(NANDFlashState *s)
503 503 {
504 504 if (s->bdrv) {
505 505 bdrv_close(s->bdrv);
... ... @@ -515,7 +515,7 @@ void nand_done(struct nand_flash_s *s)
515 515 #else
516 516  
517 517 /* Program a single page */
518   -static void glue(nand_blk_write_, PAGE_SIZE)(struct nand_flash_s *s)
  518 +static void glue(nand_blk_write_, PAGE_SIZE)(NANDFlashState *s)
519 519 {
520 520 uint32_t off, page, sector, soff;
521 521 uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200];
... ... @@ -561,7 +561,7 @@ static void glue(nand_blk_write_, PAGE_SIZE)(struct nand_flash_s *s)
561 561 }
562 562  
563 563 /* Erase a single block */
564   -static void glue(nand_blk_erase_, PAGE_SIZE)(struct nand_flash_s *s)
  564 +static void glue(nand_blk_erase_, PAGE_SIZE)(NANDFlashState *s)
565 565 {
566 566 uint32_t i, page, addr;
567 567 uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, };
... ... @@ -606,7 +606,7 @@ static void glue(nand_blk_erase_, PAGE_SIZE)(struct nand_flash_s *s)
606 606 }
607 607 }
608 608  
609   -static void glue(nand_blk_load_, PAGE_SIZE)(struct nand_flash_s *s,
  609 +static void glue(nand_blk_load_, PAGE_SIZE)(NANDFlashState *s,
610 610 uint32_t addr, int offset)
611 611 {
612 612 if (PAGE(addr) >= s->pages)
... ... @@ -638,7 +638,7 @@ static void glue(nand_blk_load_, PAGE_SIZE)(struct nand_flash_s *s,
638 638 s->addr += PAGE_SIZE;
639 639 }
640 640  
641   -static void glue(nand_init_, PAGE_SIZE)(struct nand_flash_s *s)
  641 +static void glue(nand_init_, PAGE_SIZE)(NANDFlashState *s)
642 642 {
643 643 s->oob_shift = PAGE_SHIFT - 5;
644 644 s->pages = s->size >> PAGE_SHIFT;
... ...
hw/nseries.c
  View file @bc24a22
... ... @@ -40,14 +40,14 @@ struct n800_s {
40 40 struct {
41 41 void *opaque;
42 42 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
43   - struct uwire_slave_s *chip;
  43 + uWireSlave *chip;
44 44 } ts;
45 45 i2c_bus *i2c;
46 46  
47 47 int keymap[0x80];
48 48 i2c_slave *kbd;
49 49  
50   - struct tusb_s *usb;
  50 + TUSBState *usb;
51 51 void *retu;
52 52 void *tahvo;
53 53 void *nand;
... ... @@ -195,13 +195,13 @@ static void n8x0_i2c_setup(struct n800_s *s)
195 195 }
196 196  
197 197 /* Touchscreen and keypad controller */
198   -static struct mouse_transform_info_s n800_pointercal = {
  198 +static MouseTransformInfo n800_pointercal = {
199 199 .x = 800,
200 200 .y = 480,
201 201 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
202 202 };
203 203  
204   -static struct mouse_transform_info_s n810_pointercal = {
  204 +static MouseTransformInfo n810_pointercal = {
205 205 .x = 800,
206 206 .y = 480,
207 207 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
... ... @@ -729,7 +729,7 @@ static void n8x0_cbus_setup(struct n800_s *s)
729 729 qemu_irq retu_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_RETU_GPIO)[0];
730 730 qemu_irq tahvo_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TAHVO_GPIO)[0];
731 731  
732   - struct cbus_s *cbus = cbus_init(dat_out);
  732 + CBus *cbus = cbus_init(dat_out);
733 733  
734 734 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_CLK_GPIO, cbus->clk);
735 735 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_DAT_GPIO, cbus->dat);
... ... @@ -764,7 +764,7 @@ static void n8x0_usb_setup(struct n800_s *s)
764 764 {
765 765 qemu_irq tusb_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TUSB_INT_GPIO)[0];
766 766 qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];
767   - struct tusb_s *tusb = tusb6010_init(tusb_irq);
  767 + TUSBState *tusb = tusb6010_init(tusb_irq);
768 768  
769 769 /* Using the NOR interface */
770 770 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,
... ...
hw/omap.h
  View file @bc24a22
... ... @@ -681,7 +681,7 @@ struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
681 681 qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start);
682 682 void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler);
683 683  
684   -struct uwire_slave_s {
  684 +struct uWireSlave {
685 685 uint16_t (*receive)(void *opaque);
686 686 void (*send)(void *opaque, uint16_t data);
687 687 void *opaque;
... ... @@ -690,7 +690,7 @@ struct omap_uwire_s;
690 690 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
691 691 qemu_irq *irq, qemu_irq dma, omap_clk clk);
692 692 void omap_uwire_attach(struct omap_uwire_s *s,
693   - struct uwire_slave_s *slave, int chipselect);
  693 + uWireSlave *slave, int chipselect);
694 694  
695 695 struct omap_mcspi_s;
696 696 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
... ... @@ -703,7 +703,7 @@ struct omap_rtc_s;
703 703 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
704 704 qemu_irq *irq, omap_clk clk);
705 705  
706   -struct i2s_codec_s {
  706 +struct I2SCodec {
707 707 void *opaque;
708 708  
709 709 /* The CPU can call this if it is generating the clock signal on the
... ... @@ -730,7 +730,7 @@ struct i2s_codec_s {
730 730 struct omap_mcbsp_s;
731 731 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
732 732 qemu_irq *irq, qemu_irq *dma, omap_clk clk);
733   -void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);
  733 +void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
734 734  
735 735 struct omap_lpg_s;
736 736 struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
... ...
hw/omap1.c
  View file @bc24a22
... ... @@ -2984,13 +2984,13 @@ struct omap_uwire_s {
2984 2984 uint16_t control;
2985 2985 uint16_t setup[5];
2986 2986  
2987   - struct uwire_slave_s *chip[4];
  2987 + uWireSlave *chip[4];
2988 2988 };
2989 2989  
2990 2990 static void omap_uwire_transfer_start(struct omap_uwire_s *s)
2991 2991 {
2992 2992 int chipselect = (s->control >> 10) & 3; /* INDEX */
2993   - struct uwire_slave_s *slave = s->chip[chipselect];
  2993 + uWireSlave *slave = s->chip[chipselect];
2994 2994  
2995 2995 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
2996 2996 if (s->control & (1 << 12)) /* CS_CMD */
... ... @@ -3132,7 +3132,7 @@ struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
3132 3132 }
3133 3133  
3134 3134 void omap_uwire_attach(struct omap_uwire_s *s,
3135   - struct uwire_slave_s *slave, int chipselect)
  3135 + uWireSlave *slave, int chipselect)
3136 3136 {
3137 3137 if (chipselect < 0 || chipselect > 3) {
3138 3138 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
... ... @@ -3770,7 +3770,7 @@ struct omap_mcbsp_s {
3770 3770 int tx_req;
3771 3771 int rx_req;
3772 3772  
3773   - struct i2s_codec_s *codec;
  3773 + I2SCodec *codec;
3774 3774 QEMUTimer *source_timer;
3775 3775 QEMUTimer *sink_timer;
3776 3776 };
... ... @@ -4290,7 +4290,7 @@ static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
4290 4290 }
4291 4291 }
4292 4292  
4293   -void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave)
  4293 +void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave)
4294 4294 {
4295 4295 s->codec = slave;
4296 4296 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0];
... ...
hw/omap2.c
  View file @bc24a22
... ... @@ -4068,7 +4068,7 @@ struct omap_gpmc_s {
4068 4068 int ecc_cs;
4069 4069 int ecc_ptr;
4070 4070 uint32_t ecc_cfg;
4071   - struct ecc_state_s ecc[9];
  4071 + ECCState ecc[9];
4072 4072 };
4073 4073  
4074 4074 static void omap_gpmc_int_update(struct omap_gpmc_s *s)
... ...
hw/omap_mmc.c
  View file @bc24a22
... ... @@ -112,7 +112,7 @@ static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
112 112 {
113 113 uint32_t rspstatus, mask;
114 114 int rsplen, timeout;
115   - struct sd_request_s request;
  115 + SDRequest request;
116 116 uint8_t response[16];
117 117  
118 118 if (init && cmd == 0) {
... ...
hw/onenand.c
  View file @bc24a22
... ... @@ -31,7 +31,7 @@
31 31 /* Fixed */
32 32 #define BLOCK_SHIFT (PAGE_SHIFT + 6)
33 33  
34   -struct onenand_s {
  34 +typedef struct {
35 35 uint32_t id;
36 36 int shift;
37 37 target_phys_addr_t base;
... ... @@ -59,14 +59,14 @@ struct onenand_s {
59 59 uint16_t intstatus;
60 60 uint16_t wpstatus;
61 61  
62   - struct ecc_state_s ecc;
  62 + ECCState ecc;
63 63  
64 64 int density_mask;
65 65 int secs;
66 66 int secs_cur;
67 67 int blocks;
68 68 uint8_t *blockwp;
69   -};
  69 +} OneNANDState;
70 70  
71 71 enum {
72 72 ONEN_BUF_BLOCK = 0,
... ... @@ -99,7 +99,7 @@ enum {
99 99  
100 100 void onenand_base_update(void *opaque, target_phys_addr_t new)
101 101 {
102   - struct onenand_s *s = (struct onenand_s *) opaque;
  102 + OneNANDState *s = (OneNANDState *) opaque;
103 103  
104 104 s->base = new;
105 105  
... ... @@ -118,19 +118,19 @@ void onenand_base_update(void *opaque, target_phys_addr_t new)
118 118  
119 119 void onenand_base_unmap(void *opaque)
120 120 {
121   - struct onenand_s *s = (struct onenand_s *) opaque;
  121 + OneNANDState *s = (OneNANDState *) opaque;
122 122  
123 123 cpu_register_physical_memory(s->base,
124 124 0x10000 << s->shift, IO_MEM_UNASSIGNED);
125 125 }
126 126  
127   -static void onenand_intr_update(struct onenand_s *s)
  127 +static void onenand_intr_update(OneNANDState *s)
128 128 {
129 129 qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1);
130 130 }
131 131  
132 132 /* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
133   -static void onenand_reset(struct onenand_s *s, int cold)
  133 +static void onenand_reset(OneNANDState *s, int cold)
134 134 {
135 135 memset(&s->addr, 0, sizeof(s->addr));
136 136 s->command = 0;
... ... @@ -160,7 +160,7 @@ static void onenand_reset(struct onenand_s *s, int cold)
160 160 }
161 161 }
162 162  
163   -static inline int onenand_load_main(struct onenand_s *s, int sec, int secn,
  163 +static inline int onenand_load_main(OneNANDState *s, int sec, int secn,
164 164 void *dest)
165 165 {
166 166 if (s->bdrv_cur)
... ... @@ -173,7 +173,7 @@ static inline int onenand_load_main(struct onenand_s *s, int sec, int secn,
173 173 return 0;
174 174 }
175 175  
176   -static inline int onenand_prog_main(struct onenand_s *s, int sec, int secn,
  176 +static inline int onenand_prog_main(OneNANDState *s, int sec, int secn,
177 177 void *src)
178 178 {
179 179 if (s->bdrv_cur)
... ... @@ -186,7 +186,7 @@ static inline int onenand_prog_main(struct onenand_s *s, int sec, int secn,
186 186 return 0;
187 187 }
188 188  
189   -static inline int onenand_load_spare(struct onenand_s *s, int sec, int secn,
  189 +static inline int onenand_load_spare(OneNANDState *s, int sec, int secn,
190 190 void *dest)
191 191 {
192 192 uint8_t buf[512];
... ... @@ -203,7 +203,7 @@ static inline int onenand_load_spare(struct onenand_s *s, int sec, int secn,
203 203 return 0;
204 204 }
205 205  
206   -static inline int onenand_prog_spare(struct onenand_s *s, int sec, int secn,
  206 +static inline int onenand_prog_spare(OneNANDState *s, int sec, int secn,
207 207 void *src)
208 208 {
209 209 uint8_t buf[512];
... ... @@ -221,7 +221,7 @@ static inline int onenand_prog_spare(struct onenand_s *s, int sec, int secn,
221 221 return 0;
222 222 }
223 223  
224   -static inline int onenand_erase(struct onenand_s *s, int sec, int num)
  224 +static inline int onenand_erase(OneNANDState *s, int sec, int num)
225 225 {
226 226 /* TODO: optimise */
227 227 uint8_t buf[512];
... ... @@ -237,7 +237,7 @@ static inline int onenand_erase(struct onenand_s *s, int sec, int num)
237 237 return 0;
238 238 }
239 239  
240   -static void onenand_command(struct onenand_s *s, int cmd)
  240 +static void onenand_command(OneNANDState *s, int cmd)
241 241 {
242 242 int b;
243 243 int sec;
... ... @@ -446,7 +446,7 @@ static void onenand_command(struct onenand_s *s, int cmd)
446 446  
447 447 static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
448 448 {
449   - struct onenand_s *s = (struct onenand_s *) opaque;
  449 + OneNANDState *s = (OneNANDState *) opaque;
450 450 int offset = addr >> s->shift;
451 451  
452 452 switch (offset) {
... ... @@ -511,7 +511,7 @@ static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
511 511 static void onenand_write(void *opaque, target_phys_addr_t addr,
512 512 uint32_t value)
513 513 {
514   - struct onenand_s *s = (struct onenand_s *) opaque;
  514 + OneNANDState *s = (OneNANDState *) opaque;
515 515 int offset = addr >> s->shift;
516 516 int sec;
517 517  
... ... @@ -618,7 +618,7 @@ static CPUWriteMemoryFunc *onenand_writefn[] = {
618 618  
619 619 void *onenand_init(uint32_t id, int regshift, qemu_irq irq)
620 620 {
621   - struct onenand_s *s = (struct onenand_s *) qemu_mallocz(sizeof(*s));
  621 + OneNANDState *s = (OneNANDState *) qemu_mallocz(sizeof(*s));
622 622 int bdrv_index = drive_get_index(IF_MTD, 0, 0);
623 623 uint32_t size = 1 << (24 + ((id >> 12) & 7));
624 624 void *ram;
... ... @@ -656,7 +656,7 @@ void *onenand_init(uint32_t id, int regshift, qemu_irq irq)
656 656  
657 657 void *onenand_raw_otp(void *opaque)
658 658 {
659   - struct onenand_s *s = (struct onenand_s *) opaque;
  659 + OneNANDState *s = (OneNANDState *) opaque;
660 660  
661 661 return s->otp;
662 662 }
... ...
hw/palm.c
  View file @bc24a22
... ... @@ -84,7 +84,7 @@ static CPUWriteMemoryFunc *static_writefn[] = {
84 84 #define PALMTE_MMC2_GPIO 7
85 85 #define PALMTE_MMC3_GPIO 11
86 86  
87   -static struct mouse_transform_info_s palmte_pointercal = {
  87 +static MouseTransformInfo palmte_pointercal = {
88 88 .x = 320,
89 89 .y = 320,
90 90 .a = { -5909, 8, 22465308, 104, 7644, -1219972, 65536 },
... ... @@ -92,7 +92,7 @@ static struct mouse_transform_info_s palmte_pointercal = {
92 92  
93 93 static void palmte_microwire_setup(struct omap_mpu_state_s *cpu)
94 94 {
95   - struct uwire_slave_s *tsc;
  95 + uWireSlave *tsc;
96 96 AudioState *audio = 0;
97 97  
98 98 #ifdef HAS_AUDIO
... ...
hw/pcmcia.h
  View file @bc24a22
... ... @@ -2,20 +2,20 @@
2 2  
3 3 #include "qemu-common.h"
4 4  
5   -struct pcmcia_socket_s {
  5 +typedef struct {
6 6 qemu_irq irq;
7 7 int attached;
8 8 const char *slot_string;
9 9 const char *card_string;
10   -};
  10 +} PCMCIASocket;
11 11  
12   -void pcmcia_socket_register(struct pcmcia_socket_s *socket);
13   -void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
  12 +void pcmcia_socket_register(PCMCIASocket *socket);
  13 +void pcmcia_socket_unregister(PCMCIASocket *socket);
14 14 void pcmcia_info(Monitor *mon);
15 15  
16   -struct pcmcia_card_s {
  16 +struct PCMCIACardState {
17 17 void *state;
18   - struct pcmcia_socket_s *slot;
  18 + PCMCIASocket *slot;
19 19 int (*attach)(void *state);
20 20 int (*detach)(void *state);
21 21 const uint8_t *cis;
... ... @@ -48,4 +48,4 @@ struct pcmcia_card_s {
48 48 #define CISTPL_ENDMARK 0xff
49 49  
50 50 /* dscm1xxxx.c */
51   -struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
  51 +PCMCIACardState *dscm1xxxx_init(BlockDriverState *bdrv);
... ...
hw/pl181.c
  View file @bc24a22
... ... @@ -135,7 +135,7 @@ static uint32_t pl181_fifo_pop(pl181_state *s)
135 135  
136 136 static void pl181_send_command(pl181_state *s)
137 137 {
138   - struct sd_request_s request;
  138 + SDRequest request;
139 139 uint8_t response[16];
140 140 int rlen;
141 141  
... ...
hw/pxa.h
  View file @bc24a22
... ... @@ -70,40 +70,40 @@ void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
70 70 void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
71 71  
72 72 /* pxa2xx_gpio.c */
73   -struct pxa2xx_gpio_info_s;
74   -struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
  73 +typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
  74 +PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base,
75 75 CPUState *env, qemu_irq *pic, int lines);
76   -qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s);
77   -void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s,
  76 +qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s);
  77 +void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s,
78 78 int line, qemu_irq handler);
79   -void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler);
  79 +void pxa2xx_gpio_read_notifier(PXA2xxGPIOInfo *s, qemu_irq handler);
80 80  
81 81 /* pxa2xx_dma.c */
82   -struct pxa2xx_dma_state_s;
83   -struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
  82 +typedef struct PXA2xxDMAState PXA2xxDMAState;
  83 +PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
84 84 qemu_irq irq);
85   -struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
  85 +PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
86 86 qemu_irq irq);
87   -void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on);
  87 +void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on);
88 88  
89 89 /* pxa2xx_lcd.c */
90   -struct pxa2xx_lcdc_s;
91   -struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
  90 +typedef struct PXA2xxLCDState PXA2xxLCDState;
  91 +PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
92 92 qemu_irq irq);
93   -void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler);
  93 +void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
94 94 void pxa2xx_lcdc_oritentation(void *opaque, int angle);
95 95  
96 96 /* pxa2xx_mmci.c */
97   -struct pxa2xx_mmci_s;
98   -struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
  97 +typedef struct PXA2xxMMCIState PXA2xxMMCIState;
  98 +PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
99 99 BlockDriverState *bd, qemu_irq irq, void *dma);
100   -void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly,
  100 +void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
101 101 qemu_irq coverswitch);
102 102  
103 103 /* pxa2xx_pcmcia.c */
104   -struct pxa2xx_pcmcia_s;
105   -struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base);
106   -int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card);
  104 +typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
  105 +PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
  106 +int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
107 107 int pxa2xx_pcmcia_dettach(void *opaque);
108 108 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
109 109  
... ... @@ -112,40 +112,40 @@ struct keymap {
112 112 int column;
113 113 int row;
114 114 };
115   -struct pxa2xx_keypad_s;
116   -struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base,
  115 +typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
  116 +PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
117 117 qemu_irq irq);
118   -void pxa27x_register_keypad(struct pxa2xx_keypad_s *kp, struct keymap *map,
  118 +void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
119 119 int size);
120 120  
121 121 /* pxa2xx.c */
122   -struct pxa2xx_ssp_s;
123   -void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
  122 +typedef struct PXA2xxSSPState PXA2xxSSPState;
  123 +void pxa2xx_ssp_attach(PXA2xxSSPState *port,
124 124 uint32_t (*readfn)(void *opaque),
125 125 void (*writefn)(void *opaque, uint32_t value), void *opaque);
126 126  
127   -struct pxa2xx_i2c_s;
128   -struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
  127 +typedef struct PXA2xxI2CState PXA2xxI2CState;
  128 +PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
129 129 qemu_irq irq, uint32_t page_size);
130   -i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s);
  130 +i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
131 131  
132   -struct pxa2xx_i2s_s;
133   -struct pxa2xx_fir_s;
  132 +typedef struct PXA2xxI2SState PXA2xxI2SState;
  133 +typedef struct PXA2xxFIrState PXA2xxFIrState;
134 134  
135   -struct pxa2xx_state_s {
  135 +typedef struct {
136 136 CPUState *env;
137 137 qemu_irq *pic;
138 138 qemu_irq reset;
139   - struct pxa2xx_dma_state_s *dma;
140   - struct pxa2xx_gpio_info_s *gpio;
141   - struct pxa2xx_lcdc_s *lcd;
142   - struct pxa2xx_ssp_s **ssp;
143   - struct pxa2xx_i2c_s *i2c[2];
144   - struct pxa2xx_mmci_s *mmc;
145   - struct pxa2xx_pcmcia_s *pcmcia[2];
146   - struct pxa2xx_i2s_s *i2s;
147   - struct pxa2xx_fir_s *fir;
148   - struct pxa2xx_keypad_s *kp;
  139 + PXA2xxDMAState *dma;
  140 + PXA2xxGPIOInfo *gpio;
  141 + PXA2xxLCDState *lcd;
  142 + PXA2xxSSPState **ssp;
  143 + PXA2xxI2CState *i2c[2];
  144 + PXA2xxMMCIState *mmc;
  145 + PXA2xxPCMCIAState *pcmcia[2];
  146 + PXA2xxI2SState *i2s;
  147 + PXA2xxFIrState *fir;
  148 + PXA2xxKeyPadState *kp;
149 149  
150 150 /* Power management */
151 151 target_phys_addr_t pm_base;
... ... @@ -189,11 +189,11 @@ struct pxa2xx_state_s {
189 189 QEMUTimer *rtc_swal1;
190 190 QEMUTimer *rtc_swal2;
191 191 QEMUTimer *rtc_pi;
192   -};
  192 +} PXA2xxState;
193 193  
194   -struct pxa2xx_i2s_s {
  194 +struct PXA2xxI2SState {
195 195 qemu_irq irq;
196   - struct pxa2xx_dma_state_s *dma;
  196 + PXA2xxDMAState *dma;
197 197 void (*data_req)(void *, int, int);
198 198  
199 199 uint32_t control[2];
... ... @@ -215,8 +215,8 @@ struct pxa2xx_i2s_s {
215 215 # define PA_FMT "0x%08lx"
216 216 # define REG_FMT "0x" TARGET_FMT_plx
217 217  
218   -struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision);
219   -struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size);
  218 +PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
  219 +PXA2xxState *pxa255_init(unsigned int sdram_size);
220 220  
221 221 /* usb-ohci.c */
222 222 void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
... ...
hw/pxa2xx.c
  View file @bc24a22
... ... @@ -89,7 +89,7 @@ static PXASSPDef pxa27x_ssp[] = {
89 89  
90 90 static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
91 91 {
92   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  92 + PXA2xxState *s = (PXA2xxState *) opaque;
93 93  
94 94 switch (addr) {
95 95 case PMCR ... PCMD31:
... ... @@ -108,7 +108,7 @@ static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
108 108 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
109 109 uint32_t value)
110 110 {
111   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  111 + PXA2xxState *s = (PXA2xxState *) opaque;
112 112  
113 113 switch (addr) {
114 114 case PMCR:
... ... @@ -147,7 +147,7 @@ static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {
147 147  
148 148 static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
149 149 {
150   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  150 + PXA2xxState *s = (PXA2xxState *) opaque;
151 151 int i;
152 152  
153 153 for (i = 0; i < 0x40; i ++)
... ... @@ -156,7 +156,7 @@ static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
156 156  
157 157 static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
158 158 {
159   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  159 + PXA2xxState *s = (PXA2xxState *) opaque;
160 160 int i;
161 161  
162 162 for (i = 0; i < 0x40; i ++)
... ... @@ -172,7 +172,7 @@ static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
172 172  
173 173 static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
174 174 {
175   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  175 + PXA2xxState *s = (PXA2xxState *) opaque;
176 176  
177 177 switch (addr) {
178 178 case CCCR:
... ... @@ -193,7 +193,7 @@ static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
193 193 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
194 194 uint32_t value)
195 195 {
196   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  196 + PXA2xxState *s = (PXA2xxState *) opaque;
197 197  
198 198 switch (addr) {
199 199 case CCCR:
... ... @@ -228,7 +228,7 @@ static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {
228 228  
229 229 static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
230 230 {
231   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  231 + PXA2xxState *s = (PXA2xxState *) opaque;
232 232 int i;
233 233  
234 234 for (i = 0; i < 4; i ++)
... ... @@ -239,7 +239,7 @@ static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
239 239  
240 240 static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
241 241 {
242   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  242 + PXA2xxState *s = (PXA2xxState *) opaque;
243 243 int i;
244 244  
245 245 for (i = 0; i < 4; i ++)
... ... @@ -252,7 +252,7 @@ static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
252 252  
253 253 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
254 254 {
255   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  255 + PXA2xxState *s = (PXA2xxState *) opaque;
256 256  
257 257 switch (reg) {
258 258 case 6: /* Clock Configuration register */
... ... @@ -271,7 +271,7 @@ static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
271 271 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
272 272 uint32_t value)
273 273 {
274   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  274 + PXA2xxState *s = (PXA2xxState *) opaque;
275 275 static const char *pwrmode[8] = {
276 276 "Normal", "Idle", "Deep-idle", "Standby",
277 277 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
... ... @@ -364,7 +364,7 @@ static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
364 364  
365 365 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
366 366 {
367   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  367 + PXA2xxState *s = (PXA2xxState *) opaque;
368 368  
369 369 switch (reg) {
370 370 case CPPMNC:
... ... @@ -389,7 +389,7 @@ static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
389 389 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
390 390 uint32_t value)
391 391 {
392   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  392 + PXA2xxState *s = (PXA2xxState *) opaque;
393 393  
394 394 switch (reg) {
395 395 case CPPMNC:
... ... @@ -482,7 +482,7 @@ static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
482 482  
483 483 static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
484 484 {
485   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  485 + PXA2xxState *s = (PXA2xxState *) opaque;
486 486  
487 487 switch (addr) {
488 488 case MDCNFG ... SA1110:
... ... @@ -499,7 +499,7 @@ static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
499 499 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
500 500 uint32_t value)
501 501 {
502   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  502 + PXA2xxState *s = (PXA2xxState *) opaque;
503 503  
504 504 switch (addr) {
505 505 case MDCNFG ... SA1110:
... ... @@ -528,7 +528,7 @@ static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {
528 528  
529 529 static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
530 530 {
531   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  531 + PXA2xxState *s = (PXA2xxState *) opaque;
532 532 int i;
533 533  
534 534 for (i = 0; i < 0x1a; i ++)
... ... @@ -537,7 +537,7 @@ static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
537 537  
538 538 static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
539 539 {
540   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  540 + PXA2xxState *s = (PXA2xxState *) opaque;
541 541 int i;
542 542  
543 543 for (i = 0; i < 0x1a; i ++)
... ... @@ -547,7 +547,7 @@ static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
547 547 }
548 548  
549 549 /* Synchronous Serial Ports */
550   -struct pxa2xx_ssp_s {
  550 +struct PXA2xxSSPState {
551 551 qemu_irq irq;
552 552 int enable;
553 553  
... ... @@ -616,7 +616,7 @@ struct pxa2xx_ssp_s {
616 616 #define SSSR_BCE (1 << 23)
617 617 #define SSSR_RW 0x00bc0080
618 618  
619   -static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s)
  619 +static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
620 620 {
621 621 int level = 0;
622 622  
... ... @@ -632,7 +632,7 @@ static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s)
632 632 qemu_set_irq(s->irq, !!level);
633 633 }
634 634  
635   -static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s)
  635 +static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
636 636 {
637 637 s->sssr &= ~(0xf << 12); /* Clear RFL */
638 638 s->sssr &= ~(0xf << 8); /* Clear TFL */
... ... @@ -659,7 +659,7 @@ static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s)
659 659  
660 660 static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
661 661 {
662   - struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
  662 + PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
663 663 uint32_t retval;
664 664  
665 665 switch (addr) {
... ... @@ -705,7 +705,7 @@ static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
705 705 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
706 706 uint32_t value)
707 707 {
708   - struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
  708 + PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
709 709  
710 710 switch (addr) {
711 711 case SSCR0:
... ... @@ -796,7 +796,7 @@ static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
796 796 }
797 797 }
798 798  
799   -void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
  799 +void pxa2xx_ssp_attach(PXA2xxSSPState *port,
800 800 uint32_t (*readfn)(void *opaque),
801 801 void (*writefn)(void *opaque, uint32_t value), void *opaque)
802 802 {
... ... @@ -824,7 +824,7 @@ static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {
824 824  
825 825 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
826 826 {
827   - struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
  827 + PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
828 828 int i;
829 829  
830 830 qemu_put_be32(f, s->enable);
... ... @@ -846,7 +846,7 @@ static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
846 846  
847 847 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
848 848 {
849   - struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
  849 + PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
850 850 int i;
851 851  
852 852 s->enable = qemu_get_be32(f);
... ... @@ -886,12 +886,12 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
886 886 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
887 887 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
888 888  
889   -static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s)
  889 +static inline void pxa2xx_rtc_int_update(PXA2xxState *s)
890 890 {
891 891 qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
892 892 }
893 893  
894   -static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s)
  894 +static void pxa2xx_rtc_hzupdate(PXA2xxState *s)
895 895 {
896 896 int64_t rt = qemu_get_clock(rt_clock);
897 897 s->last_rcnr += ((rt - s->last_hz) << 15) /
... ... @@ -901,7 +901,7 @@ static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s)
901 901 s->last_hz = rt;
902 902 }
903 903  
904   -static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s)
  904 +static void pxa2xx_rtc_swupdate(PXA2xxState *s)
905 905 {
906 906 int64_t rt = qemu_get_clock(rt_clock);
907 907 if (s->rtsr & (1 << 12))
... ... @@ -909,7 +909,7 @@ static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s)
909 909 s->last_sw = rt;
910 910 }
911 911  
912   -static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s)
  912 +static void pxa2xx_rtc_piupdate(PXA2xxState *s)
913 913 {
914 914 int64_t rt = qemu_get_clock(rt_clock);
915 915 if (s->rtsr & (1 << 15))
... ... @@ -917,7 +917,7 @@ static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s)
917 917 s->last_pi = rt;
918 918 }
919 919  
920   -static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s,
  920 +static inline void pxa2xx_rtc_alarm_update(PXA2xxState *s,
921 921 uint32_t rtsr)
922 922 {
923 923 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
... ... @@ -962,7 +962,7 @@ static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s,
962 962  
963 963 static inline void pxa2xx_rtc_hz_tick(void *opaque)
964 964 {
965   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  965 + PXA2xxState *s = (PXA2xxState *) opaque;
966 966 s->rtsr |= (1 << 0);
967 967 pxa2xx_rtc_alarm_update(s, s->rtsr);
968 968 pxa2xx_rtc_int_update(s);
... ... @@ -970,7 +970,7 @@ static inline void pxa2xx_rtc_hz_tick(void *opaque)
970 970  
971 971 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
972 972 {
973   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  973 + PXA2xxState *s = (PXA2xxState *) opaque;
974 974 s->rtsr |= (1 << 4);
975 975 pxa2xx_rtc_alarm_update(s, s->rtsr);
976 976 pxa2xx_rtc_int_update(s);
... ... @@ -978,7 +978,7 @@ static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
978 978  
979 979 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
980 980 {
981   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  981 + PXA2xxState *s = (PXA2xxState *) opaque;
982 982 s->rtsr |= (1 << 6);
983 983 pxa2xx_rtc_alarm_update(s, s->rtsr);
984 984 pxa2xx_rtc_int_update(s);
... ... @@ -986,7 +986,7 @@ static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
986 986  
987 987 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
988 988 {
989   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  989 + PXA2xxState *s = (PXA2xxState *) opaque;
990 990 s->rtsr |= (1 << 8);
991 991 pxa2xx_rtc_alarm_update(s, s->rtsr);
992 992 pxa2xx_rtc_int_update(s);
... ... @@ -994,7 +994,7 @@ static inline void pxa2xx_rtc_swal1_tick(void *opaque)
994 994  
995 995 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
996 996 {
997   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  997 + PXA2xxState *s = (PXA2xxState *) opaque;
998 998 s->rtsr |= (1 << 10);
999 999 pxa2xx_rtc_alarm_update(s, s->rtsr);
1000 1000 pxa2xx_rtc_int_update(s);
... ... @@ -1002,7 +1002,7 @@ static inline void pxa2xx_rtc_swal2_tick(void *opaque)
1002 1002  
1003 1003 static inline void pxa2xx_rtc_pi_tick(void *opaque)
1004 1004 {
1005   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  1005 + PXA2xxState *s = (PXA2xxState *) opaque;
1006 1006 s->rtsr |= (1 << 13);
1007 1007 pxa2xx_rtc_piupdate(s);
1008 1008 s->last_rtcpicr = 0;
... ... @@ -1012,7 +1012,7 @@ static inline void pxa2xx_rtc_pi_tick(void *opaque)
1012 1012  
1013 1013 static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1014 1014 {
1015   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  1015 + PXA2xxState *s = (PXA2xxState *) opaque;
1016 1016  
1017 1017 switch (addr) {
1018 1018 case RTTR:
... ... @@ -1058,7 +1058,7 @@ static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1058 1058 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1059 1059 uint32_t value)
1060 1060 {
1061   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  1061 + PXA2xxState *s = (PXA2xxState *) opaque;
1062 1062  
1063 1063 switch (addr) {
1064 1064 case RTTR:
... ... @@ -1170,7 +1170,7 @@ static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
1170 1170 pxa2xx_rtc_write,
1171 1171 };
1172 1172  
1173   -static void pxa2xx_rtc_init(struct pxa2xx_state_s *s)
  1173 +static void pxa2xx_rtc_init(PXA2xxState *s)
1174 1174 {
1175 1175 struct tm tm;
1176 1176 int wom;
... ... @@ -1201,7 +1201,7 @@ static void pxa2xx_rtc_init(struct pxa2xx_state_s *s)
1201 1201  
1202 1202 static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
1203 1203 {
1204   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  1204 + PXA2xxState *s = (PXA2xxState *) opaque;
1205 1205  
1206 1206 pxa2xx_rtc_hzupdate(s);
1207 1207 pxa2xx_rtc_piupdate(s);
... ... @@ -1229,7 +1229,7 @@ static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
1229 1229  
1230 1230 static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
1231 1231 {
1232   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  1232 + PXA2xxState *s = (PXA2xxState *) opaque;
1233 1233  
1234 1234 qemu_get_be32s(f, &s->rttr);
1235 1235 qemu_get_be32s(f, &s->rtsr);
... ... @@ -1256,7 +1256,7 @@ static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
1256 1256 }
1257 1257  
1258 1258 /* I2C Interface */
1259   -struct pxa2xx_i2c_s {
  1259 +struct PXA2xxI2CState {
1260 1260 i2c_slave slave;
1261 1261 i2c_bus *bus;
1262 1262 qemu_irq irq;
... ... @@ -1274,7 +1274,7 @@ struct pxa2xx_i2c_s {
1274 1274 #define ISR 0x98 /* I2C Status register */
1275 1275 #define ISAR 0xa0 /* I2C Slave Address register */
1276 1276  
1277   -static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s)
  1277 +static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1278 1278 {
1279 1279 uint16_t level = 0;
1280 1280 level |= s->status & s->control & (1 << 10); /* BED */
... ... @@ -1287,7 +1287,7 @@ static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s)
1287 1287 /* These are only stubs now. */
1288 1288 static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1289 1289 {
1290   - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
  1290 + PXA2xxI2CState *s = (PXA2xxI2CState *) i2c;
1291 1291  
1292 1292 switch (event) {
1293 1293 case I2C_START_SEND:
... ... @@ -1310,7 +1310,7 @@ static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1310 1310  
1311 1311 static int pxa2xx_i2c_rx(i2c_slave *i2c)
1312 1312 {
1313   - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
  1313 + PXA2xxI2CState *s = (PXA2xxI2CState *) i2c;
1314 1314 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1315 1315 return 0;
1316 1316  
... ... @@ -1324,7 +1324,7 @@ static int pxa2xx_i2c_rx(i2c_slave *i2c)
1324 1324  
1325 1325 static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1326 1326 {
1327   - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
  1327 + PXA2xxI2CState *s = (PXA2xxI2CState *) i2c;
1328 1328 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1329 1329 return 1;
1330 1330  
... ... @@ -1339,7 +1339,7 @@ static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1339 1339  
1340 1340 static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1341 1341 {
1342   - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
  1342 + PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1343 1343  
1344 1344 addr -= s->offset;
1345 1345 switch (addr) {
... ... @@ -1367,7 +1367,7 @@ static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1367 1367 static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1368 1368 uint32_t value)
1369 1369 {
1370   - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
  1370 + PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1371 1371 int ack;
1372 1372  
1373 1373 addr -= s->offset;
... ... @@ -1448,7 +1448,7 @@ static CPUWriteMemoryFunc *pxa2xx_i2c_writefn[] = {
1448 1448  
1449 1449 static void pxa2xx_i2c_save(QEMUFile *f, void *opaque)
1450 1450 {
1451   - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
  1451 + PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1452 1452  
1453 1453 qemu_put_be16s(f, &s->control);
1454 1454 qemu_put_be16s(f, &s->status);
... ... @@ -1460,7 +1460,7 @@ static void pxa2xx_i2c_save(QEMUFile *f, void *opaque)
1460 1460  
1461 1461 static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
1462 1462 {
1463   - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
  1463 + PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1464 1464  
1465 1465 if (version_id != 1)
1466 1466 return -EINVAL;
... ... @@ -1474,13 +1474,13 @@ static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
1474 1474 return 0;
1475 1475 }
1476 1476  
1477   -struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
  1477 +PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
1478 1478 qemu_irq irq, uint32_t region_size)
1479 1479 {
1480 1480 int iomemtype;
1481 1481 /* FIXME: Should the slave device really be on a separate bus? */
1482   - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *)
1483   - i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s));
  1482 + PXA2xxI2CState *s = (PXA2xxI2CState *)
  1483 + i2c_slave_init(i2c_init_bus(), 0, sizeof(PXA2xxI2CState));
1484 1484  
1485 1485 s->irq = irq;
1486 1486 s->slave.event = pxa2xx_i2c_event;
... ... @@ -1500,13 +1500,13 @@ struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
1500 1500 return s;
1501 1501 }
1502 1502  
1503   -i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s)
  1503 +i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1504 1504 {
1505 1505 return s->bus;
1506 1506 }
1507 1507  
1508 1508 /* PXA Inter-IC Sound Controller */
1509   -static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s)
  1509 +static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1510 1510 {
1511 1511 i2s->rx_len = 0;
1512 1512 i2s->tx_len = 0;
... ... @@ -1523,7 +1523,7 @@ static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s)
1523 1523 #define SACR_DREC(val) (val & (1 << 3))
1524 1524 #define SACR_DPRL(val) (val & (1 << 4))
1525 1525  
1526   -static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s)
  1526 +static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1527 1527 {
1528 1528 int rfs, tfs;
1529 1529 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
... ... @@ -1562,7 +1562,7 @@ static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s)
1562 1562  
1563 1563 static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1564 1564 {
1565   - struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
  1565 + PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1566 1566  
1567 1567 switch (addr) {
1568 1568 case SACR0:
... ... @@ -1594,7 +1594,7 @@ static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1594 1594 static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1595 1595 uint32_t value)
1596 1596 {
1597   - struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
  1597 + PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1598 1598 uint32_t *sample;
1599 1599  
1600 1600 switch (addr) {
... ... @@ -1660,7 +1660,7 @@ static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = {
1660 1660  
1661 1661 static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
1662 1662 {
1663   - struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
  1663 + PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1664 1664  
1665 1665 qemu_put_be32s(f, &s->control[0]);
1666 1666 qemu_put_be32s(f, &s->control[1]);
... ... @@ -1676,7 +1676,7 @@ static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
1676 1676  
1677 1677 static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
1678 1678 {
1679   - struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
  1679 + PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1680 1680  
1681 1681 qemu_get_be32s(f, &s->control[0]);
1682 1682 qemu_get_be32s(f, &s->control[1]);
... ... @@ -1694,7 +1694,7 @@ static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
1694 1694  
1695 1695 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1696 1696 {
1697   - struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
  1697 + PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1698 1698 uint32_t *sample;
1699 1699  
1700 1700 /* Signal FIFO errors */
... ... @@ -1714,12 +1714,12 @@ static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1714 1714 pxa2xx_i2s_update(s);
1715 1715 }
1716 1716  
1717   -static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base,
1718   - qemu_irq irq, struct pxa2xx_dma_state_s *dma)
  1717 +static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
  1718 + qemu_irq irq, PXA2xxDMAState *dma)
1719 1719 {
1720 1720 int iomemtype;
1721   - struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *)
1722   - qemu_mallocz(sizeof(struct pxa2xx_i2s_s));
  1721 + PXA2xxI2SState *s = (PXA2xxI2SState *)
  1722 + qemu_mallocz(sizeof(PXA2xxI2SState));
1723 1723  
1724 1724 s->irq = irq;
1725 1725 s->dma = dma;
... ... @@ -1738,9 +1738,9 @@ static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base,
1738 1738 }
1739 1739  
1740 1740 /* PXA Fast Infra-red Communications Port */
1741   -struct pxa2xx_fir_s {
  1741 +struct PXA2xxFIrState {
1742 1742 qemu_irq irq;
1743   - struct pxa2xx_dma_state_s *dma;
  1743 + PXA2xxDMAState *dma;
1744 1744 int enable;
1745 1745 CharDriverState *chr;
1746 1746  
... ... @@ -1752,7 +1752,7 @@ struct pxa2xx_fir_s {
1752 1752 uint8_t rx_fifo[64];
1753 1753 };
1754 1754  
1755   -static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s)
  1755 +static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1756 1756 {
1757 1757 s->control[0] = 0x00;
1758 1758 s->control[1] = 0x00;
... ... @@ -1762,7 +1762,7 @@ static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s)
1762 1762 s->enable = 0;
1763 1763 }
1764 1764  
1765   -static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s)
  1765 +static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1766 1766 {
1767 1767 static const int tresh[4] = { 8, 16, 32, 0 };
1768 1768 int intr = 0;
... ... @@ -1810,7 +1810,7 @@ static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s)
1810 1810  
1811 1811 static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1812 1812 {
1813   - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
  1813 + PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1814 1814 uint8_t ret;
1815 1815  
1816 1816 switch (addr) {
... ... @@ -1848,7 +1848,7 @@ static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1848 1848 static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1849 1849 uint32_t value)
1850 1850 {
1851   - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
  1851 + PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1852 1852 uint8_t ch;
1853 1853  
1854 1854 switch (addr) {
... ... @@ -1903,13 +1903,13 @@ static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = {
1903 1903  
1904 1904 static int pxa2xx_fir_is_empty(void *opaque)
1905 1905 {
1906   - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
  1906 + PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1907 1907 return (s->rx_len < 64);
1908 1908 }
1909 1909  
1910 1910 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1911 1911 {
1912   - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
  1912 + PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1913 1913 if (!(s->control[0] & (1 << 4))) /* RXE */
1914 1914 return;
1915 1915  
... ... @@ -1935,7 +1935,7 @@ static void pxa2xx_fir_event(void *opaque, int event)
1935 1935  
1936 1936 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1937 1937 {
1938   - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
  1938 + PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1939 1939 int i;
1940 1940  
1941 1941 qemu_put_be32(f, s->enable);
... ... @@ -1953,7 +1953,7 @@ static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1953 1953  
1954 1954 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1955 1955 {
1956   - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
  1956 + PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1957 1957 int i;
1958 1958  
1959 1959 s->enable = qemu_get_be32(f);
... ... @@ -1972,13 +1972,13 @@ static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1972 1972 return 0;
1973 1973 }
1974 1974  
1975   -static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
1976   - qemu_irq irq, struct pxa2xx_dma_state_s *dma,
  1975 +static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
  1976 + qemu_irq irq, PXA2xxDMAState *dma,
1977 1977 CharDriverState *chr)
1978 1978 {
1979 1979 int iomemtype;
1980   - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *)
1981   - qemu_mallocz(sizeof(struct pxa2xx_fir_s));
  1980 + PXA2xxFIrState *s = (PXA2xxFIrState *)
  1981 + qemu_mallocz(sizeof(PXA2xxFIrState));
1982 1982  
1983 1983 s->irq = irq;
1984 1984 s->dma = dma;
... ... @@ -2001,7 +2001,7 @@ static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
2001 2001  
2002 2002 static void pxa2xx_reset(void *opaque, int line, int level)
2003 2003 {
2004   - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
  2004 + PXA2xxState *s = (PXA2xxState *) opaque;
2005 2005  
2006 2006 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2007 2007 cpu_reset(s->env);
... ... @@ -2010,13 +2010,13 @@ static void pxa2xx_reset(void *opaque, int line, int level)
2010 2010 }
2011 2011  
2012 2012 /* Initialise a PXA270 integrated chip (ARM based core). */
2013   -struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision)
  2013 +PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
2014 2014 {
2015   - struct pxa2xx_state_s *s;
2016   - struct pxa2xx_ssp_s *ssp;
  2015 + PXA2xxState *s;
  2016 + PXA2xxSSPState *ssp;
2017 2017 int iomemtype, i;
2018 2018 int index;
2019   - s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
  2019 + s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2020 2020  
2021 2021 if (revision && strncmp(revision, "pxa27", 5)) {
2022 2022 fprintf(stderr, "Machine requires a PXA27x processor.\n");
... ... @@ -2094,10 +2094,10 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision
2094 2094 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2095 2095  
2096 2096 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2097   - s->ssp = (struct pxa2xx_ssp_s **)
2098   - qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
2099   - ssp = (struct pxa2xx_ssp_s *)
2100   - qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
  2097 + s->ssp = (PXA2xxSSPState **)
  2098 + qemu_mallocz(sizeof(PXA2xxSSPState *) * i);
  2099 + ssp = (PXA2xxSSPState *)
  2100 + qemu_mallocz(sizeof(PXA2xxSSPState) * i);
2101 2101 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2102 2102 target_phys_addr_t ssp_base;
2103 2103 s->ssp[i] = &ssp[i];
... ... @@ -2139,14 +2139,14 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision
2139 2139 }
2140 2140  
2141 2141 /* Initialise a PXA255 integrated chip (ARM based core). */
2142   -struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size)
  2142 +PXA2xxState *pxa255_init(unsigned int sdram_size)
2143 2143 {
2144   - struct pxa2xx_state_s *s;
2145   - struct pxa2xx_ssp_s *ssp;
  2144 + PXA2xxState *s;
  2145 + PXA2xxSSPState *ssp;
2146 2146 int iomemtype, i;
2147 2147 int index;
2148 2148  
2149   - s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
  2149 + s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2150 2150  
2151 2151 s->env = cpu_init("pxa255");
2152 2152 if (!s->env) {
... ... @@ -2216,10 +2216,10 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size)
2216 2216 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2217 2217  
2218 2218 for (i = 0; pxa255_ssp[i].io_base; i ++);
2219   - s->ssp = (struct pxa2xx_ssp_s **)
2220   - qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
2221   - ssp = (struct pxa2xx_ssp_s *)
2222   - qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
  2219 + s->ssp = (PXA2xxSSPState **)
  2220 + qemu_mallocz(sizeof(PXA2xxSSPState *) * i);
  2221 + ssp = (PXA2xxSSPState *)
  2222 + qemu_mallocz(sizeof(PXA2xxSSPState) * i);
2223 2223 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2224 2224 target_phys_addr_t ssp_base;
2225 2225 s->ssp[i] = &ssp[i];
... ...
hw/pxa2xx_dma.c
  View file @bc24a22
... ... @@ -11,19 +11,19 @@
11 11 #include "hw.h"
12 12 #include "pxa.h"
13 13  
14   -struct pxa2xx_dma_channel_s {
  14 +typedef struct {
15 15 target_phys_addr_t descr;
16 16 target_phys_addr_t src;
17 17 target_phys_addr_t dest;
18 18 uint32_t cmd;
19 19 uint32_t state;
20 20 int request;
21   -};
  21 +} PXA2xxDMAChannel;
22 22  
23 23 /* Allow the DMA to be used as a PIC. */
24 24 typedef void (*pxa2xx_dma_handler_t)(void *opaque, int irq, int level);
25 25  
26   -struct pxa2xx_dma_state_s {
  26 +struct PXA2xxDMAState {
27 27 pxa2xx_dma_handler_t handler;
28 28 qemu_irq irq;
29 29  
... ... @@ -37,7 +37,7 @@ struct pxa2xx_dma_state_s {
37 37 uint32_t pio;
38 38  
39 39 int channels;
40   - struct pxa2xx_dma_channel_s *chan;
  40 + PXA2xxDMAChannel *chan;
41 41  
42 42 uint8_t *req;
43 43  
... ... @@ -106,7 +106,7 @@ struct pxa2xx_dma_state_s {
106 106 #define DCSR_NODESCFETCH (1 << 30)
107 107 #define DCSR_RUN (1 << 31)
108 108  
109   -static inline void pxa2xx_dma_update(struct pxa2xx_dma_state_s *s, int ch)
  109 +static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch)
110 110 {
111 111 if (ch >= 0) {
112 112 if ((s->chan[ch].state & DCSR_STOPIRQEN) &&
... ... @@ -145,7 +145,7 @@ static inline void pxa2xx_dma_update(struct pxa2xx_dma_state_s *s, int ch)
145 145 }
146 146  
147 147 static inline void pxa2xx_dma_descriptor_fetch(
148   - struct pxa2xx_dma_state_s *s, int ch)
  148 + PXA2xxDMAState *s, int ch)
149 149 {
150 150 uint32_t desc[4];
151 151 target_phys_addr_t daddr = s->chan[ch].descr & ~0xf;
... ... @@ -170,14 +170,14 @@ static inline void pxa2xx_dma_descriptor_fetch(
170 170 s->chan[ch].state |= DCSR_STARTINTR;
171 171 }
172 172  
173   -static void pxa2xx_dma_run(struct pxa2xx_dma_state_s *s)
  173 +static void pxa2xx_dma_run(PXA2xxDMAState *s)
174 174 {
175 175 int c, srcinc, destinc;
176 176 uint32_t n, size;
177 177 uint32_t width;
178 178 uint32_t length;
179 179 uint8_t buffer[32];
180   - struct pxa2xx_dma_channel_s *ch;
  180 + PXA2xxDMAChannel *ch;
181 181  
182 182 if (s->running ++)
183 183 return;
... ... @@ -254,7 +254,7 @@ static void pxa2xx_dma_run(struct pxa2xx_dma_state_s *s)
254 254  
255 255 static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset)
256 256 {
257   - struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque;
  257 + PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
258 258 unsigned int channel;
259 259  
260 260 switch (offset) {
... ... @@ -308,7 +308,7 @@ static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset)
308 308 static void pxa2xx_dma_write(void *opaque,
309 309 target_phys_addr_t offset, uint32_t value)
310 310 {
311   - struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque;
  311 + PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
312 312 unsigned int channel;
313 313  
314 314 switch (offset) {
... ... @@ -430,7 +430,7 @@ static CPUWriteMemoryFunc *pxa2xx_dma_writefn[] = {
430 430  
431 431 static void pxa2xx_dma_save(QEMUFile *f, void *opaque)
432 432 {
433   - struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque;
  433 + PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
434 434 int i;
435 435  
436 436 qemu_put_be32(f, s->channels);
... ... @@ -456,7 +456,7 @@ static void pxa2xx_dma_save(QEMUFile *f, void *opaque)
456 456  
457 457 static int pxa2xx_dma_load(QEMUFile *f, void *opaque, int version_id)
458 458 {
459   - struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque;
  459 + PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
460 460 int i;
461 461  
462 462 if (qemu_get_be32(f) != s->channels)
... ... @@ -483,21 +483,21 @@ static int pxa2xx_dma_load(QEMUFile *f, void *opaque, int version_id)
483 483 return 0;
484 484 }
485 485  
486   -static struct pxa2xx_dma_state_s *pxa2xx_dma_init(target_phys_addr_t base,
  486 +static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base,
487 487 qemu_irq irq, int channels)
488 488 {
489 489 int i, iomemtype;
490   - struct pxa2xx_dma_state_s *s;
491   - s = (struct pxa2xx_dma_state_s *)
492   - qemu_mallocz(sizeof(struct pxa2xx_dma_state_s));
  490 + PXA2xxDMAState *s;
  491 + s = (PXA2xxDMAState *)
  492 + qemu_mallocz(sizeof(PXA2xxDMAState));
493 493  
494 494 s->channels = channels;
495   - s->chan = qemu_mallocz(sizeof(struct pxa2xx_dma_channel_s) * s->channels);
  495 + s->chan = qemu_mallocz(sizeof(PXA2xxDMAChannel) * s->channels);
496 496 s->irq = irq;
497 497 s->handler = (pxa2xx_dma_handler_t) pxa2xx_dma_request;
498 498 s->req = qemu_mallocz(sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
499 499  
500   - memset(s->chan, 0, sizeof(struct pxa2xx_dma_channel_s) * s->channels);
  500 + memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels);
501 501 for (i = 0; i < s->channels; i ++)
502 502 s->chan[i].state = DCSR_STOPINTR;
503 503  
... ... @@ -512,19 +512,19 @@ static struct pxa2xx_dma_state_s *pxa2xx_dma_init(target_phys_addr_t base,
512 512 return s;
513 513 }
514 514  
515   -struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
  515 +PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
516 516 qemu_irq irq)
517 517 {
518 518 return pxa2xx_dma_init(base, irq, PXA27X_DMA_NUM_CHANNELS);
519 519 }
520 520  
521   -struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
  521 +PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
522 522 qemu_irq irq)
523 523 {
524 524 return pxa2xx_dma_init(base, irq, PXA255_DMA_NUM_CHANNELS);
525 525 }
526 526  
527   -void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on)
  527 +void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on)
528 528 {
529 529 int ch;
530 530 if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS)
... ...
hw/pxa2xx_gpio.c
  View file @bc24a22
... ... @@ -12,7 +12,7 @@
12 12  
13 13 #define PXA2XX_GPIO_BANKS 4
14 14  
15   -struct pxa2xx_gpio_info_s {
  15 +struct PXA2xxGPIOInfo {
16 16 qemu_irq *pic;
17 17 int lines;
18 18 CPUState *cpu_env;
... ... @@ -63,7 +63,7 @@ static struct {
63 63 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
64 64 };
65 65  
66   -static void pxa2xx_gpio_irq_update(struct pxa2xx_gpio_info_s *s)
  66 +static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
67 67 {
68 68 if (s->status[0] & (1 << 0))
69 69 qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_0]);
... ... @@ -88,7 +88,7 @@ static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
88 88  
89 89 static void pxa2xx_gpio_set(void *opaque, int line, int level)
90 90 {
91   - struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
  91 + PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
92 92 int bank;
93 93 uint32_t mask;
94 94  
... ... @@ -118,7 +118,7 @@ static void pxa2xx_gpio_set(void *opaque, int line, int level)
118 118 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
119 119 }
120 120  
121   -static void pxa2xx_gpio_handler_update(struct pxa2xx_gpio_info_s *s) {
  121 +static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
122 122 uint32_t level, diff;
123 123 int i, bit, line;
124 124 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
... ... @@ -136,7 +136,7 @@ static void pxa2xx_gpio_handler_update(struct pxa2xx_gpio_info_s *s) {
136 136  
137 137 static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
138 138 {
139   - struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
  139 + PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
140 140 uint32_t ret;
141 141 int bank;
142 142 if (offset >= 0x200)
... ... @@ -188,7 +188,7 @@ static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
188 188 static void pxa2xx_gpio_write(void *opaque,
189 189 target_phys_addr_t offset, uint32_t value)
190 190 {
191   - struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
  191 + PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
192 192 int bank;
193 193 if (offset >= 0x200)
194 194 return;
... ... @@ -251,7 +251,7 @@ static CPUWriteMemoryFunc *pxa2xx_gpio_writefn[] = {
251 251  
252 252 static void pxa2xx_gpio_save(QEMUFile *f, void *opaque)
253 253 {
254   - struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
  254 + PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
255 255 int i;
256 256  
257 257 qemu_put_be32(f, s->lines);
... ... @@ -272,7 +272,7 @@ static void pxa2xx_gpio_save(QEMUFile *f, void *opaque)
272 272  
273 273 static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id)
274 274 {
275   - struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
  275 + PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
276 276 int i;
277 277  
278 278 if (qemu_get_be32(f) != s->lines)
... ... @@ -294,15 +294,15 @@ static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id)
294 294 return 0;
295 295 }
296 296  
297   -struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
  297 +PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base,
298 298 CPUState *env, qemu_irq *pic, int lines)
299 299 {
300 300 int iomemtype;
301   - struct pxa2xx_gpio_info_s *s;
  301 + PXA2xxGPIOInfo *s;
302 302  
303   - s = (struct pxa2xx_gpio_info_s *)
304   - qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s));
305   - memset(s, 0, sizeof(struct pxa2xx_gpio_info_s));
  303 + s = (PXA2xxGPIOInfo *)
  304 + qemu_mallocz(sizeof(PXA2xxGPIOInfo));
  305 + memset(s, 0, sizeof(PXA2xxGPIOInfo));
306 306 s->pic = pic;
307 307 s->lines = lines;
308 308 s->cpu_env = env;
... ... @@ -318,12 +318,12 @@ struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
318 318 return s;
319 319 }
320 320  
321   -qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s)
  321 +qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s)
322 322 {
323 323 return s->in;
324 324 }
325 325  
326   -void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s,
  326 +void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s,
327 327 int line, qemu_irq handler)
328 328 {
329 329 if (line >= s->lines) {
... ... @@ -338,7 +338,7 @@ void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s,
338 338 * Registers a callback to notify on GPLR reads. This normally
339 339 * shouldn't be needed but it is used for the hack on Spitz machines.
340 340 */
341   -void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler)
  341 +void pxa2xx_gpio_read_notifier(PXA2xxGPIOInfo *s, qemu_irq handler)
342 342 {
343 343 s->read_notify = handler;
344 344 }
... ...
hw/pxa2xx_keypad.c
  View file @bc24a22
... ... @@ -79,7 +79,7 @@
79 79 #define PXAKBD_MAXROW 8
80 80 #define PXAKBD_MAXCOL 8
81 81  
82   -struct pxa2xx_keypad_s{
  82 +struct PXA2xxKeyPadState {
83 83 qemu_irq irq;
84 84 struct keymap *map;
85 85  
... ... @@ -95,7 +95,7 @@ struct pxa2xx_keypad_s{
95 95 uint32_t kpkdi;
96 96 };
97 97  
98   -static void pxa27x_keyboard_event (struct pxa2xx_keypad_s *kp, int keycode)
  98 +static void pxa27x_keyboard_event (PXA2xxKeyPadState *kp, int keycode)
99 99 {
100 100 int row, col,rel;
101 101  
... ... @@ -156,7 +156,7 @@ out:
156 156  
157 157 static uint32_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset)
158 158 {
159   - struct pxa2xx_keypad_s *s = (struct pxa2xx_keypad_s *) opaque;
  159 + PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
160 160 uint32_t tmp;
161 161  
162 162 switch (offset) {
... ... @@ -218,7 +218,7 @@ static uint32_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset)
218 218 static void pxa2xx_keypad_write(void *opaque,
219 219 target_phys_addr_t offset, uint32_t value)
220 220 {
221   - struct pxa2xx_keypad_s *s = (struct pxa2xx_keypad_s *) opaque;
  221 + PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
222 222  
223 223 switch (offset) {
224 224 case KPC:
... ... @@ -271,7 +271,7 @@ static CPUWriteMemoryFunc *pxa2xx_keypad_writefn[] = {
271 271  
272 272 static void pxa2xx_keypad_save(QEMUFile *f, void *opaque)
273 273 {
274   - struct pxa2xx_keypad_s *s = (struct pxa2xx_keypad_s *) opaque;
  274 + PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
275 275  
276 276 qemu_put_be32s(f, &s->kpc);
277 277 qemu_put_be32s(f, &s->kpdk);
... ... @@ -288,7 +288,7 @@ static void pxa2xx_keypad_save(QEMUFile *f, void *opaque)
288 288  
289 289 static int pxa2xx_keypad_load(QEMUFile *f, void *opaque, int version_id)
290 290 {
291   - struct pxa2xx_keypad_s *s = (struct pxa2xx_keypad_s *) opaque;
  291 + PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
292 292  
293 293 qemu_get_be32s(f, &s->kpc);
294 294 qemu_get_be32s(f, &s->kpdk);
... ... @@ -304,13 +304,13 @@ static int pxa2xx_keypad_load(QEMUFile *f, void *opaque, int version_id)
304 304 return 0;
305 305 }
306 306  
307   -struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base,
  307 +PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
308 308 qemu_irq irq)
309 309 {
310 310 int iomemtype;
311   - struct pxa2xx_keypad_s *s;
  311 + PXA2xxKeyPadState *s;
312 312  
313   - s = (struct pxa2xx_keypad_s *) qemu_mallocz(sizeof(struct pxa2xx_keypad_s));
  313 + s = (PXA2xxKeyPadState *) qemu_mallocz(sizeof(PXA2xxKeyPadState));
314 314 s->irq = irq;
315 315  
316 316 iomemtype = cpu_register_io_memory(0, pxa2xx_keypad_readfn,
... ... @@ -323,7 +323,7 @@ struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base,
323 323 return s;
324 324 }
325 325  
326   -void pxa27x_register_keypad(struct pxa2xx_keypad_s *kp, struct keymap *map,
  326 +void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
327 327 int size)
328 328 {
329 329 if(!map || size < 0x80) {
... ...
hw/pxa2xx_lcd.c
  View file @bc24a22
... ... @@ -15,7 +15,7 @@
15 15 #include "sysemu.h"
16 16 #include "framebuffer.h"
17 17  
18   -struct pxa2xx_lcdc_s {
  18 +struct PXA2xxLCDState {
19 19 qemu_irq irq;
20 20 int irqlevel;
21 21  
... ... @@ -55,7 +55,7 @@ struct pxa2xx_lcdc_s {
55 55 int up;
56 56 uint8_t palette[1024];
57 57 uint8_t pbuffer[1024];
58   - void (*redraw)(struct pxa2xx_lcdc_s *s, target_phys_addr_t addr,
  58 + void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
59 59 int *miny, int *maxy);
60 60  
61 61 target_phys_addr_t descriptor;
... ... @@ -68,12 +68,12 @@ struct pxa2xx_lcdc_s {
68 68 int orientation;
69 69 };
70 70  
71   -struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
  71 +typedef struct __attribute__ ((__packed__)) {
72 72 uint32_t fdaddr;
73 73 uint32_t fsaddr;
74 74 uint32_t fidr;
75 75 uint32_t ldcmd;
76   -};
  76 +} PXAFrameDescriptor;
77 77  
78 78 #define LCCR0 0x000 /* LCD Controller Control register 0 */
79 79 #define LCCR1 0x004 /* LCD Controller Control register 1 */
... ... @@ -177,7 +177,7 @@ struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
177 177 #define LDCMD_PAL (1 << 26)
178 178  
179 179 /* Route internal interrupt lines to the global IC */
180   -static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s)
  180 +static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
181 181 {
182 182 int level = 0;
183 183 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
... ... @@ -197,7 +197,7 @@ static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s)
197 197 }
198 198  
199 199 /* Set Branch Status interrupt high and poke associated registers */
200   -static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch)
  200 +static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch)
201 201 {
202 202 int unmasked;
203 203 if (ch == 0) {
... ... @@ -217,7 +217,7 @@ static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch)
217 217 }
218 218  
219 219 /* Set Start Of Frame Status interrupt high and poke associated registers */
220   -static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch)
  220 +static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch)
221 221 {
222 222 int unmasked;
223 223 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
... ... @@ -240,7 +240,7 @@ static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch)
240 240 }
241 241  
242 242 /* Set End Of Frame Status interrupt high and poke associated registers */
243   -static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch)
  243 +static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch)
244 244 {
245 245 int unmasked;
246 246 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
... ... @@ -263,7 +263,7 @@ static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch)
263 263 }
264 264  
265 265 /* Set Bus Error Status interrupt high and poke associated registers */
266   -static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch)
  266 +static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch)
267 267 {
268 268 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
269 269 if (s->irqlevel)
... ... @@ -273,7 +273,7 @@ static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch)
273 273 }
274 274  
275 275 /* Set Read Status interrupt high and poke associated registers */
276   -static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s)
  276 +static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
277 277 {
278 278 s->status[0] |= LCSR0_RDST;
279 279 if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
... ... @@ -281,9 +281,9 @@ static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s)
281 281 }
282 282  
283 283 /* Load new Frame Descriptors from DMA */
284   -static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s)
  284 +static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
285 285 {
286   - struct pxa_frame_descriptor_s desc;
  286 + PXAFrameDescriptor desc;
287 287 target_phys_addr_t descptr;
288 288 int i;
289 289  
... ... @@ -315,7 +315,7 @@ static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s)
315 315  
316 316 static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
317 317 {
318   - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
  318 + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
319 319 int ch;
320 320  
321 321 switch (offset) {
... ... @@ -409,7 +409,7 @@ static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
409 409 static void pxa2xx_lcdc_write(void *opaque,
410 410 target_phys_addr_t offset, uint32_t value)
411 411 {
412   - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
  412 + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
413 413 int ch;
414 414  
415 415 switch (offset) {
... ... @@ -572,7 +572,7 @@ static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = {
572 572 };
573 573  
574 574 /* Load new palette for a given DMA channel, convert to internal format */
575   -static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp)
  575 +static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
576 576 {
577 577 int i, n, format, r, g, b, alpha;
578 578 uint32_t *dest, *src;
... ... @@ -663,7 +663,7 @@ static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp)
663 663 }
664 664 }
665 665  
666   -static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s,
  666 +static void pxa2xx_lcdc_dma0_redraw_horiz(PXA2xxLCDState *s,
667 667 target_phys_addr_t addr, int *miny, int *maxy)
668 668 {
669 669 int src_width, dest_width;
... ... @@ -690,7 +690,7 @@ static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s,
690 690 fn, s->dma_ch[0].palette, miny, maxy);
691 691 }
692 692  
693   -static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s,
  693 +static void pxa2xx_lcdc_dma0_redraw_vert(PXA2xxLCDState *s,
694 694 target_phys_addr_t addr, int *miny, int *maxy)
695 695 {
696 696 int src_width, dest_width;
... ... @@ -718,7 +718,7 @@ static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s,
718 718 miny, maxy);
719 719 }
720 720  
721   -static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s)
  721 +static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
722 722 {
723 723 int width, height;
724 724 if (!(s->control[0] & LCCR0_ENB))
... ... @@ -740,7 +740,7 @@ static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s)
740 740  
741 741 static void pxa2xx_update_display(void *opaque)
742 742 {
743   - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
  743 + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
744 744 target_phys_addr_t fbptr;
745 745 int miny, maxy;
746 746 int ch;
... ... @@ -807,7 +807,7 @@ static void pxa2xx_update_display(void *opaque)
807 807  
808 808 static void pxa2xx_invalidate_display(void *opaque)
809 809 {
810   - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
  810 + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
811 811 s->invalidated = 1;
812 812 }
813 813  
... ... @@ -818,7 +818,7 @@ static void pxa2xx_screen_dump(void *opaque, const char *filename)
818 818  
819 819 static void pxa2xx_lcdc_orientation(void *opaque, int angle)
820 820 {
821   - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
  821 + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
822 822  
823 823 if (angle) {
824 824 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
... ... @@ -833,7 +833,7 @@ static void pxa2xx_lcdc_orientation(void *opaque, int angle)
833 833  
834 834 static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque)
835 835 {
836   - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
  836 + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
837 837 int i;
838 838  
839 839 qemu_put_be32(f, s->irqlevel);
... ... @@ -868,7 +868,7 @@ static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque)
868 868  
869 869 static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
870 870 {
871   - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
  871 + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
872 872 int i;
873 873  
874 874 s->irqlevel = qemu_get_be32(f);
... ... @@ -917,12 +917,12 @@ static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
917 917 #define BITS 32
918 918 #include "pxa2xx_template.h"
919 919  
920   -struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
  920 +PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
921 921 {
922 922 int iomemtype;
923   - struct pxa2xx_lcdc_s *s;
  923 + PXA2xxLCDState *s;
924 924  
925   - s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s));
  925 + s = (PXA2xxLCDState *) qemu_mallocz(sizeof(PXA2xxLCDState));
926 926 s->invalidated = 1;
927 927 s->irq = irq;
928 928  
... ... @@ -976,7 +976,7 @@ struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
976 976 return s;
977 977 }
978 978  
979   -void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler)
  979 +void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
980 980 {
981 981 s->vsync_cb = handler;
982 982 }
... ...
hw/pxa2xx_mmci.c
  View file @bc24a22
... ... @@ -11,7 +11,7 @@
11 11 #include "pxa.h"
12 12 #include "sd.h"
13 13  
14   -struct pxa2xx_mmci_s {
  14 +struct PXA2xxMMCIState {
15 15 qemu_irq irq;
16 16 void *dma;
17 17  
... ... @@ -96,22 +96,22 @@ struct pxa2xx_mmci_s {
96 96 #define PRTBUF_PRT_BUF (1 << 0)
97 97  
98 98 /* Route internal interrupt lines to the global IC and DMA */
99   -static void pxa2xx_mmci_int_update(struct pxa2xx_mmci_s *s)
  99 +static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
100 100 {
101 101 uint32_t mask = s->intmask;
102 102 if (s->cmdat & CMDAT_DMA_EN) {
103 103 mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;
104 104  
105   - pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma,
  105 + pxa2xx_dma_request(s->dma,
106 106 PXA2XX_RX_RQ_MMCI, !!(s->intreq & INT_RXFIFO_REQ));
107   - pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma,
  107 + pxa2xx_dma_request(s->dma,
108 108 PXA2XX_TX_RQ_MMCI, !!(s->intreq & INT_TXFIFO_REQ));
109 109 }
110 110  
111 111 qemu_set_irq(s->irq, !!(s->intreq & ~mask));
112 112 }
113 113  
114   -static void pxa2xx_mmci_fifo_update(struct pxa2xx_mmci_s *s)
  114 +static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
115 115 {
116 116 if (!s->active)
117 117 return;
... ... @@ -147,10 +147,10 @@ static void pxa2xx_mmci_fifo_update(struct pxa2xx_mmci_s *s)
147 147 pxa2xx_mmci_int_update(s);
148 148 }
149 149  
150   -static void pxa2xx_mmci_wakequeues(struct pxa2xx_mmci_s *s)
  150 +static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
151 151 {
152 152 int rsplen, i;
153   - struct sd_request_s request;
  153 + SDRequest request;
154 154 uint8_t response[16];
155 155  
156 156 s->active = 1;
... ... @@ -213,7 +213,7 @@ static void pxa2xx_mmci_wakequeues(struct pxa2xx_mmci_s *s)
213 213  
214 214 static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
215 215 {
216   - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
  216 + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
217 217 uint32_t ret;
218 218  
219 219 switch (offset) {
... ... @@ -275,7 +275,7 @@ static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
275 275 static void pxa2xx_mmci_write(void *opaque,
276 276 target_phys_addr_t offset, uint32_t value)
277 277 {
278   - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
  278 + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
279 279  
280 280 switch (offset) {
281 281 case MMC_STRPCL:
... ... @@ -384,21 +384,21 @@ static void pxa2xx_mmci_write(void *opaque,
384 384  
385 385 static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset)
386 386 {
387   - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
  387 + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
388 388 s->ac_width = 1;
389 389 return pxa2xx_mmci_read(opaque, offset);
390 390 }
391 391  
392 392 static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset)
393 393 {
394   - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
  394 + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
395 395 s->ac_width = 2;
396 396 return pxa2xx_mmci_read(opaque, offset);
397 397 }
398 398  
399 399 static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
400 400 {
401   - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
  401 + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
402 402 s->ac_width = 4;
403 403 return pxa2xx_mmci_read(opaque, offset);
404 404 }
... ... @@ -412,7 +412,7 @@ static CPUReadMemoryFunc *pxa2xx_mmci_readfn[] = {
412 412 static void pxa2xx_mmci_writeb(void *opaque,
413 413 target_phys_addr_t offset, uint32_t value)
414 414 {
415   - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
  415 + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
416 416 s->ac_width = 1;
417 417 pxa2xx_mmci_write(opaque, offset, value);
418 418 }
... ... @@ -420,7 +420,7 @@ static void pxa2xx_mmci_writeb(void *opaque,
420 420 static void pxa2xx_mmci_writeh(void *opaque,
421 421 target_phys_addr_t offset, uint32_t value)
422 422 {
423   - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
  423 + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
424 424 s->ac_width = 2;
425 425 pxa2xx_mmci_write(opaque, offset, value);
426 426 }
... ... @@ -428,7 +428,7 @@ static void pxa2xx_mmci_writeh(void *opaque,
428 428 static void pxa2xx_mmci_writew(void *opaque,
429 429 target_phys_addr_t offset, uint32_t value)
430 430 {
431   - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
  431 + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
432 432 s->ac_width = 4;
433 433 pxa2xx_mmci_write(opaque, offset, value);
434 434 }
... ... @@ -441,7 +441,7 @@ static CPUWriteMemoryFunc *pxa2xx_mmci_writefn[] = {
441 441  
442 442 static void pxa2xx_mmci_save(QEMUFile *f, void *opaque)
443 443 {
444   - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
  444 + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
445 445 int i;
446 446  
447 447 qemu_put_be32s(f, &s->status);
... ... @@ -475,7 +475,7 @@ static void pxa2xx_mmci_save(QEMUFile *f, void *opaque)
475 475  
476 476 static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id)
477 477 {
478   - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
  478 + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
479 479 int i;
480 480  
481 481 qemu_get_be32s(f, &s->status);
... ... @@ -517,13 +517,13 @@ static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id)
517 517 return 0;
518 518 }
519 519  
520   -struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
  520 +PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
521 521 BlockDriverState *bd, qemu_irq irq, void *dma)
522 522 {
523 523 int iomemtype;
524   - struct pxa2xx_mmci_s *s;
  524 + PXA2xxMMCIState *s;
525 525  
526   - s = (struct pxa2xx_mmci_s *) qemu_mallocz(sizeof(struct pxa2xx_mmci_s));
  526 + s = (PXA2xxMMCIState *) qemu_mallocz(sizeof(PXA2xxMMCIState));
527 527 s->irq = irq;
528 528 s->dma = dma;
529 529  
... ... @@ -540,7 +540,7 @@ struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
540 540 return s;
541 541 }
542 542  
543   -void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly,
  543 +void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
544 544 qemu_irq coverswitch)
545 545 {
546 546 sd_set_cb(s->card, readonly, coverswitch);
... ...
hw/pxa2xx_pcmcia.c
  View file @bc24a22
... ... @@ -11,9 +11,9 @@
11 11 #include "pcmcia.h"
12 12 #include "pxa.h"
13 13  
14   -struct pxa2xx_pcmcia_s {
15   - struct pcmcia_socket_s slot;
16   - struct pcmcia_card_s *card;
  14 +struct PXA2xxPCMCIAState {
  15 + PCMCIASocket slot;
  16 + PCMCIACardState *card;
17 17  
18 18 qemu_irq irq;
19 19 qemu_irq cd_irq;
... ... @@ -22,7 +22,7 @@ struct pxa2xx_pcmcia_s {
22 22 static uint32_t pxa2xx_pcmcia_common_read(void *opaque,
23 23 target_phys_addr_t offset)
24 24 {
25   - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
  25 + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
26 26  
27 27 if (s->slot.attached) {
28 28 return s->card->common_read(s->card->state, offset);
... ... @@ -34,7 +34,7 @@ static uint32_t pxa2xx_pcmcia_common_read(void *opaque,
34 34 static void pxa2xx_pcmcia_common_write(void *opaque,
35 35 target_phys_addr_t offset, uint32_t value)
36 36 {
37   - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
  37 + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
38 38  
39 39 if (s->slot.attached) {
40 40 s->card->common_write(s->card->state, offset, value);
... ... @@ -44,7 +44,7 @@ static void pxa2xx_pcmcia_common_write(void *opaque,
44 44 static uint32_t pxa2xx_pcmcia_attr_read(void *opaque,
45 45 target_phys_addr_t offset)
46 46 {
47   - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
  47 + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
48 48  
49 49 if (s->slot.attached) {
50 50 return s->card->attr_read(s->card->state, offset);
... ... @@ -56,7 +56,7 @@ static uint32_t pxa2xx_pcmcia_attr_read(void *opaque,
56 56 static void pxa2xx_pcmcia_attr_write(void *opaque,
57 57 target_phys_addr_t offset, uint32_t value)
58 58 {
59   - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
  59 + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
60 60  
61 61 if (s->slot.attached) {
62 62 s->card->attr_write(s->card->state, offset, value);
... ... @@ -66,7 +66,7 @@ static void pxa2xx_pcmcia_attr_write(void *opaque,
66 66 static uint32_t pxa2xx_pcmcia_io_read(void *opaque,
67 67 target_phys_addr_t offset)
68 68 {
69   - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
  69 + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
70 70  
71 71 if (s->slot.attached) {
72 72 return s->card->io_read(s->card->state, offset);
... ... @@ -78,7 +78,7 @@ static uint32_t pxa2xx_pcmcia_io_read(void *opaque,
78 78 static void pxa2xx_pcmcia_io_write(void *opaque,
79 79 target_phys_addr_t offset, uint32_t value)
80 80 {
81   - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
  81 + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
82 82  
83 83 if (s->slot.attached) {
84 84 s->card->io_write(s->card->state, offset, value);
... ... @@ -123,20 +123,20 @@ static CPUWriteMemoryFunc *pxa2xx_pcmcia_io_writefn[] = {
123 123  
124 124 static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level)
125 125 {
126   - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
  126 + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
127 127 if (!s->irq)
128 128 return;
129 129  
130 130 qemu_set_irq(s->irq, level);
131 131 }
132 132  
133   -struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base)
  133 +PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base)
134 134 {
135 135 int iomemtype;
136   - struct pxa2xx_pcmcia_s *s;
  136 + PXA2xxPCMCIAState *s;
137 137  
138   - s = (struct pxa2xx_pcmcia_s *)
139   - qemu_mallocz(sizeof(struct pxa2xx_pcmcia_s));
  138 + s = (PXA2xxPCMCIAState *)
  139 + qemu_mallocz(sizeof(PXA2xxPCMCIAState));
140 140  
141 141 /* Socket I/O Memory Space */
142 142 iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_io_readfn,
... ... @@ -166,9 +166,9 @@ struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base)
166 166 }
167 167  
168 168 /* Insert a new card into a slot */
169   -int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card)
  169 +int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card)
170 170 {
171   - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
  171 + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
172 172 if (s->slot.attached)
173 173 return -EEXIST;
174 174  
... ... @@ -188,7 +188,7 @@ int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card)
188 188 /* Eject card from the slot */
189 189 int pxa2xx_pcmcia_dettach(void *opaque)
190 190 {
191   - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
  191 + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
192 192 if (!s->slot.attached)
193 193 return -ENOENT;
194 194  
... ... @@ -209,7 +209,7 @@ int pxa2xx_pcmcia_dettach(void *opaque)
209 209 /* Who to notify on card events */
210 210 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq)
211 211 {
212   - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
  212 + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
213 213 s->irq = irq;
214 214 s->cd_irq = cd_irq;
215 215 }
... ...
hw/pxa2xx_pic.c
  View file @bc24a22
... ... @@ -30,19 +30,19 @@
30 30  
31 31 #define PXA2XX_PIC_SRCS 40
32 32  
33   -struct pxa2xx_pic_state_s {
  33 +typedef struct {
34 34 CPUState *cpu_env;
35 35 uint32_t int_enabled[2];
36 36 uint32_t int_pending[2];
37 37 uint32_t is_fiq[2];
38 38 uint32_t int_idle;
39 39 uint32_t priority[PXA2XX_PIC_SRCS];
40   -};
  40 +} PXA2xxPICState;
41 41  
42 42 static void pxa2xx_pic_update(void *opaque)
43 43 {
44 44 uint32_t mask[2];
45   - struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
  45 + PXA2xxPICState *s = (PXA2xxPICState *) opaque;
46 46  
47 47 if (s->cpu_env->halted) {
48 48 mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
... ... @@ -69,7 +69,7 @@ static void pxa2xx_pic_update(void *opaque)
69 69 * IRQ/FIQ distinction as in PXA Developer Manual. */
70 70 static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
71 71 {
72   - struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
  72 + PXA2xxPICState *s = (PXA2xxPICState *) opaque;
73 73 int int_set = (irq >= 32);
74 74 irq &= 31;
75 75  
... ... @@ -81,7 +81,7 @@ static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
81 81 pxa2xx_pic_update(opaque);
82 82 }
83 83  
84   -static inline uint32_t pxa2xx_pic_highest(struct pxa2xx_pic_state_s *s) {
  84 +static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
85 85 int i, int_set, irq;
86 86 uint32_t bit, mask[2];
87 87 uint32_t ichp = 0x003f003f; /* Both IDs invalid */
... ... @@ -115,7 +115,7 @@ static inline uint32_t pxa2xx_pic_highest(struct pxa2xx_pic_state_s *s) {
115 115  
116 116 static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset)
117 117 {
118   - struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
  118 + PXA2xxPICState *s = (PXA2xxPICState *) opaque;
119 119  
120 120 switch (offset) {
121 121 case ICIP: /* IRQ Pending register */
... ... @@ -155,7 +155,7 @@ static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset)
155 155 static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset,
156 156 uint32_t value)
157 157 {
158   - struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
  158 + PXA2xxPICState *s = (PXA2xxPICState *) opaque;
159 159  
160 160 switch (offset) {
161 161 case ICMR: /* Mask register */
... ... @@ -243,7 +243,7 @@ static CPUWriteMemoryFunc *pxa2xx_pic_writefn[] = {
243 243  
244 244 static void pxa2xx_pic_save(QEMUFile *f, void *opaque)
245 245 {
246   - struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
  246 + PXA2xxPICState *s = (PXA2xxPICState *) opaque;
247 247 int i;
248 248  
249 249 for (i = 0; i < 2; i ++)
... ... @@ -259,7 +259,7 @@ static void pxa2xx_pic_save(QEMUFile *f, void *opaque)
259 259  
260 260 static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id)
261 261 {
262   - struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
  262 + PXA2xxPICState *s = (PXA2xxPICState *) opaque;
263 263 int i;
264 264  
265 265 for (i = 0; i < 2; i ++)
... ... @@ -278,12 +278,12 @@ static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id)
278 278  
279 279 qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
280 280 {
281   - struct pxa2xx_pic_state_s *s;
  281 + PXA2xxPICState *s;
282 282 int iomemtype;
283 283 qemu_irq *qi;
284 284  
285   - s = (struct pxa2xx_pic_state_s *)
286   - qemu_mallocz(sizeof(struct pxa2xx_pic_state_s));
  285 + s = (PXA2xxPICState *)
  286 + qemu_mallocz(sizeof(PXA2xxPICState));
287 287 if (!s)
288 288 return NULL;
289 289  
... ...
hw/pxa2xx_timer.c
  View file @bc24a22
... ... @@ -59,31 +59,31 @@ static int pxa2xx_timer4_freq[8] = {
59 59 [5 ... 7] = 0,
60 60 };
61 61  
62   -struct pxa2xx_timer0_s {
  62 +typedef struct {
63 63 uint32_t value;
64 64 int level;
65 65 qemu_irq irq;
66 66 QEMUTimer *qtimer;
67 67 int num;
68 68 void *info;
69   -};
  69 +} PXA2xxTimer0;
70 70  
71   -struct pxa2xx_timer4_s {
72   - struct pxa2xx_timer0_s tm;
  71 +typedef struct {
  72 + PXA2xxTimer0 tm;
73 73 int32_t oldclock;
74 74 int32_t clock;
75 75 uint64_t lastload;
76 76 uint32_t freq;
77 77 uint32_t control;
78   -};
  78 +} PXA2xxTimer4;
79 79  
80 80 typedef struct {
81 81 int32_t clock;
82 82 int32_t oldclock;
83 83 uint64_t lastload;
84 84 uint32_t freq;
85   - struct pxa2xx_timer0_s timer[4];
86   - struct pxa2xx_timer4_s *tm4;
  85 + PXA2xxTimer0 timer[4];
  86 + PXA2xxTimer4 *tm4;
87 87 uint32_t events;
88 88 uint32_t irq_enabled;
89 89 uint32_t reset3;
... ... @@ -332,7 +332,7 @@ static CPUWriteMemoryFunc *pxa2xx_timer_writefn[] = {
332 332  
333 333 static void pxa2xx_timer_tick(void *opaque)
334 334 {
335   - struct pxa2xx_timer0_s *t = (struct pxa2xx_timer0_s *) opaque;
  335 + PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
336 336 pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info;
337 337  
338 338 if (i->irq_enabled & (1 << t->num)) {
... ... @@ -350,7 +350,7 @@ static void pxa2xx_timer_tick(void *opaque)
350 350  
351 351 static void pxa2xx_timer_tick4(void *opaque)
352 352 {
353   - struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque;
  353 + PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
354 354 pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->tm.info;
355 355  
356 356 pxa2xx_timer_tick(&t->tm);
... ... @@ -474,8 +474,8 @@ void pxa27x_timer_init(target_phys_addr_t base,
474 474 pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);
475 475 int i;
476 476 s->freq = PXA27X_FREQ;
477   - s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 *
478   - sizeof(struct pxa2xx_timer4_s));
  477 + s->tm4 = (PXA2xxTimer4 *) qemu_mallocz(8 *
  478 + sizeof(PXA2xxTimer4));
479 479 for (i = 0; i < 8; i ++) {
480 480 s->tm4[i].tm.value = 0;
481 481 s->tm4[i].tm.irq = irq4;
... ...
... ... @@ -301,7 +301,7 @@ static void sd_set_sdstatus(SDState *sd)
301 301 memset(sd->sd_status, 0, 64);
302 302 }
303 303  
304   -static int sd_req_crc_validate(struct sd_request_s *req)
  304 +static int sd_req_crc_validate(SDRequest *req)
305 305 {
306 306 uint8_t buffer[5];
307 307 buffer[0] = 0x40 | req->cmd;
... ... @@ -580,7 +580,7 @@ static void sd_lock_command(SDState *sd)
580 580 }
581 581  
582 582 static sd_rsp_type_t sd_normal_command(SDState *sd,
583   - struct sd_request_s req)
  583 + SDRequest req)
584 584 {
585 585 uint32_t rca = 0x0000;
586 586  
... ... @@ -1119,7 +1119,7 @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
1119 1119 }
1120 1120  
1121 1121 static sd_rsp_type_t sd_app_command(SDState *sd,
1122   - struct sd_request_s req) {
  1122 + SDRequest req) {
1123 1123 uint32_t rca;
1124 1124  
1125 1125 if (sd_cmd_type[req.cmd] == sd_ac || sd_cmd_type[req.cmd] == sd_adtc)
... ... @@ -1228,7 +1228,7 @@ static sd_rsp_type_t sd_app_command(SDState *sd,
1228 1228 return sd_r0;
1229 1229 }
1230 1230  
1231   -int sd_do_command(SDState *sd, struct sd_request_s *req,
  1231 +int sd_do_command(SDState *sd, SDRequest *req,
1232 1232 uint8_t *response) {
1233 1233 uint32_t last_status = sd->card_status;
1234 1234 sd_rsp_type_t rtype;
... ...
... ... @@ -59,16 +59,16 @@ typedef enum {
59 59 sd_adtc, /* addressed with data transfer */
60 60 } sd_cmd_type_t;
61 61  
62   -struct sd_request_s {
  62 +typedef struct {
63 63 uint8_t cmd;
64 64 uint32_t arg;
65 65 uint8_t crc;
66   -};
  66 +} SDRequest;
67 67  
68 68 typedef struct SDState SDState;
69 69  
70 70 SDState *sd_init(BlockDriverState *bs, int is_spi);
71   -int sd_do_command(SDState *sd, struct sd_request_s *req,
  71 +int sd_do_command(SDState *sd, SDRequest *req,
72 72 uint8_t *response);
73 73 void sd_write_data(SDState *sd, uint8_t value);
74 74 uint8_t sd_read_data(SDState *sd);
... ...
hw/sharpsl.h
  View file @bc24a22
... ... @@ -10,11 +10,12 @@
10 10 fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__)
11 11  
12 12 /* zaurus.c */
13   -struct scoop_info_s *scoop_init(struct pxa2xx_state_s *cpu,
  13 +typedef struct ScoopInfo ScoopInfo;
  14 +ScoopInfo *scoop_init(PXA2xxState *cpu,
14 15 int instance, target_phys_addr_t target_base);
15 16 void scoop_gpio_set(void *opaque, int line, int level);
16   -qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s);
17   -void scoop_gpio_out_set(struct scoop_info_s *s, int line,
  17 +qemu_irq *scoop_gpio_in_get(ScoopInfo *s);
  18 +void scoop_gpio_out_set(ScoopInfo *s, int line,
18 19 qemu_irq handler);
19 20  
20 21 #define SL_PXA_PARAM_BASE 0xa0000a00
... ...
hw/spitz.c
  View file @bc24a22
... ... @@ -47,15 +47,15 @@
47 47 #define FLASHCTL_RYBY (1 << 5)
48 48 #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
49 49  
50   -struct sl_nand_s {
51   - struct nand_flash_s *nand;
  50 +typedef struct {
  51 + NANDFlashState *nand;
52 52 uint8_t ctl;
53   - struct ecc_state_s ecc;
54   -};
  53 + ECCState ecc;
  54 +} SLNANDState;
55 55  
56 56 static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
57 57 {
58   - struct sl_nand_s *s = (struct sl_nand_s *) opaque;
  58 + SLNANDState *s = (SLNANDState *) opaque;
59 59 int ryby;
60 60  
61 61 switch (addr) {
... ... @@ -93,7 +93,7 @@ static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
93 93  
94 94 static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
95 95 {
96   - struct sl_nand_s *s = (struct sl_nand_s *) opaque;
  96 + SLNANDState *s = (SLNANDState *) opaque;
97 97  
98 98 if (addr == FLASH_FLASHIO)
99 99 return ecc_digest(&s->ecc, nand_getio(s->nand)) |
... ... @@ -105,7 +105,7 @@ static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
105 105 static void sl_writeb(void *opaque, target_phys_addr_t addr,
106 106 uint32_t value)
107 107 {
108   - struct sl_nand_s *s = (struct sl_nand_s *) opaque;
  108 + SLNANDState *s = (SLNANDState *) opaque;
109 109  
110 110 switch (addr) {
111 111 case FLASH_ECCCLRR:
... ... @@ -134,7 +134,7 @@ static void sl_writeb(void *opaque, target_phys_addr_t addr,
134 134  
135 135 static void sl_save(QEMUFile *f, void *opaque)
136 136 {
137   - struct sl_nand_s *s = (struct sl_nand_s *) opaque;
  137 + SLNANDState *s = (SLNANDState *) opaque;
138 138  
139 139 qemu_put_8s(f, &s->ctl);
140 140 ecc_put(f, &s->ecc);
... ... @@ -142,7 +142,7 @@ static void sl_save(QEMUFile *f, void *opaque)
142 142  
143 143 static int sl_load(QEMUFile *f, void *opaque, int version_id)
144 144 {
145   - struct sl_nand_s *s = (struct sl_nand_s *) opaque;
  145 + SLNANDState *s = (SLNANDState *) opaque;
146 146  
147 147 qemu_get_8s(f, &s->ctl);
148 148 ecc_get(f, &s->ecc);
... ... @@ -155,10 +155,10 @@ enum {
155 155 FLASH_1024M,
156 156 };
157 157  
158   -static void sl_flash_register(struct pxa2xx_state_s *cpu, int size)
  158 +static void sl_flash_register(PXA2xxState *cpu, int size)
159 159 {
160 160 int iomemtype;
161   - struct sl_nand_s *s;
  161 + SLNANDState *s;
162 162 CPUReadMemoryFunc *sl_readfn[] = {
163 163 sl_readb,
164 164 sl_readb,
... ... @@ -170,7 +170,7 @@ static void sl_flash_register(struct pxa2xx_state_s *cpu, int size)
170 170 sl_writeb,
171 171 };
172 172  
173   - s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s));
  173 + s = (SLNANDState *) qemu_mallocz(sizeof(SLNANDState));
174 174 s->ctl = 0;
175 175 if (size == FLASH_128M)
176 176 s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
... ... @@ -222,7 +222,7 @@ static const int spitz_gpiomap[5] = {
222 222 };
223 223 static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, };
224 224  
225   -struct spitz_keyboard_s {
  225 +typedef struct {
226 226 qemu_irq sense[SPITZ_KEY_SENSE_NUM];
227 227 qemu_irq *strobe;
228 228 qemu_irq gpiomap[5];
... ... @@ -237,9 +237,9 @@ struct spitz_keyboard_s {
237 237 uint8_t fifo[16];
238 238 int fifopos, fifolen;
239 239 QEMUTimer *kbdtimer;
240   -};
  240 +} SpitzKeyboardState;
241 241  
242   -static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s)
  242 +static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
243 243 {
244 244 int i;
245 245 uint16_t strobe, sense = 0;
... ... @@ -258,7 +258,7 @@ static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s)
258 258  
259 259 static void spitz_keyboard_strobe(void *opaque, int line, int level)
260 260 {
261   - struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
  261 + SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
262 262  
263 263 if (level)
264 264 s->strobe_state |= 1 << line;
... ... @@ -267,7 +267,7 @@ static void spitz_keyboard_strobe(void *opaque, int line, int level)
267 267 spitz_keyboard_sense_update(s);
268 268 }
269 269  
270   -static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode)
  270 +static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
271 271 {
272 272 int spitz_keycode = s->keymap[keycode & 0x7f];
273 273 if (spitz_keycode == -1)
... ... @@ -294,7 +294,7 @@ static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode)
294 294  
295 295 #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
296 296  
297   -static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode)
  297 +static void spitz_keyboard_handler(SpitzKeyboardState *s, int keycode)
298 298 {
299 299 uint16_t code;
300 300 int mapcode;
... ... @@ -386,7 +386,7 @@ static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode)
386 386  
387 387 static void spitz_keyboard_tick(void *opaque)
388 388 {
389   - struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
  389 + SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
390 390  
391 391 if (s->fifolen) {
392 392 spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
... ... @@ -398,7 +398,7 @@ static void spitz_keyboard_tick(void *opaque)
398 398 qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
399 399 }
400 400  
401   -static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s)
  401 +static void spitz_keyboard_pre_map(SpitzKeyboardState *s)
402 402 {
403 403 int i;
404 404 for (i = 0; i < 0x100; i ++)
... ... @@ -450,7 +450,7 @@ static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s)
450 450  
451 451 static void spitz_keyboard_save(QEMUFile *f, void *opaque)
452 452 {
453   - struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
  453 + SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
454 454 int i;
455 455  
456 456 qemu_put_be16s(f, &s->sense_state);
... ... @@ -461,7 +461,7 @@ static void spitz_keyboard_save(QEMUFile *f, void *opaque)
461 461  
462 462 static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id)
463 463 {
464   - struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
  464 + SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
465 465 int i;
466 466  
467 467 qemu_get_be16s(f, &s->sense_state);
... ... @@ -480,14 +480,14 @@ static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id)
480 480 return 0;
481 481 }
482 482  
483   -static void spitz_keyboard_register(struct pxa2xx_state_s *cpu)
  483 +static void spitz_keyboard_register(PXA2xxState *cpu)
484 484 {
485 485 int i, j;
486   - struct spitz_keyboard_s *s;
  486 + SpitzKeyboardState *s;
487 487  
488   - s = (struct spitz_keyboard_s *)
489   - qemu_mallocz(sizeof(struct spitz_keyboard_s));
490   - memset(s, 0, sizeof(struct spitz_keyboard_s));
  488 + s = (SpitzKeyboardState *)
  489 + qemu_mallocz(sizeof(SpitzKeyboardState));
  490 + memset(s, 0, sizeof(SpitzKeyboardState));
491 491  
492 492 for (i = 0; i < 0x80; i ++)
493 493 s->keymap[i] = -1;
... ... @@ -527,7 +527,7 @@ static void spitz_keyboard_register(struct pxa2xx_state_s *cpu)
527 527  
528 528 static int bl_intensity, bl_power;
529 529  
530   -static void spitz_bl_update(struct pxa2xx_state_s *s)
  530 +static void spitz_bl_update(PXA2xxState *s)
531 531 {
532 532 if (bl_power && bl_intensity)
533 533 zaurus_printf("LCD Backlight now at %i/63\n", bl_intensity);
... ... @@ -545,13 +545,13 @@ static inline void spitz_bl_bit5(void *opaque, int line, int level)
545 545 bl_intensity |= 0x20;
546 546  
547 547 if (bl_power && prev != bl_intensity)
548   - spitz_bl_update((struct pxa2xx_state_s *) opaque);
  548 + spitz_bl_update((PXA2xxState *) opaque);
549 549 }
550 550  
551 551 static inline void spitz_bl_power(void *opaque, int line, int level)
552 552 {
553 553 bl_power = !!level;
554   - spitz_bl_update((struct pxa2xx_state_s *) opaque);
  554 + spitz_bl_update((PXA2xxState *) opaque);
555 555 }
556 556  
557 557 static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd)
... ... @@ -572,7 +572,7 @@ static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd)
572 572 bl_intensity &= ~0x1f;
573 573 bl_intensity |= value;
574 574 if (bl_power)
575   - spitz_bl_update((struct pxa2xx_state_s *) opaque);
  575 + spitz_bl_update((PXA2xxState *) opaque);
576 576 break;
577 577  
578 578 case LCDTG_POWERREG0:
... ... @@ -591,8 +591,8 @@ static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd)
591 591 #define SPITZ_GPIO_TP_INT 11
592 592  
593 593 static int lcd_en, ads_en, max_en;
594   -static struct max111x_s *max1111;
595   -static struct ads7846_state_s *ads7846;
  594 +static MAX111xState *max1111;
  595 +static ADS7846State *ads7846;
596 596  
597 597 /* "Demux" the signal based on current chipselect */
598 598 static uint32_t corgi_ssp_read(void *opaque)
... ... @@ -670,7 +670,7 @@ static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id)
670 670 return 0;
671 671 }
672 672  
673   -static void spitz_ssp_attach(struct pxa2xx_state_s *cpu)
  673 +static void spitz_ssp_attach(PXA2xxState *cpu)
674 674 {
675 675 qemu_irq *chipselects;
676 676  
... ... @@ -699,9 +699,9 @@ static void spitz_ssp_attach(struct pxa2xx_state_s *cpu)
699 699  
700 700 /* CF Microdrive */
701 701  
702   -static void spitz_microdrive_attach(struct pxa2xx_state_s *cpu, int slot)
  702 +static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
703 703 {
704   - struct pcmcia_card_s *md;
  704 + PCMCIACardState *md;
705 705 int index;
706 706 BlockDriverState *bs;
707 707  
... ... @@ -734,7 +734,7 @@ static void spitz_wm8750_addr(void *opaque, int line, int level)
734 734 }
735 735 #endif
736 736  
737   -static void spitz_i2c_setup(struct pxa2xx_state_s *cpu)
  737 +static void spitz_i2c_setup(PXA2xxState *cpu)
738 738 {
739 739 /* Attach the CPU on one end of our I2C bus. */
740 740 i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
... ... @@ -760,7 +760,7 @@ static void spitz_i2c_setup(struct pxa2xx_state_s *cpu)
760 760 #endif
761 761 }
762 762  
763   -static void spitz_akita_i2c_setup(struct pxa2xx_state_s *cpu)
  763 +static void spitz_akita_i2c_setup(PXA2xxState *cpu)
764 764 {
765 765 /* Attach a Max7310 to Akita I2C bus. */
766 766 i2c_set_slave_address(max7310_init(pxa2xx_i2c_bus(cpu->i2c[0])),
... ... @@ -811,8 +811,8 @@ static void spitz_out_switch(void *opaque, int line, int level)
811 811 #define SPITZ_SCP2_BACKLIGHT_ON 8
812 812 #define SPITZ_SCP2_MIC_BIAS 9
813 813  
814   -static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu,
815   - struct scoop_info_s *scp0, struct scoop_info_s *scp1)
  814 +static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
  815 + ScoopInfo *scp0, ScoopInfo *scp1)
816 816 {
817 817 qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
818 818  
... ... @@ -843,12 +843,12 @@ static int spitz_hsync;
843 843  
844 844 static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
845 845 {
846   - struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
  846 + PXA2xxState *cpu = (PXA2xxState *) opaque;
847 847 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync);
848 848 spitz_hsync ^= 1;
849 849 }
850 850  
851   -static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots)
  851 +static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
852 852 {
853 853 qemu_irq lcd_hsync;
854 854 /*
... ... @@ -912,8 +912,8 @@ static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size,
912 912 const char *kernel_cmdline, const char *initrd_filename,
913 913 const char *cpu_model, enum spitz_model_e model, int arm_id)
914 914 {
915   - struct pxa2xx_state_s *cpu;
916   - struct scoop_info_s *scp0, *scp1 = NULL;
  915 + PXA2xxState *cpu;
  916 + ScoopInfo *scp0, *scp1 = NULL;
917 917  
918 918 if (!cpu_model)
919 919 cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
... ...
hw/ssi-sd.c
  View file @bc24a22
... ... @@ -82,7 +82,7 @@ int ssi_sd_xfer(void *opaque, int val)
82 82 return 0xff;
83 83 case SSI_SD_CMDARG:
84 84 if (s->arglen == 4) {
85   - struct sd_request_s request;
  85 + SDRequest request;
86 86 uint8_t longresp[16];
87 87 /* FIXME: Check CRC. */
88 88 request.cmd = s->cmd;
... ...
hw/tc6393xb.c
  View file @bc24a22
... ... @@ -78,7 +78,7 @@
78 78 #define NAND_MODE_ECC_READ 0x40
79 79 #define NAND_MODE_ECC_RST 0x60
80 80  
81   -struct tc6393xb_s {
  81 +struct TC6393xbState {
82 82 qemu_irq irq;
83 83 qemu_irq *sub_irqs;
84 84 struct {
... ... @@ -118,8 +118,8 @@ struct tc6393xb_s {
118 118 } nand;
119 119 int nand_enable;
120 120 uint32_t nand_phys;
121   - struct nand_flash_s *flash;
122   - struct ecc_state_s ecc;
  121 + NANDFlashState *flash;
  122 + ECCState ecc;
123 123  
124 124 DisplayState *ds;
125 125 ram_addr_t vram_addr;
... ... @@ -130,14 +130,14 @@ struct tc6393xb_s {
130 130 blanked : 1;
131 131 };
132 132  
133   -qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s)
  133 +qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s)
134 134 {
135 135 return s->gpio_in;
136 136 }
137 137  
138 138 static void tc6393xb_gpio_set(void *opaque, int line, int level)
139 139 {
140   -// struct tc6393xb_s *s = opaque;
  140 +// TC6393xbState *s = opaque;
141 141  
142 142 if (line > TC6393XB_GPIOS) {
143 143 printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
... ... @@ -147,7 +147,7 @@ static void tc6393xb_gpio_set(void *opaque, int line, int level)
147 147 // FIXME: how does the chip reflect the GPIO input level change?
148 148 }
149 149  
150   -void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line,
  150 +void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
151 151 qemu_irq handler)
152 152 {
153 153 if (line >= TC6393XB_GPIOS) {
... ... @@ -158,7 +158,7 @@ void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line,
158 158 s->handler[line] = handler;
159 159 }
160 160  
161   -static void tc6393xb_gpio_handler_update(struct tc6393xb_s *s)
  161 +static void tc6393xb_gpio_handler_update(TC6393xbState *s)
162 162 {
163 163 uint32_t level, diff;
164 164 int bit;
... ... @@ -173,20 +173,20 @@ static void tc6393xb_gpio_handler_update(struct tc6393xb_s *s)
173 173 s->prev_level = level;
174 174 }
175 175  
176   -qemu_irq tc6393xb_l3v_get(struct tc6393xb_s *s)
  176 +qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
177 177 {
178 178 return s->l3v;
179 179 }
180 180  
181 181 static void tc6393xb_l3v(void *opaque, int line, int level)
182 182 {
183   - struct tc6393xb_s *s = opaque;
  183 + TC6393xbState *s = opaque;
184 184 s->blank = !level;
185 185 fprintf(stderr, "L3V: %d\n", level);
186 186 }
187 187  
188 188 static void tc6393xb_sub_irq(void *opaque, int line, int level) {
189   - struct tc6393xb_s *s = opaque;
  189 + TC6393xbState *s = opaque;
190 190 uint8_t isr = s->scr.ISR;
191 191 if (level)
192 192 isr |= 1 << line;
... ... @@ -211,7 +211,7 @@ static void tc6393xb_sub_irq(void *opaque, int line, int level) {
211 211 case SCR_ ##N(1): return s->scr.N[1]; \
212 212 case SCR_ ##N(2): return s->scr.N[2]
213 213  
214   -static uint32_t tc6393xb_scr_readb(struct tc6393xb_s *s, target_phys_addr_t addr)
  214 +static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr)
215 215 {
216 216 switch (addr) {
217 217 case SCR_REVID:
... ... @@ -272,7 +272,7 @@ static uint32_t tc6393xb_scr_readb(struct tc6393xb_s *s, target_phys_addr_t addr
272 272 case SCR_ ##N(1): s->scr.N[1] = value; return; \
273 273 case SCR_ ##N(2): s->scr.N[2] = value; return
274 274  
275   -static void tc6393xb_scr_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value)
  275 +static void tc6393xb_scr_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value)
276 276 {
277 277 switch (addr) {
278 278 SCR_REG_B(ISR);
... ... @@ -318,12 +318,12 @@ static void tc6393xb_scr_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, u
318 318 #undef SCR_REG_L
319 319 #undef SCR_REG_A
320 320  
321   -static void tc6393xb_nand_irq(struct tc6393xb_s *s) {
  321 +static void tc6393xb_nand_irq(TC6393xbState *s) {
322 322 qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND],
323 323 (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
324 324 }
325 325  
326   -static uint32_t tc6393xb_nand_cfg_readb(struct tc6393xb_s *s, target_phys_addr_t addr) {
  326 +static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t addr) {
327 327 switch (addr) {
328 328 case NAND_CFG_COMMAND:
329 329 return s->nand_enable ? 2 : 0;
... ... @@ -336,7 +336,7 @@ static uint32_t tc6393xb_nand_cfg_readb(struct tc6393xb_s *s, target_phys_addr_t
336 336 fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
337 337 return 0;
338 338 }
339   -static void tc6393xb_nand_cfg_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) {
  339 +static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
340 340 switch (addr) {
341 341 case NAND_CFG_COMMAND:
342 342 s->nand_enable = (value & 0x2);
... ... @@ -353,7 +353,7 @@ static void tc6393xb_nand_cfg_writeb(struct tc6393xb_s *s, target_phys_addr_t ad
353 353 (uint32_t) addr, value & 0xff);
354 354 }
355 355  
356   -static uint32_t tc6393xb_nand_readb(struct tc6393xb_s *s, target_phys_addr_t addr) {
  356 +static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr) {
357 357 switch (addr) {
358 358 case NAND_DATA + 0:
359 359 case NAND_DATA + 1:
... ... @@ -372,7 +372,7 @@ static uint32_t tc6393xb_nand_readb(struct tc6393xb_s *s, target_phys_addr_t add
372 372 fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
373 373 return 0;
374 374 }
375   -static void tc6393xb_nand_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) {
  375 +static void tc6393xb_nand_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
376 376 // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
377 377 // (uint32_t) addr, value & 0xff);
378 378 switch (addr) {
... ... @@ -427,7 +427,7 @@ static void tc6393xb_nand_writeb(struct tc6393xb_s *s, target_phys_addr_t addr,
427 427 #define BITS 32
428 428 #include "tc6393xb_template.h"
429 429  
430   -static void tc6393xb_draw_graphic(struct tc6393xb_s *s, int full_update)
  430 +static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
431 431 {
432 432 switch (ds_get_bits_per_pixel(s->ds)) {
433 433 case 8:
... ... @@ -453,7 +453,7 @@ static void tc6393xb_draw_graphic(struct tc6393xb_s *s, int full_update)
453 453 dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
454 454 }
455 455  
456   -static void tc6393xb_draw_blank(struct tc6393xb_s *s, int full_update)
  456 +static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
457 457 {
458 458 int i, w;
459 459 uint8_t *d;
... ... @@ -473,7 +473,7 @@ static void tc6393xb_draw_blank(struct tc6393xb_s *s, int full_update)
473 473  
474 474 static void tc6393xb_update_display(void *opaque)
475 475 {
476   - struct tc6393xb_s *s = opaque;
  476 + TC6393xbState *s = opaque;
477 477 int full_update;
478 478  
479 479 if (s->scr_width == 0 || s->scr_height == 0)
... ... @@ -496,7 +496,7 @@ static void tc6393xb_update_display(void *opaque)
496 496  
497 497  
498 498 static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) {
499   - struct tc6393xb_s *s = opaque;
  499 + TC6393xbState *s = opaque;
500 500  
501 501 switch (addr >> 8) {
502 502 case 0:
... ... @@ -517,7 +517,7 @@ static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) {
517 517 }
518 518  
519 519 static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) {
520   - struct tc6393xb_s *s = opaque;
  520 + TC6393xbState *s = opaque;
521 521  
522 522 switch (addr >> 8) {
523 523 case 0:
... ... @@ -563,10 +563,10 @@ static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t valu
563 563 tc6393xb_writeb(opaque, addr + 3, value >> 24);
564 564 }
565 565  
566   -struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq)
  566 +TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq)
567 567 {
568 568 int iomemtype;
569   - struct tc6393xb_s *s;
  569 + TC6393xbState *s;
570 570 CPUReadMemoryFunc *tc6393xb_readfn[] = {
571 571 tc6393xb_readb,
572 572 tc6393xb_readw,
... ... @@ -578,7 +578,7 @@ struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq)
578 578 tc6393xb_writel,
579 579 };
580 580  
581   - s = (struct tc6393xb_s *) qemu_mallocz(sizeof(struct tc6393xb_s));
  581 + s = (TC6393xbState *) qemu_mallocz(sizeof(TC6393xbState));
582 582 s->irq = irq;
583 583 s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
584 584  
... ...
hw/tc6393xb_template.h
  View file @bc24a22
... ... @@ -36,7 +36,7 @@
36 36 #endif
37 37  
38 38  
39   -static void glue(tc6393xb_draw_graphic, BITS)(struct tc6393xb_s *s)
  39 +static void glue(tc6393xb_draw_graphic, BITS)(TC6393xbState *s)
40 40 {
41 41 int i;
42 42 int w_display;
... ...
hw/tmp105.c
  View file @bc24a22
... ... @@ -22,7 +22,7 @@
22 22 #include "hw.h"
23 23 #include "i2c.h"
24 24  
25   -struct tmp105_s {
  25 +typedef struct {
26 26 i2c_slave i2c;
27 27 int len;
28 28 uint8_t buf[2];
... ... @@ -34,14 +34,14 @@ struct tmp105_s {
34 34 int16_t limit[2];
35 35 int faults;
36 36 int alarm;
37   -};
  37 +} TMP105State;
38 38  
39   -static void tmp105_interrupt_update(struct tmp105_s *s)
  39 +static void tmp105_interrupt_update(TMP105State *s)
40 40 {
41 41 qemu_set_irq(s->pin, s->alarm ^ ((~s->config >> 2) & 1)); /* POL */
42 42 }
43 43  
44   -static void tmp105_alarm_update(struct tmp105_s *s)
  44 +static void tmp105_alarm_update(TMP105State *s)
45 45 {
46 46 if ((s->config >> 0) & 1) { /* SD */
47 47 if ((s->config >> 7) & 1) /* OS */
... ... @@ -68,7 +68,7 @@ static void tmp105_alarm_update(struct tmp105_s *s)
68 68 /* Units are 0.001 centigrades relative to 0 C. */
69 69 void tmp105_set(i2c_slave *i2c, int temp)
70 70 {
71   - struct tmp105_s *s = (struct tmp105_s *) i2c;
  71 + TMP105State *s = (TMP105State *) i2c;
72 72  
73 73 if (temp >= 128000 || temp < -128000) {
74 74 fprintf(stderr, "%s: values is out of range (%i.%03i C)\n",
... ... @@ -83,7 +83,7 @@ void tmp105_set(i2c_slave *i2c, int temp)
83 83  
84 84 static const int tmp105_faultq[4] = { 1, 2, 4, 6 };
85 85  
86   -static void tmp105_read(struct tmp105_s *s)
  86 +static void tmp105_read(TMP105State *s)
87 87 {
88 88 s->len = 0;
89 89  
... ... @@ -115,7 +115,7 @@ static void tmp105_read(struct tmp105_s *s)
115 115 }
116 116 }
117 117  
118   -static void tmp105_write(struct tmp105_s *s)
  118 +static void tmp105_write(TMP105State *s)
119 119 {
120 120 switch (s->pointer & 3) {
121 121 case 0: /* Temperature */
... ... @@ -141,7 +141,7 @@ static void tmp105_write(struct tmp105_s *s)
141 141  
142 142 static int tmp105_rx(i2c_slave *i2c)
143 143 {
144   - struct tmp105_s *s = (struct tmp105_s *) i2c;
  144 + TMP105State *s = (TMP105State *) i2c;
145 145  
146 146 if (s->len < 2)
147 147 return s->buf[s->len ++];
... ... @@ -151,7 +151,7 @@ static int tmp105_rx(i2c_slave *i2c)
151 151  
152 152 static int tmp105_tx(i2c_slave *i2c, uint8_t data)
153 153 {
154   - struct tmp105_s *s = (struct tmp105_s *) i2c;
  154 + TMP105State *s = (TMP105State *) i2c;
155 155  
156 156 if (!s->len ++)
157 157 s->pointer = data;
... ... @@ -166,7 +166,7 @@ static int tmp105_tx(i2c_slave *i2c, uint8_t data)
166 166  
167 167 static void tmp105_event(i2c_slave *i2c, enum i2c_event event)
168 168 {
169   - struct tmp105_s *s = (struct tmp105_s *) i2c;
  169 + TMP105State *s = (TMP105State *) i2c;
170 170  
171 171 if (event == I2C_START_RECV)
172 172 tmp105_read(s);
... ... @@ -176,7 +176,7 @@ static void tmp105_event(i2c_slave *i2c, enum i2c_event event)
176 176  
177 177 static void tmp105_save(QEMUFile *f, void *opaque)
178 178 {
179   - struct tmp105_s *s = (struct tmp105_s *) opaque;
  179 + TMP105State *s = (TMP105State *) opaque;
180 180  
181 181 qemu_put_byte(f, s->len);
182 182 qemu_put_8s(f, &s->buf[0]);
... ... @@ -195,7 +195,7 @@ static void tmp105_save(QEMUFile *f, void *opaque)
195 195  
196 196 static int tmp105_load(QEMUFile *f, void *opaque, int version_id)
197 197 {
198   - struct tmp105_s *s = (struct tmp105_s *) opaque;
  198 + TMP105State *s = (TMP105State *) opaque;
199 199  
200 200 s->len = qemu_get_byte(f);
201 201 qemu_get_8s(f, &s->buf[0]);
... ... @@ -216,7 +216,7 @@ static int tmp105_load(QEMUFile *f, void *opaque, int version_id)
216 216  
217 217 void tmp105_reset(i2c_slave *i2c)
218 218 {
219   - struct tmp105_s *s = (struct tmp105_s *) i2c;
  219 + TMP105State *s = (TMP105State *) i2c;
220 220  
221 221 s->temperature = 0;
222 222 s->pointer = 0;
... ... @@ -229,8 +229,8 @@ void tmp105_reset(i2c_slave *i2c)
229 229  
230 230 struct i2c_slave *tmp105_init(i2c_bus *bus, qemu_irq alarm)
231 231 {
232   - struct tmp105_s *s = (struct tmp105_s *)
233   - i2c_slave_init(bus, 0, sizeof(struct tmp105_s));
  232 + TMP105State *s = (TMP105State *)
  233 + i2c_slave_init(bus, 0, sizeof(TMP105State));
234 234  
235 235 s->i2c.event = tmp105_event;
236 236 s->i2c.recv = tmp105_rx;
... ...
hw/tosa.c
  View file @bc24a22
... ... @@ -45,9 +45,9 @@
45 45 #define DAC_CH1 0
46 46 #define DAC_CH2 1
47 47  
48   -static void tosa_microdrive_attach(struct pxa2xx_state_s *cpu)
  48 +static void tosa_microdrive_attach(PXA2xxState *cpu)
49 49 {
50   - struct pcmcia_card_s *md;
  50 + PCMCIACardState *md;
51 51 int index;
52 52 BlockDriverState *bs;
53 53  
... ... @@ -83,10 +83,10 @@ static void tosa_out_switch(void *opaque, int line, int level)
83 83 }
84 84  
85 85  
86   -static void tosa_gpio_setup(struct pxa2xx_state_s *cpu,
87   - struct scoop_info_s *scp0,
88   - struct scoop_info_s *scp1,
89   - struct tc6393xb_s *tmio)
  86 +static void tosa_gpio_setup(PXA2xxState *cpu,
  87 + ScoopInfo *scp0,
  88 + ScoopInfo *scp1,
  89 + TC6393xbState *tmio)
90 90 {
91 91 qemu_irq *outsignals = qemu_allocate_irqs(tosa_out_switch, cpu, 4);
92 92 /* MMC/SD host */
... ... @@ -178,7 +178,7 @@ static int tosa_dac_recv(i2c_slave *s)
178 178 return -1;
179 179 }
180 180  
181   -static void tosa_tg_init(struct pxa2xx_state_s *cpu)
  181 +static void tosa_tg_init(PXA2xxState *cpu)
182 182 {
183 183 struct i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
184 184 struct i2c_slave *dac = i2c_slave_init(bus, 0, sizeof(struct tosa_dac_i2c));
... ... @@ -201,9 +201,9 @@ static void tosa_init(ram_addr_t ram_size, int vga_ram_size,
201 201 const char *kernel_filename, const char *kernel_cmdline,
202 202 const char *initrd_filename, const char *cpu_model)
203 203 {
204   - struct pxa2xx_state_s *cpu;
205   - struct tc6393xb_s *tmio;
206   - struct scoop_info_s *scp0, *scp1;
  204 + PXA2xxState *cpu;
  205 + TC6393xbState *tmio;
  206 + ScoopInfo *scp0, *scp1;
207 207  
208 208 if (!cpu_model)
209 209 cpu_model = "pxa255";
... ...
hw/tsc2005.c
  View file @bc24a22
... ... @@ -26,7 +26,7 @@
26 26  
27 27 #define TSC_CUT_RESOLUTION(value, p) ((value) >> (16 - (p ? 12 : 10)))
28 28  
29   -struct tsc2005_state_s {
  29 +typedef struct {
30 30 qemu_irq pint; /* Combination of the nPENIRQ and DAV signals */
31 31 QEMUTimer *timer;
32 32 uint16_t model;
... ... @@ -55,7 +55,7 @@ struct tsc2005_state_s {
55 55 uint16_t aux_thr[2];
56 56  
57 57 int tr[8];
58   -};
  58 +} TSC2005State;
59 59  
60 60 enum {
61 61 TSC_MODE_XYZ_SCAN = 0x0,
... ... @@ -108,7 +108,7 @@ static const uint16_t mode_regs[16] = {
108 108 #define TEMP1_VAL (1264 << 4) /* +/- 5 at 12-bit */
109 109 #define TEMP2_VAL (1531 << 4) /* +/- 5 at 12-bit */
110 110  
111   -static uint16_t tsc2005_read(struct tsc2005_state_s *s, int reg)
  111 +static uint16_t tsc2005_read(TSC2005State *s, int reg)
112 112 {
113 113 uint16_t ret;
114 114  
... ... @@ -178,7 +178,7 @@ static uint16_t tsc2005_read(struct tsc2005_state_s *s, int reg)
178 178 return 0xffff;
179 179 }
180 180  
181   -static void tsc2005_write(struct tsc2005_state_s *s, int reg, uint16_t data)
  181 +static void tsc2005_write(TSC2005State *s, int reg, uint16_t data)
182 182 {
183 183 switch (reg) {
184 184 case 0x8: /* AUX high treshold */
... ... @@ -226,7 +226,7 @@ static void tsc2005_write(struct tsc2005_state_s *s, int reg, uint16_t data)
226 226 }
227 227  
228 228 /* This handles most of the chip's logic. */
229   -static void tsc2005_pin_update(struct tsc2005_state_s *s)
  229 +static void tsc2005_pin_update(TSC2005State *s)
230 230 {
231 231 int64_t expires;
232 232 int pin_state;
... ... @@ -295,7 +295,7 @@ static void tsc2005_pin_update(struct tsc2005_state_s *s)
295 295 qemu_mod_timer(s->timer, expires);
296 296 }
297 297  
298   -static void tsc2005_reset(struct tsc2005_state_s *s)
  298 +static void tsc2005_reset(TSC2005State *s)
299 299 {
300 300 s->state = 0;
301 301 s->pin_func = 0;
... ... @@ -321,7 +321,7 @@ static void tsc2005_reset(struct tsc2005_state_s *s)
321 321  
322 322 static uint8_t tsc2005_txrx_word(void *opaque, uint8_t value)
323 323 {
324   - struct tsc2005_state_s *s = opaque;
  324 + TSC2005State *s = opaque;
325 325 uint32_t ret = 0;
326 326  
327 327 switch (s->state ++) {
... ... @@ -399,7 +399,7 @@ uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len)
399 399  
400 400 static void tsc2005_timer_tick(void *opaque)
401 401 {
402   - struct tsc2005_state_s *s = opaque;
  402 + TSC2005State *s = opaque;
403 403  
404 404 /* Timer ticked -- a set of conversions has been finished. */
405 405  
... ... @@ -415,7 +415,7 @@ static void tsc2005_timer_tick(void *opaque)
415 415 static void tsc2005_touchscreen_event(void *opaque,
416 416 int x, int y, int z, int buttons_state)
417 417 {
418   - struct tsc2005_state_s *s = opaque;
  418 + TSC2005State *s = opaque;
419 419 int p = s->pressure;
420 420  
421 421 if (buttons_state) {
... ... @@ -435,7 +435,7 @@ static void tsc2005_touchscreen_event(void *opaque,
435 435  
436 436 static void tsc2005_save(QEMUFile *f, void *opaque)
437 437 {
438   - struct tsc2005_state_s *s = (struct tsc2005_state_s *) opaque;
  438 + TSC2005State *s = (TSC2005State *) opaque;
439 439 int i;
440 440  
441 441 qemu_put_be16(f, s->x);
... ... @@ -476,7 +476,7 @@ static void tsc2005_save(QEMUFile *f, void *opaque)
476 476  
477 477 static int tsc2005_load(QEMUFile *f, void *opaque, int version_id)
478 478 {
479   - struct tsc2005_state_s *s = (struct tsc2005_state_s *) opaque;
  479 + TSC2005State *s = (TSC2005State *) opaque;
480 480 int i;
481 481  
482 482 s->x = qemu_get_be16(f);
... ... @@ -522,10 +522,10 @@ static int tsc2005_load(QEMUFile *f, void *opaque, int version_id)
522 522  
523 523 void *tsc2005_init(qemu_irq pintdav)
524 524 {
525   - struct tsc2005_state_s *s;
  525 + TSC2005State *s;
526 526  
527   - s = (struct tsc2005_state_s *)
528   - qemu_mallocz(sizeof(struct tsc2005_state_s));
  527 + s = (TSC2005State *)
  528 + qemu_mallocz(sizeof(TSC2005State));
529 529 s->x = 400;
530 530 s->y = 240;
531 531 s->pressure = 0;
... ... @@ -559,9 +559,9 @@ void *tsc2005_init(qemu_irq pintdav)
559 559 * from the touchscreen. Assuming 12-bit precision was used during
560 560 * tslib calibration.
561 561 */
562   -void tsc2005_set_transform(void *opaque, struct mouse_transform_info_s *info)
  562 +void tsc2005_set_transform(void *opaque, MouseTransformInfo *info)
563 563 {
564   - struct tsc2005_state_s *s = (struct tsc2005_state_s *) opaque;
  564 + TSC2005State *s = (TSC2005State *) opaque;
565 565  
566 566 /* This version assumes touchscreen X & Y axis are parallel or
567 567 * perpendicular to LCD's X & Y axis in some way. */
... ...
hw/tsc210x.c
  View file @bc24a22
... ... @@ -24,7 +24,7 @@
24 24 #include "audio/audio.h"
25 25 #include "qemu-timer.h"
26 26 #include "console.h"
27   -#include "omap.h" /* For struct i2s_codec_s and struct uwire_slave_s */
  27 +#include "omap.h" /* For I2SCodec and uWireSlave */
28 28 #include "devices.h"
29 29  
30 30 #define TSC_DATA_REGISTERS_PAGE 0x0
... ... @@ -35,14 +35,14 @@
35 35  
36 36 #define TSC_CUT_RESOLUTION(value, p) ((value) >> (16 - resolution[p]))
37 37  
38   -struct tsc210x_state_s {
  38 +typedef struct {
39 39 qemu_irq pint;
40 40 qemu_irq kbint;
41 41 qemu_irq davint;
42 42 QEMUTimer *timer;
43 43 QEMUSoundCard card;
44   - struct uwire_slave_s chip;
45   - struct i2s_codec_s codec;
  44 + uWireSlave chip;
  45 + I2SCodec codec;
46 46 uint8_t in_fifo[16384];
47 47 uint8_t out_fifo[16384];
48 48 uint16_t model;
... ... @@ -94,7 +94,7 @@ struct tsc210x_state_s {
94 94 int mode;
95 95 int intr;
96 96 } kb;
97   -};
  97 +} TSC210xState;
98 98  
99 99 static const int resolution[4] = { 12, 8, 10, 12 };
100 100  
... ... @@ -153,7 +153,7 @@ static const uint16_t mode_regs[16] = {
153 153 #define TSC_POWEROFF_DELAY 50
154 154 #define TSC_SOFTSTEP_DELAY 50
155 155  
156   -static void tsc210x_reset(struct tsc210x_state_s *s)
  156 +static void tsc210x_reset(TSC210xState *s)
157 157 {
158 158 s->state = 0;
159 159 s->pin_func = 2;
... ... @@ -211,14 +211,14 @@ static void tsc210x_reset(struct tsc210x_state_s *s)
211 211 qemu_irq_raise(s->kbint);
212 212 }
213 213  
214   -struct tsc210x_rate_info_s {
  214 +typedef struct {
215 215 int rate;
216 216 int dsor;
217 217 int fsref;
218   -};
  218 +} TSC210xRateInfo;
219 219  
220 220 /* { rate, dsor, fsref } */
221   -static const struct tsc210x_rate_info_s tsc2101_rates[] = {
  221 +static const TSC210xRateInfo tsc2101_rates[] = {
222 222 /* Fsref / 6.0 */
223 223 { 7350, 7, 1 },
224 224 { 8000, 7, 0 },
... ... @@ -248,7 +248,7 @@ static const struct tsc210x_rate_info_s tsc2101_rates[] = {
248 248 };
249 249  
250 250 /* { rate, dsor, fsref } */
251   -static const struct tsc210x_rate_info_s tsc2102_rates[] = {
  251 +static const TSC210xRateInfo tsc2102_rates[] = {
252 252 /* Fsref / 6.0 */
253 253 { 7350, 63, 1 },
254 254 { 8000, 63, 0 },
... ... @@ -277,7 +277,7 @@ static const struct tsc210x_rate_info_s tsc2102_rates[] = {
277 277 { 0, 0, 0 },
278 278 };
279 279  
280   -static inline void tsc210x_out_flush(struct tsc210x_state_s *s, int len)
  280 +static inline void tsc210x_out_flush(TSC210xState *s, int len)
281 281 {
282 282 uint8_t *data = s->codec.out.fifo + s->codec.out.start;
283 283 uint8_t *end = data + len;
... ... @@ -291,7 +291,7 @@ static inline void tsc210x_out_flush(struct tsc210x_state_s *s, int len)
291 291 s->codec.out.start = 0;
292 292 }
293 293  
294   -static void tsc210x_audio_out_cb(struct tsc210x_state_s *s, int free_b)
  294 +static void tsc210x_audio_out_cb(TSC210xState *s, int free_b)
295 295 {
296 296 if (s->codec.out.len >= free_b) {
297 297 tsc210x_out_flush(s, free_b);
... ... @@ -302,9 +302,9 @@ static void tsc210x_audio_out_cb(struct tsc210x_state_s *s, int free_b)
302 302 qemu_irq_raise(s->codec.tx_start);
303 303 }
304 304  
305   -static void tsc2102_audio_rate_update(struct tsc210x_state_s *s)
  305 +static void tsc2102_audio_rate_update(TSC210xState *s)
306 306 {
307   - const struct tsc210x_rate_info_s *rate;
  307 + const TSC210xRateInfo *rate;
308 308  
309 309 s->codec.tx_rate = 0;
310 310 s->codec.rx_rate = 0;
... ... @@ -323,7 +323,7 @@ static void tsc2102_audio_rate_update(struct tsc210x_state_s *s)
323 323 s->codec.tx_rate = rate->rate;
324 324 }
325 325  
326   -static void tsc2102_audio_output_update(struct tsc210x_state_s *s)
  326 +static void tsc2102_audio_output_update(TSC210xState *s)
327 327 {
328 328 int enable;
329 329 struct audsettings fmt;
... ... @@ -357,7 +357,7 @@ static void tsc2102_audio_output_update(struct tsc210x_state_s *s)
357 357 }
358 358 }
359 359  
360   -static uint16_t tsc2102_data_register_read(struct tsc210x_state_s *s, int reg)
  360 +static uint16_t tsc2102_data_register_read(TSC210xState *s, int reg)
361 361 {
362 362 switch (reg) {
363 363 case 0x00: /* X */
... ... @@ -433,7 +433,7 @@ static uint16_t tsc2102_data_register_read(struct tsc210x_state_s *s, int reg)
433 433 }
434 434  
435 435 static uint16_t tsc2102_control_register_read(
436   - struct tsc210x_state_s *s, int reg)
  436 + TSC210xState *s, int reg)
437 437 {
438 438 switch (reg) {
439 439 case 0x00: /* TSC ADC */
... ... @@ -483,7 +483,7 @@ static uint16_t tsc2102_control_register_read(
483 483 }
484 484 }
485 485  
486   -static uint16_t tsc2102_audio_register_read(struct tsc210x_state_s *s, int reg)
  486 +static uint16_t tsc2102_audio_register_read(TSC210xState *s, int reg)
487 487 {
488 488 int l_ch, r_ch;
489 489 uint16_t val;
... ... @@ -565,7 +565,7 @@ static uint16_t tsc2102_audio_register_read(struct tsc210x_state_s *s, int reg)
565 565 }
566 566  
567 567 static void tsc2102_data_register_write(
568   - struct tsc210x_state_s *s, int reg, uint16_t value)
  568 + TSC210xState *s, int reg, uint16_t value)
569 569 {
570 570 switch (reg) {
571 571 case 0x00: /* X */
... ... @@ -589,7 +589,7 @@ static void tsc2102_data_register_write(
589 589 }
590 590  
591 591 static void tsc2102_control_register_write(
592   - struct tsc210x_state_s *s, int reg, uint16_t value)
  592 + TSC210xState *s, int reg, uint16_t value)
593 593 {
594 594 switch (reg) {
595 595 case 0x00: /* TSC ADC */
... ... @@ -673,7 +673,7 @@ static void tsc2102_control_register_write(
673 673 }
674 674  
675 675 static void tsc2102_audio_register_write(
676   - struct tsc210x_state_s *s, int reg, uint16_t value)
  676 + TSC210xState *s, int reg, uint16_t value)
677 677 {
678 678 switch (reg) {
679 679 case 0x00: /* Audio Control 1 */
... ... @@ -804,7 +804,7 @@ static void tsc2102_audio_register_write(
804 804 }
805 805  
806 806 /* This handles most of the chip logic. */
807   -static void tsc210x_pin_update(struct tsc210x_state_s *s)
  807 +static void tsc210x_pin_update(TSC210xState *s)
808 808 {
809 809 int64_t expires;
810 810 int pin_state;
... ... @@ -873,7 +873,7 @@ static void tsc210x_pin_update(struct tsc210x_state_s *s)
873 873 qemu_mod_timer(s->timer, expires);
874 874 }
875 875  
876   -static uint16_t tsc210x_read(struct tsc210x_state_s *s)
  876 +static uint16_t tsc210x_read(TSC210xState *s)
877 877 {
878 878 uint16_t ret = 0x0000;
879 879  
... ... @@ -904,7 +904,7 @@ static uint16_t tsc210x_read(struct tsc210x_state_s *s)
904 904 return ret;
905 905 }
906 906  
907   -static void tsc210x_write(struct tsc210x_state_s *s, uint16_t value)
  907 +static void tsc210x_write(TSC210xState *s, uint16_t value)
908 908 {
909 909 /*
910 910 * This is a two-state state machine for reading
... ... @@ -940,7 +940,7 @@ static void tsc210x_write(struct tsc210x_state_s *s, uint16_t value)
940 940  
941 941 uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len)
942 942 {
943   - struct tsc210x_state_s *s = opaque;
  943 + TSC210xState *s = opaque;
944 944 uint32_t ret = 0;
945 945  
946 946 if (len != 16)
... ... @@ -959,7 +959,7 @@ uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len)
959 959  
960 960 static void tsc210x_timer_tick(void *opaque)
961 961 {
962   - struct tsc210x_state_s *s = opaque;
  962 + TSC210xState *s = opaque;
963 963  
964 964 /* Timer ticked -- a set of conversions has been finished. */
965 965  
... ... @@ -975,7 +975,7 @@ static void tsc210x_timer_tick(void *opaque)
975 975 static void tsc210x_touchscreen_event(void *opaque,
976 976 int x, int y, int z, int buttons_state)
977 977 {
978   - struct tsc210x_state_s *s = opaque;
  978 + TSC210xState *s = opaque;
979 979 int p = s->pressure;
980 980  
981 981 if (buttons_state) {
... ... @@ -993,7 +993,7 @@ static void tsc210x_touchscreen_event(void *opaque,
993 993 tsc210x_pin_update(s);
994 994 }
995 995  
996   -static void tsc210x_i2s_swallow(struct tsc210x_state_s *s)
  996 +static void tsc210x_i2s_swallow(TSC210xState *s)
997 997 {
998 998 if (s->dac_voice[0])
999 999 tsc210x_out_flush(s, s->codec.out.len);
... ... @@ -1001,7 +1001,7 @@ static void tsc210x_i2s_swallow(struct tsc210x_state_s *s)
1001 1001 s->codec.out.len = 0;
1002 1002 }
1003 1003  
1004   -static void tsc210x_i2s_set_rate(struct tsc210x_state_s *s, int in, int out)
  1004 +static void tsc210x_i2s_set_rate(TSC210xState *s, int in, int out)
1005 1005 {
1006 1006 s->i2s_tx_rate = out;
1007 1007 s->i2s_rx_rate = in;
... ... @@ -1009,7 +1009,7 @@ static void tsc210x_i2s_set_rate(struct tsc210x_state_s *s, int in, int out)
1009 1009  
1010 1010 static void tsc210x_save(QEMUFile *f, void *opaque)
1011 1011 {
1012   - struct tsc210x_state_s *s = (struct tsc210x_state_s *) opaque;
  1012 + TSC210xState *s = (TSC210xState *) opaque;
1013 1013 int64_t now = qemu_get_clock(vm_clock);
1014 1014 int i;
1015 1015  
... ... @@ -1055,7 +1055,7 @@ static void tsc210x_save(QEMUFile *f, void *opaque)
1055 1055  
1056 1056 static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
1057 1057 {
1058   - struct tsc210x_state_s *s = (struct tsc210x_state_s *) opaque;
  1058 + TSC210xState *s = (TSC210xState *) opaque;
1059 1059 int64_t now = qemu_get_clock(vm_clock);
1060 1060 int i;
1061 1061  
... ... @@ -1105,13 +1105,13 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
1105 1105 return 0;
1106 1106 }
1107 1107  
1108   -struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio)
  1108 +uWireSlave *tsc2102_init(qemu_irq pint, AudioState *audio)
1109 1109 {
1110   - struct tsc210x_state_s *s;
  1110 + TSC210xState *s;
1111 1111  
1112   - s = (struct tsc210x_state_s *)
1113   - qemu_mallocz(sizeof(struct tsc210x_state_s));
1114   - memset(s, 0, sizeof(struct tsc210x_state_s));
  1112 + s = (TSC210xState *)
  1113 + qemu_mallocz(sizeof(TSC210xState));
  1114 + memset(s, 0, sizeof(TSC210xState));
1115 1115 s->x = 160;
1116 1116 s->y = 160;
1117 1117 s->pressure = 0;
... ... @@ -1156,14 +1156,14 @@ struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio)
1156 1156 return &s->chip;
1157 1157 }
1158 1158  
1159   -struct uwire_slave_s *tsc2301_init(qemu_irq penirq, qemu_irq kbirq,
  1159 +uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq,
1160 1160 qemu_irq dav, AudioState *audio)
1161 1161 {
1162   - struct tsc210x_state_s *s;
  1162 + TSC210xState *s;
1163 1163  
1164   - s = (struct tsc210x_state_s *)
1165   - qemu_mallocz(sizeof(struct tsc210x_state_s));
1166   - memset(s, 0, sizeof(struct tsc210x_state_s));
  1164 + s = (TSC210xState *)
  1165 + qemu_mallocz(sizeof(TSC210xState));
  1166 + memset(s, 0, sizeof(TSC210xState));
1167 1167 s->x = 400;
1168 1168 s->y = 240;
1169 1169 s->pressure = 0;
... ... @@ -1209,9 +1209,9 @@ struct uwire_slave_s *tsc2301_init(qemu_irq penirq, qemu_irq kbirq,
1209 1209 return &s->chip;
1210 1210 }
1211 1211  
1212   -struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip)
  1212 +I2SCodec *tsc210x_codec(uWireSlave *chip)
1213 1213 {
1214   - struct tsc210x_state_s *s = (struct tsc210x_state_s *) chip->opaque;
  1214 + TSC210xState *s = (TSC210xState *) chip->opaque;
1215 1215  
1216 1216 return &s->codec;
1217 1217 }
... ... @@ -1221,10 +1221,10 @@ struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip)
1221 1221 * from the touchscreen. Assuming 12-bit precision was used during
1222 1222 * tslib calibration.
1223 1223 */
1224   -void tsc210x_set_transform(struct uwire_slave_s *chip,
1225   - struct mouse_transform_info_s *info)
  1224 +void tsc210x_set_transform(uWireSlave *chip,
  1225 + MouseTransformInfo *info)
1226 1226 {
1227   - struct tsc210x_state_s *s = (struct tsc210x_state_s *) chip->opaque;
  1227 + TSC210xState *s = (TSC210xState *) chip->opaque;
1228 1228 #if 0
1229 1229 int64_t ltr[8];
1230 1230  
... ... @@ -1283,9 +1283,9 @@ void tsc210x_set_transform(struct uwire_slave_s *chip,
1283 1283 #endif
1284 1284 }
1285 1285  
1286   -void tsc210x_key_event(struct uwire_slave_s *chip, int key, int down)
  1286 +void tsc210x_key_event(uWireSlave *chip, int key, int down)
1287 1287 {
1288   - struct tsc210x_state_s *s = (struct tsc210x_state_s *) chip->opaque;
  1288 + TSC210xState *s = (TSC210xState *) chip->opaque;
1289 1289  
1290 1290 if (down)
1291 1291 s->kb.down |= 1 << key;
... ...