gwj / at91sam9263 · Commits

Commit bbf662ee31cbd2dcd4fa7f469ad7e16f78e1acfa

Authored by bellard
1 parent 7d03f82f

MONITOR insn address generation fix - converted XLAT to TCG 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4479 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 20 additions and 40 deletions
target-i386/op.c
  View file @bbf662e
... ... @@ -224,30 +224,6 @@ void OPPROTO op_imulq_T0_T1(void)
224 224 /* constant load & misc op */
225 225  
226 226 /* XXX: consistent names */
227   -void OPPROTO op_addl_T1_im(void)
228   -{
229   - T1 += PARAM1;
230   -}
231   -
232   -void OPPROTO op_movl_T1_A0(void)
233   -{
234   - T1 = A0;
235   -}
236   -
237   -void OPPROTO op_addl_A0_AL(void)
238   -{
239   - A0 = (uint32_t)(A0 + (EAX & 0xff));
240   -}
241   -
242   -#ifdef TARGET_X86_64
243   -
244   -void OPPROTO op_addq_A0_AL(void)
245   -{
246   - A0 = (A0 + (EAX & 0xff));
247   -}
248   -
249   -#endif
250   -
251 227 void OPPROTO op_into(void)
252 228 {
253 229 int eflags;
... ...
target-i386/translate.c
  View file @bbf662e
... ... @@ -2352,12 +2352,12 @@ static void gen_push_T0(DisasContext *s)
2352 2352 gen_op_addl_A0_im(-4);
2353 2353 if (s->ss32) {
2354 2354 if (s->addseg) {
2355   - gen_op_movl_T1_A0();
  2355 + tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2356 2356 gen_op_addl_A0_seg(R_SS);
2357 2357 }
2358 2358 } else {
2359 2359 gen_op_andl_A0_ffff();
2360   - gen_op_movl_T1_A0();
  2360 + tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2361 2361 gen_op_addl_A0_seg(R_SS);
2362 2362 }
2363 2363 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
... ... @@ -2447,7 +2447,7 @@ static void gen_stack_A0(DisasContext *s)
2447 2447 gen_op_movl_A0_reg(R_ESP);
2448 2448 if (!s->ss32)
2449 2449 gen_op_andl_A0_ffff();
2450   - gen_op_movl_T1_A0();
  2450 + tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2451 2451 if (s->addseg)
2452 2452 gen_op_addl_A0_seg(R_SS);
2453 2453 }
... ... @@ -2460,7 +2460,7 @@ static void gen_pusha(DisasContext *s)
2460 2460 gen_op_addl_A0_im(-16 << s->dflag);
2461 2461 if (!s->ss32)
2462 2462 gen_op_andl_A0_ffff();
2463   - gen_op_movl_T1_A0();
  2463 + tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2464 2464 if (s->addseg)
2465 2465 gen_op_addl_A0_seg(R_SS);
2466 2466 for(i = 0;i < 8; i++) {
... ... @@ -2478,8 +2478,8 @@ static void gen_popa(DisasContext *s)
2478 2478 gen_op_movl_A0_reg(R_ESP);
2479 2479 if (!s->ss32)
2480 2480 gen_op_andl_A0_ffff();
2481   - gen_op_movl_T1_A0();
2482   - gen_op_addl_T1_im(16 << s->dflag);
  2481 + tcg_gen_mov_tl(cpu_T[1], cpu_A0);
  2482 + tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2483 2483 if (s->addseg)
2484 2484 gen_op_addl_A0_seg(R_SS);
2485 2485 for(i = 0;i < 8; i++) {
... ... @@ -2505,7 +2505,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
2505 2505  
2506 2506 gen_op_movl_A0_reg(R_ESP);
2507 2507 gen_op_addq_A0_im(-opsize);
2508   - gen_op_movl_T1_A0();
  2508 + tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2509 2509  
2510 2510 /* push bp */
2511 2511 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
... ... @@ -2518,7 +2518,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
2518 2518 cpu_T[1]);
2519 2519 }
2520 2520 gen_op_mov_reg_T1(ot, R_EBP);
2521   - gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
  2521 + tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2522 2522 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2523 2523 } else
2524 2524 #endif
... ... @@ -2530,7 +2530,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
2530 2530 gen_op_addl_A0_im(-opsize);
2531 2531 if (!s->ss32)
2532 2532 gen_op_andl_A0_ffff();
2533   - gen_op_movl_T1_A0();
  2533 + tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2534 2534 if (s->addseg)
2535 2535 gen_op_addl_A0_seg(R_SS);
2536 2536 /* push bp */
... ... @@ -2544,7 +2544,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
2544 2544 cpu_T[1]);
2545 2545 }
2546 2546 gen_op_mov_reg_T1(ot, R_EBP);
2547   - gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
  2547 + tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2548 2548 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2549 2549 }
2550 2550 }
... ... @@ -4561,14 +4561,20 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
4561 4561 #ifdef TARGET_X86_64
4562 4562 if (s->aflag == 2) {
4563 4563 gen_op_movq_A0_reg(R_EBX);
4564   - gen_op_addq_A0_AL();
  4564 + gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
  4565 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
  4566 + tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
4565 4567 } else
4566 4568 #endif
4567 4569 {
4568 4570 gen_op_movl_A0_reg(R_EBX);
4569   - gen_op_addl_A0_AL();
  4571 + gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
  4572 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
  4573 + tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
4570 4574 if (s->aflag == 0)
4571 4575 gen_op_andl_A0_ffff();
  4576 + else
  4577 + tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
4572 4578 }
4573 4579 gen_add_A0_ds_seg(s);
4574 4580 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
... ... @@ -6285,13 +6291,11 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
6285 6291 gen_jmp_im(pc_start - s->cs_base);
6286 6292 #ifdef TARGET_X86_64
6287 6293 if (s->aflag == 2) {
6288   - gen_op_movq_A0_reg(R_EBX);
6289   - gen_op_addq_A0_AL();
  6294 + gen_op_movq_A0_reg(R_EAX);
6290 6295 } else
6291 6296 #endif
6292 6297 {
6293   - gen_op_movl_A0_reg(R_EBX);
6294   - gen_op_addl_A0_AL();
  6298 + gen_op_movl_A0_reg(R_EAX);
6295 6299 if (s->aflag == 0)
6296 6300 gen_op_andl_A0_ffff();
6297 6301 }
... ...