Commit bb5529bb624ab922def08f24f5201b9fd83bb094

Authored by blueswir1
1 parent 54728ac6

Convert ldfsr and stfsr to TCG


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4067 c046a42c-6fe2-441c-8c8c-71466251a162
target-sparc/helper.h
... ... @@ -34,6 +34,7 @@ uint64_t TCG_HELPER_PROTO helper_ld_asi(target_ulong addr, int asi,
34 34 void TCG_HELPER_PROTO helper_st_asi(target_ulong addr, uint64_t val, int asi,
35 35 int size);
36 36 void TCG_HELPER_PROTO helper_ldfsr(void);
  37 +void TCG_HELPER_PROTO helper_stfsr(void);
37 38 void TCG_HELPER_PROTO helper_check_ieee_exceptions(void);
38 39 void TCG_HELPER_PROTO helper_clear_float_exceptions(void);
39 40 void TCG_HELPER_PROTO helper_fabss(void);
... ...
target-sparc/op.c
... ... @@ -285,16 +285,6 @@ void OPPROTO op_sdiv_T1_T0(void)
285 285 #endif
286 286 #endif
287 287  
288   -void OPPROTO op_ldfsr(void)
289   -{
290   - PUT_FSR32(env, *((uint32_t *) &FT0));
291   -}
292   -
293   -void OPPROTO op_stfsr(void)
294   -{
295   - *((uint32_t *) &FT0) = GET_FSR32(env);
296   -}
297   -
298 288 #ifndef TARGET_SPARC64
299 289 /* XXX: use another pointer for %iN registers to avoid slow wrapping
300 290 handling ? */
... ...
target-sparc/op_helper.c
... ... @@ -1590,6 +1590,8 @@ uint64_t helper_pack64(target_ulong high, target_ulong low)
1590 1590 void helper_ldfsr(void)
1591 1591 {
1592 1592 int rnd_mode;
  1593 +
  1594 + PUT_FSR32(env, *((uint32_t *) &FT0));
1593 1595 switch (env->fsr & FSR_RD_MASK) {
1594 1596 case FSR_RD_NEAREST:
1595 1597 rnd_mode = float_round_nearest_even;
... ... @@ -1608,7 +1610,12 @@ void helper_ldfsr(void)
1608 1610 set_float_rounding_mode(rnd_mode, &env->fp_status);
1609 1611 }
1610 1612  
1611   -void helper_debug()
  1613 +void helper_stfsr(void)
  1614 +{
  1615 + *((uint32_t *) &FT0) = GET_FSR32(env);
  1616 +}
  1617 +
  1618 +void helper_debug(void)
1612 1619 {
1613 1620 env->exception_index = EXCP_DEBUG;
1614 1621 cpu_loop_exit();
... ...
target-sparc/translate.c
... ... @@ -4259,7 +4259,6 @@ static void disas_sparc_insn(DisasContext * dc)
4259 4259 case 0x21: /* load fsr */
4260 4260 gen_op_check_align_T0_3();
4261 4261 gen_op_ldst(ldf);
4262   - gen_op_ldfsr();
4263 4262 tcg_gen_helper_0_0(helper_ldfsr);
4264 4263 break;
4265 4264 case 0x22: /* load quad fpreg */
... ... @@ -4415,7 +4414,7 @@ static void disas_sparc_insn(DisasContext * dc)
4415 4414 #ifdef CONFIG_USER_ONLY
4416 4415 gen_op_check_align_T0_3();
4417 4416 #endif
4418   - gen_op_stfsr();
  4417 + tcg_gen_helper_0_0(helper_stfsr);
4419 4418 gen_op_ldst(stf);
4420 4419 break;
4421 4420 case 0x26:
... ...