gwj / at91sam9263 · Commits

Commit ba6a9d8cdaffda76c9a8e28dc3d7b8363b48d904

Authored by blueswir1
1 parent 91736d37

Fix FCC handling for Sparc64 target, initial patch by Vince Weaver 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5110 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 28 additions and 30 deletions
target-sparc/cpu.h
  View file @ba6a9d8
... ... @@ -110,48 +110,48 @@
110 110 #endif
111 111  
112 112 /* Fcc */
113   -#define FSR_RD1 (1<<31)
114   -#define FSR_RD0 (1<<30)
  113 +#define FSR_RD1 (1ULL << 31)
  114 +#define FSR_RD0 (1ULL << 30)
115 115 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
116 116 #define FSR_RD_NEAREST 0
117 117 #define FSR_RD_ZERO FSR_RD0
118 118 #define FSR_RD_POS FSR_RD1
119 119 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
120 120  
121   -#define FSR_NVM (1<<27)
122   -#define FSR_OFM (1<<26)
123   -#define FSR_UFM (1<<25)
124   -#define FSR_DZM (1<<24)
125   -#define FSR_NXM (1<<23)
  121 +#define FSR_NVM (1ULL << 27)
  122 +#define FSR_OFM (1ULL << 26)
  123 +#define FSR_UFM (1ULL << 25)
  124 +#define FSR_DZM (1ULL << 24)
  125 +#define FSR_NXM (1ULL << 23)
126 126 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
127 127  
128   -#define FSR_NVA (1<<9)
129   -#define FSR_OFA (1<<8)
130   -#define FSR_UFA (1<<7)
131   -#define FSR_DZA (1<<6)
132   -#define FSR_NXA (1<<5)
  128 +#define FSR_NVA (1ULL << 9)
  129 +#define FSR_OFA (1ULL << 8)
  130 +#define FSR_UFA (1ULL << 7)
  131 +#define FSR_DZA (1ULL << 6)
  132 +#define FSR_NXA (1ULL << 5)
133 133 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
134 134  
135   -#define FSR_NVC (1<<4)
136   -#define FSR_OFC (1<<3)
137   -#define FSR_UFC (1<<2)
138   -#define FSR_DZC (1<<1)
139   -#define FSR_NXC (1<<0)
  135 +#define FSR_NVC (1ULL << 4)
  136 +#define FSR_OFC (1ULL << 3)
  137 +#define FSR_UFC (1ULL << 2)
  138 +#define FSR_DZC (1ULL << 1)
  139 +#define FSR_NXC (1ULL << 0)
140 140 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
141 141  
142   -#define FSR_FTT2 (1<<16)
143   -#define FSR_FTT1 (1<<15)
144   -#define FSR_FTT0 (1<<14)
  142 +#define FSR_FTT2 (1ULL << 16)
  143 +#define FSR_FTT1 (1ULL << 15)
  144 +#define FSR_FTT0 (1ULL << 14)
145 145 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
146   -#define FSR_FTT_IEEE_EXCP (1 << 14)
147   -#define FSR_FTT_UNIMPFPOP (3 << 14)
148   -#define FSR_FTT_SEQ_ERROR (4 << 14)
149   -#define FSR_FTT_INVAL_FPR (6 << 14)
  146 +#define FSR_FTT_IEEE_EXCP (1ULL << 14)
  147 +#define FSR_FTT_UNIMPFPOP (3ULL << 14)
  148 +#define FSR_FTT_SEQ_ERROR (4ULL << 14)
  149 +#define FSR_FTT_INVAL_FPR (6ULL << 14)
150 150  
151 151 #define FSR_FCC1_SHIFT 11
152   -#define FSR_FCC1 (1 << FSR_FCC1_SHIFT)
  152 +#define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
153 153 #define FSR_FCC0_SHIFT 10
154   -#define FSR_FCC0 (1 << FSR_FCC0_SHIFT)
  154 +#define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
155 155  
156 156 /* MMU */
157 157 #define MMU_E (1<<0)
... ...
target-sparc/translate.c
  View file @ba6a9d8
... ... @@ -999,16 +999,14 @@ static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
999 999 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
1000 1000 unsigned int fcc_offset)
1001 1001 {
1002   - tcg_gen_extu_i32_tl(reg, src);
1003   - tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
  1002 + tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
1004 1003 tcg_gen_andi_tl(reg, reg, 0x1);
1005 1004 }
1006 1005  
1007 1006 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
1008 1007 unsigned int fcc_offset)
1009 1008 {
1010   - tcg_gen_extu_i32_tl(reg, src);
1011   - tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
  1009 + tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
1012 1010 tcg_gen_andi_tl(reg, reg, 0x1);
1013 1011 }
1014 1012  
... ...