Commit ba28189bac853bfb3abbb3895a9f37103aaf6781
1 parent
bec19c09
Fix potential condition code problems
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4382 c046a42c-6fe2-441c-8c8c-71466251a162
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1 changed file
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58 additions
and
46 deletions
target-sparc/translate.c
@@ -434,15 +434,16 @@ static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) | @@ -434,15 +434,16 @@ static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) | ||
434 | tcg_gen_mov_tl(cpu_cc_src, src1); | 434 | tcg_gen_mov_tl(cpu_cc_src, src1); |
435 | tcg_gen_mov_tl(cpu_cc_src2, src2); | 435 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
436 | tcg_gen_add_tl(dst, src1, src2); | 436 | tcg_gen_add_tl(dst, src1, src2); |
437 | + tcg_gen_mov_tl(cpu_cc_dst, dst); | ||
437 | gen_cc_clear_icc(); | 438 | gen_cc_clear_icc(); |
438 | - gen_cc_NZ_icc(dst); | ||
439 | - gen_cc_C_add_icc(dst, cpu_cc_src); | ||
440 | - gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2); | 439 | + gen_cc_NZ_icc(cpu_cc_dst); |
440 | + gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | ||
441 | + gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | ||
441 | #ifdef TARGET_SPARC64 | 442 | #ifdef TARGET_SPARC64 |
442 | gen_cc_clear_xcc(); | 443 | gen_cc_clear_xcc(); |
443 | - gen_cc_NZ_xcc(dst); | ||
444 | - gen_cc_C_add_xcc(dst, cpu_cc_src); | ||
445 | - gen_cc_V_add_xcc(dst, cpu_cc_src, cpu_cc_src2); | 444 | + gen_cc_NZ_xcc(cpu_cc_dst); |
445 | + gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | ||
446 | + gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | ||
446 | #endif | 447 | #endif |
447 | } | 448 | } |
448 | 449 | ||
@@ -459,13 +460,14 @@ static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) | @@ -459,13 +460,14 @@ static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) | ||
459 | gen_cc_C_add_xcc(dst, cpu_cc_src); | 460 | gen_cc_C_add_xcc(dst, cpu_cc_src); |
460 | #endif | 461 | #endif |
461 | tcg_gen_add_tl(dst, dst, cpu_cc_src2); | 462 | tcg_gen_add_tl(dst, dst, cpu_cc_src2); |
462 | - gen_cc_NZ_icc(dst); | ||
463 | - gen_cc_C_add_icc(dst, cpu_cc_src); | ||
464 | - gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2); | 463 | + tcg_gen_mov_tl(cpu_cc_dst, dst); |
464 | + gen_cc_NZ_icc(cpu_cc_dst); | ||
465 | + gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | ||
466 | + gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | ||
465 | #ifdef TARGET_SPARC64 | 467 | #ifdef TARGET_SPARC64 |
466 | - gen_cc_NZ_xcc(dst); | ||
467 | - gen_cc_C_add_xcc(dst, cpu_cc_src); | ||
468 | - gen_cc_V_add_xcc(dst, cpu_cc_src, cpu_cc_src2); | 468 | + gen_cc_NZ_xcc(cpu_cc_dst); |
469 | + gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | ||
470 | + gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | ||
469 | #endif | 471 | #endif |
470 | } | 472 | } |
471 | 473 | ||
@@ -474,16 +476,17 @@ static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) | @@ -474,16 +476,17 @@ static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) | ||
474 | tcg_gen_mov_tl(cpu_cc_src, src1); | 476 | tcg_gen_mov_tl(cpu_cc_src, src1); |
475 | tcg_gen_mov_tl(cpu_cc_src2, src2); | 477 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
476 | tcg_gen_add_tl(dst, src1, src2); | 478 | tcg_gen_add_tl(dst, src1, src2); |
479 | + tcg_gen_mov_tl(cpu_cc_dst, dst); | ||
477 | gen_cc_clear_icc(); | 480 | gen_cc_clear_icc(); |
478 | - gen_cc_NZ_icc(dst); | ||
479 | - gen_cc_C_add_icc(dst, cpu_cc_src); | ||
480 | - gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2); | 481 | + gen_cc_NZ_icc(cpu_cc_dst); |
482 | + gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | ||
483 | + gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | ||
481 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); | 484 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
482 | #ifdef TARGET_SPARC64 | 485 | #ifdef TARGET_SPARC64 |
483 | gen_cc_clear_xcc(); | 486 | gen_cc_clear_xcc(); |
484 | - gen_cc_NZ_xcc(dst); | ||
485 | - gen_cc_C_add_xcc(dst, cpu_cc_src); | ||
486 | - gen_cc_V_add_xcc(dst, cpu_cc_src, cpu_cc_src2); | 487 | + gen_cc_NZ_xcc(cpu_cc_dst); |
488 | + gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | ||
489 | + gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | ||
487 | #endif | 490 | #endif |
488 | } | 491 | } |
489 | 492 | ||
@@ -493,15 +496,16 @@ static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) | @@ -493,15 +496,16 @@ static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) | ||
493 | tcg_gen_mov_tl(cpu_cc_src2, src2); | 496 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
494 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); | 497 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
495 | tcg_gen_add_tl(dst, src1, src2); | 498 | tcg_gen_add_tl(dst, src1, src2); |
499 | + tcg_gen_mov_tl(cpu_cc_dst, dst); | ||
496 | gen_add_tv(dst, cpu_cc_src, cpu_cc_src2); | 500 | gen_add_tv(dst, cpu_cc_src, cpu_cc_src2); |
497 | gen_cc_clear_icc(); | 501 | gen_cc_clear_icc(); |
498 | - gen_cc_NZ_icc(dst); | ||
499 | - gen_cc_C_add_icc(dst, cpu_cc_src); | 502 | + gen_cc_NZ_icc(cpu_cc_dst); |
503 | + gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | ||
500 | #ifdef TARGET_SPARC64 | 504 | #ifdef TARGET_SPARC64 |
501 | gen_cc_clear_xcc(); | 505 | gen_cc_clear_xcc(); |
502 | - gen_cc_NZ_xcc(dst); | ||
503 | - gen_cc_C_add_xcc(dst, cpu_cc_src); | ||
504 | - gen_cc_V_add_xcc(dst, cpu_cc_src, cpu_cc_src2); | 506 | + gen_cc_NZ_xcc(cpu_cc_dst); |
507 | + gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | ||
508 | + gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | ||
505 | #endif | 509 | #endif |
506 | } | 510 | } |
507 | 511 | ||
@@ -592,15 +596,16 @@ static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) | @@ -592,15 +596,16 @@ static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) | ||
592 | tcg_gen_mov_tl(cpu_cc_src, src1); | 596 | tcg_gen_mov_tl(cpu_cc_src, src1); |
593 | tcg_gen_mov_tl(cpu_cc_src2, src2); | 597 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
594 | tcg_gen_sub_tl(dst, src1, src2); | 598 | tcg_gen_sub_tl(dst, src1, src2); |
599 | + tcg_gen_mov_tl(cpu_cc_dst, dst); | ||
595 | gen_cc_clear_icc(); | 600 | gen_cc_clear_icc(); |
596 | - gen_cc_NZ_icc(dst); | 601 | + gen_cc_NZ_icc(cpu_cc_dst); |
597 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); | 602 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
598 | - gen_cc_V_sub_icc(dst, cpu_cc_src, cpu_cc_src2); | 603 | + gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
599 | #ifdef TARGET_SPARC64 | 604 | #ifdef TARGET_SPARC64 |
600 | gen_cc_clear_xcc(); | 605 | gen_cc_clear_xcc(); |
601 | - gen_cc_NZ_xcc(dst); | 606 | + gen_cc_NZ_xcc(cpu_cc_dst); |
602 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); | 607 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
603 | - gen_cc_V_sub_xcc(dst, cpu_cc_src, cpu_cc_src2); | 608 | + gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
604 | #endif | 609 | #endif |
605 | } | 610 | } |
606 | 611 | ||
@@ -617,13 +622,14 @@ static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) | @@ -617,13 +622,14 @@ static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) | ||
617 | gen_cc_C_sub_xcc(dst, cpu_cc_src); | 622 | gen_cc_C_sub_xcc(dst, cpu_cc_src); |
618 | #endif | 623 | #endif |
619 | tcg_gen_sub_tl(dst, dst, cpu_cc_src2); | 624 | tcg_gen_sub_tl(dst, dst, cpu_cc_src2); |
620 | - gen_cc_NZ_icc(dst); | ||
621 | - gen_cc_C_sub_icc(dst, cpu_cc_src); | ||
622 | - gen_cc_V_sub_icc(dst, cpu_cc_src, cpu_cc_src2); | 625 | + tcg_gen_mov_tl(cpu_cc_dst, dst); |
626 | + gen_cc_NZ_icc(cpu_cc_dst); | ||
627 | + gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); | ||
628 | + gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | ||
623 | #ifdef TARGET_SPARC64 | 629 | #ifdef TARGET_SPARC64 |
624 | - gen_cc_NZ_xcc(dst); | ||
625 | - gen_cc_C_sub_xcc(dst, cpu_cc_src); | ||
626 | - gen_cc_V_sub_xcc(dst, cpu_cc_src, cpu_cc_src2); | 630 | + gen_cc_NZ_xcc(cpu_cc_dst); |
631 | + gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); | ||
632 | + gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | ||
627 | #endif | 633 | #endif |
628 | } | 634 | } |
629 | 635 | ||
@@ -632,16 +638,17 @@ static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) | @@ -632,16 +638,17 @@ static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) | ||
632 | tcg_gen_mov_tl(cpu_cc_src, src1); | 638 | tcg_gen_mov_tl(cpu_cc_src, src1); |
633 | tcg_gen_mov_tl(cpu_cc_src2, src2); | 639 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
634 | tcg_gen_sub_tl(dst, src1, src2); | 640 | tcg_gen_sub_tl(dst, src1, src2); |
641 | + tcg_gen_mov_tl(cpu_cc_dst, dst); | ||
635 | gen_cc_clear_icc(); | 642 | gen_cc_clear_icc(); |
636 | - gen_cc_NZ_icc(dst); | 643 | + gen_cc_NZ_icc(cpu_cc_dst); |
637 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); | 644 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
638 | - gen_cc_V_sub_icc(dst, cpu_cc_src, cpu_cc_src2); | 645 | + gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
639 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); | 646 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
640 | #ifdef TARGET_SPARC64 | 647 | #ifdef TARGET_SPARC64 |
641 | gen_cc_clear_xcc(); | 648 | gen_cc_clear_xcc(); |
642 | - gen_cc_NZ_xcc(dst); | 649 | + gen_cc_NZ_xcc(cpu_cc_dst); |
643 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); | 650 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
644 | - gen_cc_V_sub_xcc(dst, cpu_cc_src, cpu_cc_src2); | 651 | + gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
645 | #endif | 652 | #endif |
646 | } | 653 | } |
647 | 654 | ||
@@ -651,15 +658,16 @@ static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) | @@ -651,15 +658,16 @@ static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) | ||
651 | tcg_gen_mov_tl(cpu_cc_src2, src2); | 658 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
652 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); | 659 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
653 | tcg_gen_sub_tl(dst, src1, src2); | 660 | tcg_gen_sub_tl(dst, src1, src2); |
661 | + tcg_gen_mov_tl(cpu_cc_dst, dst); | ||
654 | gen_sub_tv(dst, cpu_cc_src, cpu_cc_src2); | 662 | gen_sub_tv(dst, cpu_cc_src, cpu_cc_src2); |
655 | gen_cc_clear_icc(); | 663 | gen_cc_clear_icc(); |
656 | - gen_cc_NZ_icc(dst); | 664 | + gen_cc_NZ_icc(cpu_cc_dst); |
657 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); | 665 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
658 | #ifdef TARGET_SPARC64 | 666 | #ifdef TARGET_SPARC64 |
659 | gen_cc_clear_xcc(); | 667 | gen_cc_clear_xcc(); |
660 | - gen_cc_NZ_xcc(dst); | 668 | + gen_cc_NZ_xcc(cpu_cc_dst); |
661 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); | 669 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
662 | - gen_cc_V_sub_xcc(dst, cpu_cc_src, cpu_cc_src2); | 670 | + gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
663 | #endif | 671 | #endif |
664 | } | 672 | } |
665 | 673 | ||
@@ -708,11 +716,12 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) | @@ -708,11 +716,12 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) | ||
708 | 716 | ||
709 | /* do addition and update flags */ | 717 | /* do addition and update flags */ |
710 | tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2); | 718 | tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2); |
719 | + tcg_gen_mov_tl(cpu_cc_dst, dst); | ||
711 | 720 | ||
712 | gen_cc_clear_icc(); | 721 | gen_cc_clear_icc(); |
713 | - gen_cc_NZ_icc(dst); | ||
714 | - gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2); | ||
715 | - gen_cc_C_add_icc(dst, cpu_cc_src); | 722 | + gen_cc_NZ_icc(cpu_cc_dst); |
723 | + gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | ||
724 | + gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | ||
716 | } | 725 | } |
717 | 726 | ||
718 | static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) | 727 | static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
@@ -791,8 +800,9 @@ static inline void gen_op_div_cc(TCGv dst) | @@ -791,8 +800,9 @@ static inline void gen_op_div_cc(TCGv dst) | ||
791 | { | 800 | { |
792 | int l1; | 801 | int l1; |
793 | 802 | ||
803 | + tcg_gen_mov_tl(cpu_cc_dst, dst); | ||
794 | gen_cc_clear_icc(); | 804 | gen_cc_clear_icc(); |
795 | - gen_cc_NZ_icc(dst); | 805 | + gen_cc_NZ_icc(cpu_cc_dst); |
796 | l1 = gen_new_label(); | 806 | l1 = gen_new_label(); |
797 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2)); | 807 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2)); |
798 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1); | 808 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1); |
@@ -802,11 +812,13 @@ static inline void gen_op_div_cc(TCGv dst) | @@ -802,11 +812,13 @@ static inline void gen_op_div_cc(TCGv dst) | ||
802 | 812 | ||
803 | static inline void gen_op_logic_cc(TCGv dst) | 813 | static inline void gen_op_logic_cc(TCGv dst) |
804 | { | 814 | { |
815 | + tcg_gen_mov_tl(cpu_cc_dst, dst); | ||
816 | + | ||
805 | gen_cc_clear_icc(); | 817 | gen_cc_clear_icc(); |
806 | - gen_cc_NZ_icc(dst); | 818 | + gen_cc_NZ_icc(cpu_cc_dst); |
807 | #ifdef TARGET_SPARC64 | 819 | #ifdef TARGET_SPARC64 |
808 | gen_cc_clear_xcc(); | 820 | gen_cc_clear_xcc(); |
809 | - gen_cc_NZ_xcc(dst); | 821 | + gen_cc_NZ_xcc(cpu_cc_dst); |
810 | #endif | 822 | #endif |
811 | } | 823 | } |
812 | 824 |