gwj / at91sam9263 · Commits

Commit b8d3f5d1264260db42e1d64c9d7c537df0aa31ce

Authored by j_mayer
1 parent a750fc0b

Add flags to support PowerPC 405 bootinfos variations. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3245 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 6 additions and 4 deletions
hw/ppc405.h
  View file @b8d3f5d
... ... @@ -57,7 +57,8 @@ struct ppc4xx_bd_info_t {
57 57 CPUState *ppc405_init (const unsigned char *cpu_model,
58 58 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
59 59 uint32_t sysclk);
60   -ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd);
  60 +ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
  61 + uint32_t flags);
61 62  
62 63 /* */
63 64 typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
... ...
hw/ppc405_boards.c
  View file @b8d3f5d
... ... @@ -288,7 +288,7 @@ static void ref405ep_init (int ram_size, int vga_ram_size, int boot_device,
288 288 bd.bi_plb_busfreq = 33333333;
289 289 bd.bi_pci_busfreq = 33333333;
290 290 bd.bi_opbfreq = 33333333;
291   - bdloc = ppc405_set_bootinfo(env, &bd);
  291 + bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
292 292 env->gpr[3] = bdloc;
293 293 kernel_base = KERNEL_LOAD_ADDR;
294 294 /* now we can load the kernel */
... ...
hw/ppc405_uc.c
  View file @b8d3f5d
... ... @@ -69,7 +69,8 @@ CPUState *ppc405_init (const unsigned char *cpu_model,
69 69 return env;
70 70 }
71 71  
72   -ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd)
  72 +ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
  73 + uint32_t flags)
73 74 {
74 75 ram_addr_t bdloc;
75 76 int i, n;
... ... @@ -103,7 +104,7 @@ ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd)
103 104 for (i = 0; i < 6; i++)
104 105 stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
105 106 n = 0x6A;
106   - if (env->spr[SPR_PVR] == CPU_PPC_405EP) {
  107 + if (flags & 0x00000001) {
107 108 for (i = 0; i < 6; i++)
108 109 stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]);
109 110 }
... ...