Commit b8a9e8f1336492798107a8704c22c4e8053c3dd7
1 parent
4955a2cd
initial user mmu support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1270 c046a42c-6fe2-441c-8c8c-71466251a162
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3 changed files
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31 additions
and
2 deletions
target-arm/cpu.h
| @@ -24,8 +24,10 @@ | @@ -24,8 +24,10 @@ | ||
| 24 | 24 | ||
| 25 | #include "cpu-defs.h" | 25 | #include "cpu-defs.h" |
| 26 | 26 | ||
| 27 | -#define EXCP_UDEF 1 /* undefined instruction */ | ||
| 28 | -#define EXCP_SWI 2 /* software interrupt */ | 27 | +#define EXCP_UDEF 1 /* undefined instruction */ |
| 28 | +#define EXCP_SWI 2 /* software interrupt */ | ||
| 29 | +#define EXCP_PREFETCH_ABORT 3 | ||
| 30 | +#define EXCP_DATA_ABORT 4 | ||
| 29 | 31 | ||
| 30 | typedef struct CPUARMState { | 32 | typedef struct CPUARMState { |
| 31 | uint32_t regs[16]; | 33 | uint32_t regs[16]; |
| @@ -39,6 +41,9 @@ typedef struct CPUARMState { | @@ -39,6 +41,9 @@ typedef struct CPUARMState { | ||
| 39 | 41 | ||
| 40 | int thumb; /* 0 = arm mode, 1 = thumb mode */ | 42 | int thumb; /* 0 = arm mode, 1 = thumb mode */ |
| 41 | 43 | ||
| 44 | + /* coprocessor 15 (MMU) status */ | ||
| 45 | + uint32_t cp15_6; | ||
| 46 | + | ||
| 42 | /* exception/interrupt handling */ | 47 | /* exception/interrupt handling */ |
| 43 | jmp_buf jmp_env; | 48 | jmp_buf jmp_env; |
| 44 | int exception_index; | 49 | int exception_index; |
target-arm/exec.h
| @@ -48,3 +48,6 @@ static inline void env_to_regs(void) | @@ -48,3 +48,6 @@ static inline void env_to_regs(void) | ||
| 48 | static inline void regs_to_env(void) | 48 | static inline void regs_to_env(void) |
| 49 | { | 49 | { |
| 50 | } | 50 | } |
| 51 | + | ||
| 52 | +int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, | ||
| 53 | + int is_user, int is_softmmu); |
target-arm/translate.c
| @@ -424,6 +424,7 @@ static void disas_arm_insn(DisasContext *s) | @@ -424,6 +424,7 @@ static void disas_arm_insn(DisasContext *s) | ||
| 424 | gen_op_movl_T0_psr(); | 424 | gen_op_movl_T0_psr(); |
| 425 | gen_movl_reg_T0(s, rd); | 425 | gen_movl_reg_T0(s, rd); |
| 426 | } | 426 | } |
| 427 | + break; | ||
| 427 | case 0x1: | 428 | case 0x1: |
| 428 | if (op1 == 1) { | 429 | if (op1 == 1) { |
| 429 | /* branch/exchange thumb (bx). */ | 430 | /* branch/exchange thumb (bx). */ |
| @@ -1576,3 +1577,23 @@ target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) | @@ -1576,3 +1577,23 @@ target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) | ||
| 1576 | { | 1577 | { |
| 1577 | return addr; | 1578 | return addr; |
| 1578 | } | 1579 | } |
| 1580 | + | ||
| 1581 | +#if defined(CONFIG_USER_ONLY) | ||
| 1582 | + | ||
| 1583 | +int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, | ||
| 1584 | + int is_user, int is_softmmu) | ||
| 1585 | +{ | ||
| 1586 | + env->cp15_6 = address; | ||
| 1587 | + if (rw == 2) { | ||
| 1588 | + env->exception_index = EXCP_PREFETCH_ABORT; | ||
| 1589 | + } else { | ||
| 1590 | + env->exception_index = EXCP_DATA_ABORT; | ||
| 1591 | + } | ||
| 1592 | + return 1; | ||
| 1593 | +} | ||
| 1594 | + | ||
| 1595 | +#else | ||
| 1596 | + | ||
| 1597 | +#error not implemented | ||
| 1598 | + | ||
| 1599 | +#endif |