gwj / at91sam9263 · Commits

Commit b89e94af1dfcf881960804344ac9d2a6759d3aea

Authored by Blue Swirl
1 parent 7ab463cb

Improve instruction name comments for easier searching 

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Inline Side-by-side
Showing 1 changed file with 44 additions and 44 deletions
target-sparc/translate.c
  View file @b89e94a
@@ -2496,7 +2496,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2496,7 +2496,7 @@ static void disas_sparc_insn(DisasContext * dc)
2496 gen_helper_check_ieee_exceptions(); 2496 gen_helper_check_ieee_exceptions();
2497 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); 2497 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2498 break; 2498 break;
2499 - case 0x42: 2499 + case 0x42: /* faddd */
2500 gen_op_load_fpr_DT0(DFPREG(rs1)); 2500 gen_op_load_fpr_DT0(DFPREG(rs1));
2501 gen_op_load_fpr_DT1(DFPREG(rs2)); 2501 gen_op_load_fpr_DT1(DFPREG(rs2));
2502 gen_clear_float_exceptions(); 2502 gen_clear_float_exceptions();
@@ -2520,7 +2520,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2520,7 +2520,7 @@ static void disas_sparc_insn(DisasContext * dc)
2520 gen_helper_check_ieee_exceptions(); 2520 gen_helper_check_ieee_exceptions();
2521 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); 2521 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2522 break; 2522 break;
2523 - case 0x46: 2523 + case 0x46: /* fsubd */
2524 gen_op_load_fpr_DT0(DFPREG(rs1)); 2524 gen_op_load_fpr_DT0(DFPREG(rs1));
2525 gen_op_load_fpr_DT1(DFPREG(rs2)); 2525 gen_op_load_fpr_DT1(DFPREG(rs2));
2526 gen_clear_float_exceptions(); 2526 gen_clear_float_exceptions();
@@ -2571,7 +2571,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2571,7 +2571,7 @@ static void disas_sparc_insn(DisasContext * dc)
2571 gen_helper_check_ieee_exceptions(); 2571 gen_helper_check_ieee_exceptions();
2572 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); 2572 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2573 break; 2573 break;
2574 - case 0x4e: 2574 + case 0x4e: /* fdivd */
2575 gen_op_load_fpr_DT0(DFPREG(rs1)); 2575 gen_op_load_fpr_DT0(DFPREG(rs1));
2576 gen_op_load_fpr_DT1(DFPREG(rs2)); 2576 gen_op_load_fpr_DT1(DFPREG(rs2));
2577 gen_clear_float_exceptions(); 2577 gen_clear_float_exceptions();
@@ -3136,7 +3136,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3136,7 +3136,7 @@ static void disas_sparc_insn(DisasContext * dc)
3136 cpu_src1 = get_src1(insn, cpu_src1); 3136 cpu_src1 = get_src1(insn, cpu_src1);
3137 cpu_src2 = get_src2(insn, cpu_src2); 3137 cpu_src2 = get_src2(insn, cpu_src2);
3138 switch (xop & ~0x10) { 3138 switch (xop & ~0x10) {
3139 - case 0x0: 3139 + case 0x0: /* add */
3140 if (IS_IMM) { 3140 if (IS_IMM) {
3141 simm = GET_FIELDs(insn, 19, 31); 3141 simm = GET_FIELDs(insn, 19, 31);
3142 if (xop & 0x10) { 3142 if (xop & 0x10) {
@@ -3152,7 +3152,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3152,7 +3152,7 @@ static void disas_sparc_insn(DisasContext * dc)
3152 } 3152 }
3153 } 3153 }
3154 break; 3154 break;
3155 - case 0x1: 3155 + case 0x1: /* and */
3156 if (IS_IMM) { 3156 if (IS_IMM) {
3157 simm = GET_FIELDs(insn, 19, 31); 3157 simm = GET_FIELDs(insn, 19, 31);
3158 tcg_gen_andi_tl(cpu_dst, cpu_src1, simm); 3158 tcg_gen_andi_tl(cpu_dst, cpu_src1, simm);
@@ -3163,7 +3163,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3163,7 +3163,7 @@ static void disas_sparc_insn(DisasContext * dc)
3163 gen_op_logic_cc(cpu_dst); 3163 gen_op_logic_cc(cpu_dst);
3164 } 3164 }
3165 break; 3165 break;
3166 - case 0x2: 3166 + case 0x2: /* or */
3167 if (IS_IMM) { 3167 if (IS_IMM) {
3168 simm = GET_FIELDs(insn, 19, 31); 3168 simm = GET_FIELDs(insn, 19, 31);
3169 tcg_gen_ori_tl(cpu_dst, cpu_src1, simm); 3169 tcg_gen_ori_tl(cpu_dst, cpu_src1, simm);
@@ -3173,7 +3173,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3173,7 +3173,7 @@ static void disas_sparc_insn(DisasContext * dc)
3173 if (xop & 0x10) 3173 if (xop & 0x10)
3174 gen_op_logic_cc(cpu_dst); 3174 gen_op_logic_cc(cpu_dst);
3175 break; 3175 break;
3176 - case 0x3: 3176 + case 0x3: /* xor */
3177 if (IS_IMM) { 3177 if (IS_IMM) {
3178 simm = GET_FIELDs(insn, 19, 31); 3178 simm = GET_FIELDs(insn, 19, 31);
3179 tcg_gen_xori_tl(cpu_dst, cpu_src1, simm); 3179 tcg_gen_xori_tl(cpu_dst, cpu_src1, simm);
@@ -3183,7 +3183,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3183,7 +3183,7 @@ static void disas_sparc_insn(DisasContext * dc)
3183 if (xop & 0x10) 3183 if (xop & 0x10)
3184 gen_op_logic_cc(cpu_dst); 3184 gen_op_logic_cc(cpu_dst);
3185 break; 3185 break;
3186 - case 0x4: 3186 + case 0x4: /* sub */
3187 if (IS_IMM) { 3187 if (IS_IMM) {
3188 simm = GET_FIELDs(insn, 19, 31); 3188 simm = GET_FIELDs(insn, 19, 31);
3189 if (xop & 0x10) { 3189 if (xop & 0x10) {
@@ -3199,7 +3199,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3199,7 +3199,7 @@ static void disas_sparc_insn(DisasContext * dc)
3199 } 3199 }
3200 } 3200 }
3201 break; 3201 break;
3202 - case 0x5: 3202 + case 0x5: /* andn */
3203 if (IS_IMM) { 3203 if (IS_IMM) {
3204 simm = GET_FIELDs(insn, 19, 31); 3204 simm = GET_FIELDs(insn, 19, 31);
3205 tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm); 3205 tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm);
@@ -3209,7 +3209,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3209,7 +3209,7 @@ static void disas_sparc_insn(DisasContext * dc)
3209 if (xop & 0x10) 3209 if (xop & 0x10)
3210 gen_op_logic_cc(cpu_dst); 3210 gen_op_logic_cc(cpu_dst);
3211 break; 3211 break;
3212 - case 0x6: 3212 + case 0x6: /* orn */
3213 if (IS_IMM) { 3213 if (IS_IMM) {
3214 simm = GET_FIELDs(insn, 19, 31); 3214 simm = GET_FIELDs(insn, 19, 31);
3215 tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm); 3215 tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm);
@@ -3219,7 +3219,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3219,7 +3219,7 @@ static void disas_sparc_insn(DisasContext * dc)
3219 if (xop & 0x10) 3219 if (xop & 0x10)
3220 gen_op_logic_cc(cpu_dst); 3220 gen_op_logic_cc(cpu_dst);
3221 break; 3221 break;
3222 - case 0x7: 3222 + case 0x7: /* xorn */
3223 if (IS_IMM) { 3223 if (IS_IMM) {
3224 simm = GET_FIELDs(insn, 19, 31); 3224 simm = GET_FIELDs(insn, 19, 31);
3225 tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm); 3225 tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm);
@@ -3230,7 +3230,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3230,7 +3230,7 @@ static void disas_sparc_insn(DisasContext * dc)
3230 if (xop & 0x10) 3230 if (xop & 0x10)
3231 gen_op_logic_cc(cpu_dst); 3231 gen_op_logic_cc(cpu_dst);
3232 break; 3232 break;
3233 - case 0x8: 3233 + case 0x8: /* addx, V9 addc */
3234 if (IS_IMM) { 3234 if (IS_IMM) {
3235 simm = GET_FIELDs(insn, 19, 31); 3235 simm = GET_FIELDs(insn, 19, 31);
3236 if (xop & 0x10) 3236 if (xop & 0x10)
@@ -3260,19 +3260,19 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3260,19 +3260,19 @@ static void disas_sparc_insn(DisasContext * dc)
3260 } 3260 }
3261 break; 3261 break;
3262 #endif 3262 #endif
3263 - case 0xa: 3263 + case 0xa: /* umul */
3264 CHECK_IU_FEATURE(dc, MUL); 3264 CHECK_IU_FEATURE(dc, MUL);
3265 gen_op_umul(cpu_dst, cpu_src1, cpu_src2); 3265 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3266 if (xop & 0x10) 3266 if (xop & 0x10)
3267 gen_op_logic_cc(cpu_dst); 3267 gen_op_logic_cc(cpu_dst);
3268 break; 3268 break;
3269 - case 0xb: 3269 + case 0xb: /* smul */
3270 CHECK_IU_FEATURE(dc, MUL); 3270 CHECK_IU_FEATURE(dc, MUL);
3271 gen_op_smul(cpu_dst, cpu_src1, cpu_src2); 3271 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3272 if (xop & 0x10) 3272 if (xop & 0x10)
3273 gen_op_logic_cc(cpu_dst); 3273 gen_op_logic_cc(cpu_dst);
3274 break; 3274 break;
3275 - case 0xc: 3275 + case 0xc: /* subx, V9 subc */
3276 if (IS_IMM) { 3276 if (IS_IMM) {
3277 simm = GET_FIELDs(insn, 19, 31); 3277 simm = GET_FIELDs(insn, 19, 31);
3278 if (xop & 0x10) { 3278 if (xop & 0x10) {
@@ -3300,13 +3300,13 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3300,13 +3300,13 @@ static void disas_sparc_insn(DisasContext * dc)
3300 tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2); 3300 tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
3301 break; 3301 break;
3302 #endif 3302 #endif
3303 - case 0xe: 3303 + case 0xe: /* udiv */
3304 CHECK_IU_FEATURE(dc, DIV); 3304 CHECK_IU_FEATURE(dc, DIV);
3305 gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2); 3305 gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2);
3306 if (xop & 0x10) 3306 if (xop & 0x10)
3307 gen_op_div_cc(cpu_dst); 3307 gen_op_div_cc(cpu_dst);
3308 break; 3308 break;
3309 - case 0xf: 3309 + case 0xf: /* sdiv */
3310 CHECK_IU_FEATURE(dc, DIV); 3310 CHECK_IU_FEATURE(dc, DIV);
3311 gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2); 3311 gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2);
3312 if (xop & 0x10) 3312 if (xop & 0x10)
@@ -4385,19 +4385,19 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4385,19 +4385,19 @@ static void disas_sparc_insn(DisasContext * dc)
4385 (xop > 0x17 && xop <= 0x1d ) || 4385 (xop > 0x17 && xop <= 0x1d ) ||
4386 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { 4386 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4387 switch (xop) { 4387 switch (xop) {
4388 - case 0x0: /* load unsigned word */ 4388 + case 0x0: /* ld, V9 lduw, load unsigned word */
4389 gen_address_mask(dc, cpu_addr); 4389 gen_address_mask(dc, cpu_addr);
4390 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); 4390 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4391 break; 4391 break;
4392 - case 0x1: /* load unsigned byte */ 4392 + case 0x1: /* ldub, load unsigned byte */
4393 gen_address_mask(dc, cpu_addr); 4393 gen_address_mask(dc, cpu_addr);
4394 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); 4394 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4395 break; 4395 break;
4396 - case 0x2: /* load unsigned halfword */ 4396 + case 0x2: /* lduh, load unsigned halfword */
4397 gen_address_mask(dc, cpu_addr); 4397 gen_address_mask(dc, cpu_addr);
4398 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); 4398 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4399 break; 4399 break;
4400 - case 0x3: /* load double word */ 4400 + case 0x3: /* ldd, load double word */
4401 if (rd & 1) 4401 if (rd & 1)
4402 goto illegal_insn; 4402 goto illegal_insn;
4403 else { 4403 else {
@@ -4417,11 +4417,11 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4417,11 +4417,11 @@ static void disas_sparc_insn(DisasContext * dc)
4417 tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL); 4417 tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4418 } 4418 }
4419 break; 4419 break;
4420 - case 0x9: /* load signed byte */ 4420 + case 0x9: /* ldsb, load signed byte */
4421 gen_address_mask(dc, cpu_addr); 4421 gen_address_mask(dc, cpu_addr);
4422 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); 4422 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4423 break; 4423 break;
4424 - case 0xa: /* load signed halfword */ 4424 + case 0xa: /* ldsh, load signed halfword */
4425 gen_address_mask(dc, cpu_addr); 4425 gen_address_mask(dc, cpu_addr);
4426 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); 4426 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4427 break; 4427 break;
@@ -4436,7 +4436,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4436,7 +4436,7 @@ static void disas_sparc_insn(DisasContext * dc)
4436 tcg_temp_free(r_const); 4436 tcg_temp_free(r_const);
4437 } 4437 }
4438 break; 4438 break;
4439 - case 0x0f: /* swap register with memory. Also 4439 + case 0x0f: /* swap, swap register with memory. Also
4440 atomically */ 4440 atomically */
4441 CHECK_IU_FEATURE(dc, SWAP); 4441 CHECK_IU_FEATURE(dc, SWAP);
4442 gen_movl_reg_TN(rd, cpu_val); 4442 gen_movl_reg_TN(rd, cpu_val);
@@ -4446,7 +4446,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4446,7 +4446,7 @@ static void disas_sparc_insn(DisasContext * dc)
4446 tcg_gen_mov_tl(cpu_val, cpu_tmp0); 4446 tcg_gen_mov_tl(cpu_val, cpu_tmp0);
4447 break; 4447 break;
4448 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 4448 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4449 - case 0x10: /* load word alternate */ 4449 + case 0x10: /* lda, V9 lduwa, load word alternate */
4450 #ifndef TARGET_SPARC64 4450 #ifndef TARGET_SPARC64
4451 if (IS_IMM) 4451 if (IS_IMM)
4452 goto illegal_insn; 4452 goto illegal_insn;
@@ -4456,7 +4456,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4456,7 +4456,7 @@ static void disas_sparc_insn(DisasContext * dc)
4456 save_state(dc, cpu_cond); 4456 save_state(dc, cpu_cond);
4457 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0); 4457 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4458 break; 4458 break;
4459 - case 0x11: /* load unsigned byte alternate */ 4459 + case 0x11: /* lduba, load unsigned byte alternate */
4460 #ifndef TARGET_SPARC64 4460 #ifndef TARGET_SPARC64
4461 if (IS_IMM) 4461 if (IS_IMM)
4462 goto illegal_insn; 4462 goto illegal_insn;
@@ -4466,7 +4466,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4466,7 +4466,7 @@ static void disas_sparc_insn(DisasContext * dc)
4466 save_state(dc, cpu_cond); 4466 save_state(dc, cpu_cond);
4467 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0); 4467 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4468 break; 4468 break;
4469 - case 0x12: /* load unsigned halfword alternate */ 4469 + case 0x12: /* lduha, load unsigned halfword alternate */
4470 #ifndef TARGET_SPARC64 4470 #ifndef TARGET_SPARC64
4471 if (IS_IMM) 4471 if (IS_IMM)
4472 goto illegal_insn; 4472 goto illegal_insn;
@@ -4476,7 +4476,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4476,7 +4476,7 @@ static void disas_sparc_insn(DisasContext * dc)
4476 save_state(dc, cpu_cond); 4476 save_state(dc, cpu_cond);
4477 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0); 4477 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4478 break; 4478 break;
4479 - case 0x13: /* load double word alternate */ 4479 + case 0x13: /* ldda, load double word alternate */
4480 #ifndef TARGET_SPARC64 4480 #ifndef TARGET_SPARC64
4481 if (IS_IMM) 4481 if (IS_IMM)
4482 goto illegal_insn; 4482 goto illegal_insn;
@@ -4488,7 +4488,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4488,7 +4488,7 @@ static void disas_sparc_insn(DisasContext * dc)
4488 save_state(dc, cpu_cond); 4488 save_state(dc, cpu_cond);
4489 gen_ldda_asi(cpu_val, cpu_addr, insn, rd); 4489 gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
4490 goto skip_move; 4490 goto skip_move;
4491 - case 0x19: /* load signed byte alternate */ 4491 + case 0x19: /* ldsba, load signed byte alternate */
4492 #ifndef TARGET_SPARC64 4492 #ifndef TARGET_SPARC64
4493 if (IS_IMM) 4493 if (IS_IMM)
4494 goto illegal_insn; 4494 goto illegal_insn;
@@ -4498,7 +4498,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4498,7 +4498,7 @@ static void disas_sparc_insn(DisasContext * dc)
4498 save_state(dc, cpu_cond); 4498 save_state(dc, cpu_cond);
4499 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1); 4499 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4500 break; 4500 break;
4501 - case 0x1a: /* load signed halfword alternate */ 4501 + case 0x1a: /* ldsha, load signed halfword alternate */
4502 #ifndef TARGET_SPARC64 4502 #ifndef TARGET_SPARC64
4503 if (IS_IMM) 4503 if (IS_IMM)
4504 goto illegal_insn; 4504 goto illegal_insn;
@@ -4518,7 +4518,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4518,7 +4518,7 @@ static void disas_sparc_insn(DisasContext * dc)
4518 save_state(dc, cpu_cond); 4518 save_state(dc, cpu_cond);
4519 gen_ldstub_asi(cpu_val, cpu_addr, insn); 4519 gen_ldstub_asi(cpu_val, cpu_addr, insn);
4520 break; 4520 break;
4521 - case 0x1f: /* swap reg with alt. memory. Also 4521 + case 0x1f: /* swapa, swap reg with alt. memory. Also
4522 atomically */ 4522 atomically */
4523 CHECK_IU_FEATURE(dc, SWAP); 4523 CHECK_IU_FEATURE(dc, SWAP);
4524 #ifndef TARGET_SPARC64 4524 #ifndef TARGET_SPARC64
@@ -4586,7 +4586,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4586,7 +4586,7 @@ static void disas_sparc_insn(DisasContext * dc)
4586 goto jmp_insn; 4586 goto jmp_insn;
4587 save_state(dc, cpu_cond); 4587 save_state(dc, cpu_cond);
4588 switch (xop) { 4588 switch (xop) {
4589 - case 0x20: /* load fpreg */ 4589 + case 0x20: /* ldf, load fpreg */
4590 gen_address_mask(dc, cpu_addr); 4590 gen_address_mask(dc, cpu_addr);
4591 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); 4591 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
4592 tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0); 4592 tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0);
@@ -4605,7 +4605,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4605,7 +4605,7 @@ static void disas_sparc_insn(DisasContext * dc)
4605 } 4605 }
4606 #endif 4606 #endif
4607 break; 4607 break;
4608 - case 0x22: /* load quad fpreg */ 4608 + case 0x22: /* ldqf, load quad fpreg */
4609 { 4609 {
4610 TCGv_i32 r_const; 4610 TCGv_i32 r_const;
4611 4611
@@ -4616,7 +4616,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4616,7 +4616,7 @@ static void disas_sparc_insn(DisasContext * dc)
4616 gen_op_store_QT0_fpr(QFPREG(rd)); 4616 gen_op_store_QT0_fpr(QFPREG(rd));
4617 } 4617 }
4618 break; 4618 break;
4619 - case 0x23: /* load double fpreg */ 4619 + case 0x23: /* lddf, load double fpreg */
4620 { 4620 {
4621 TCGv_i32 r_const; 4621 TCGv_i32 r_const;
4622 4622
@@ -4633,19 +4633,19 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4633,19 +4633,19 @@ static void disas_sparc_insn(DisasContext * dc)
4633 xop == 0xe || xop == 0x1e) { 4633 xop == 0xe || xop == 0x1e) {
4634 gen_movl_reg_TN(rd, cpu_val); 4634 gen_movl_reg_TN(rd, cpu_val);
4635 switch (xop) { 4635 switch (xop) {
4636 - case 0x4: /* store word */ 4636 + case 0x4: /* st, store word */
4637 gen_address_mask(dc, cpu_addr); 4637 gen_address_mask(dc, cpu_addr);
4638 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); 4638 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4639 break; 4639 break;
4640 - case 0x5: /* store byte */ 4640 + case 0x5: /* stb, store byte */
4641 gen_address_mask(dc, cpu_addr); 4641 gen_address_mask(dc, cpu_addr);
4642 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); 4642 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4643 break; 4643 break;
4644 - case 0x6: /* store halfword */ 4644 + case 0x6: /* sth, store halfword */
4645 gen_address_mask(dc, cpu_addr); 4645 gen_address_mask(dc, cpu_addr);
4646 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); 4646 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4647 break; 4647 break;
4648 - case 0x7: /* store double word */ 4648 + case 0x7: /* std, store double word */
4649 if (rd & 1) 4649 if (rd & 1)
4650 goto illegal_insn; 4650 goto illegal_insn;
4651 else { 4651 else {
@@ -4662,7 +4662,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4662,7 +4662,7 @@ static void disas_sparc_insn(DisasContext * dc)
4662 } 4662 }
4663 break; 4663 break;
4664 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 4664 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4665 - case 0x14: /* store word alternate */ 4665 + case 0x14: /* sta, V9 stwa, store word alternate */
4666 #ifndef TARGET_SPARC64 4666 #ifndef TARGET_SPARC64
4667 if (IS_IMM) 4667 if (IS_IMM)
4668 goto illegal_insn; 4668 goto illegal_insn;
@@ -4672,7 +4672,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4672,7 +4672,7 @@ static void disas_sparc_insn(DisasContext * dc)
4672 save_state(dc, cpu_cond); 4672 save_state(dc, cpu_cond);
4673 gen_st_asi(cpu_val, cpu_addr, insn, 4); 4673 gen_st_asi(cpu_val, cpu_addr, insn, 4);
4674 break; 4674 break;
4675 - case 0x15: /* store byte alternate */ 4675 + case 0x15: /* stba, store byte alternate */
4676 #ifndef TARGET_SPARC64 4676 #ifndef TARGET_SPARC64
4677 if (IS_IMM) 4677 if (IS_IMM)
4678 goto illegal_insn; 4678 goto illegal_insn;
@@ -4682,7 +4682,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4682,7 +4682,7 @@ static void disas_sparc_insn(DisasContext * dc)
4682 save_state(dc, cpu_cond); 4682 save_state(dc, cpu_cond);
4683 gen_st_asi(cpu_val, cpu_addr, insn, 1); 4683 gen_st_asi(cpu_val, cpu_addr, insn, 1);
4684 break; 4684 break;
4685 - case 0x16: /* store halfword alternate */ 4685 + case 0x16: /* stha, store halfword alternate */
4686 #ifndef TARGET_SPARC64 4686 #ifndef TARGET_SPARC64
4687 if (IS_IMM) 4687 if (IS_IMM)
4688 goto illegal_insn; 4688 goto illegal_insn;
@@ -4692,7 +4692,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4692,7 +4692,7 @@ static void disas_sparc_insn(DisasContext * dc)
4692 save_state(dc, cpu_cond); 4692 save_state(dc, cpu_cond);
4693 gen_st_asi(cpu_val, cpu_addr, insn, 2); 4693 gen_st_asi(cpu_val, cpu_addr, insn, 2);
4694 break; 4694 break;
4695 - case 0x17: /* store double word alternate */ 4695 + case 0x17: /* stda, store double word alternate */
4696 #ifndef TARGET_SPARC64 4696 #ifndef TARGET_SPARC64
4697 if (IS_IMM) 4697 if (IS_IMM)
4698 goto illegal_insn; 4698 goto illegal_insn;
@@ -4725,7 +4725,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4725,7 +4725,7 @@ static void disas_sparc_insn(DisasContext * dc)
4725 goto jmp_insn; 4725 goto jmp_insn;
4726 save_state(dc, cpu_cond); 4726 save_state(dc, cpu_cond);
4727 switch (xop) { 4727 switch (xop) {
4728 - case 0x24: /* store fpreg */ 4728 + case 0x24: /* stf, store fpreg */
4729 gen_address_mask(dc, cpu_addr); 4729 gen_address_mask(dc, cpu_addr);
4730 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]); 4730 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]);
4731 tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx); 4731 tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx);
@@ -4768,7 +4768,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4768,7 +4768,7 @@ static void disas_sparc_insn(DisasContext * dc)
4768 goto nfq_insn; 4768 goto nfq_insn;
4769 #endif 4769 #endif
4770 #endif 4770 #endif
4771 - case 0x27: /* store double fpreg */ 4771 + case 0x27: /* stdf, store double fpreg */
4772 { 4772 {
4773 TCGv_i32 r_const; 4773 TCGv_i32 r_const;
4774 4774