gwj / at91sam9263 · Commits

Commit b6d96beda3a6cbf20a2d04a609eff78adebd8859

Authored by ths
1 parent bd5921b4

Use temporary registers for the MIPS FPU emulation. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4861 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 5 changed files with 1849 additions and 984 deletions
target-mips/cpu.h
  View file @b6d96be
... ... @@ -171,20 +171,14 @@ typedef struct CPUMIPSState CPUMIPSState;
171 171 struct CPUMIPSState {
172 172 TCState active_tc;
173 173  
174   - /* temporary hack for FP globals */
175   -#ifndef USE_HOST_FLOAT_REGS
176   - fpr_t ft0;
177   - fpr_t ft1;
178   - fpr_t ft2;
179   -#endif
180 174 CPUMIPSMVPContext *mvp;
181 175 CPUMIPSTLBContext *tlb;
182 176 CPUMIPSFPUContext *fpu;
183 177 uint32_t current_tc;
184 178  
185 179 uint32_t SEGBITS;
186   - target_ulong SEGMask;
187 180 uint32_t PABITS;
  181 + target_ulong SEGMask;
188 182 target_ulong PAMask;
189 183  
190 184 int32_t CP0_Index;
... ...
target-mips/exec.h
  View file @b6d96be
... ... @@ -10,29 +10,6 @@
10 10  
11 11 register struct CPUMIPSState *env asm(AREG0);
12 12  
13   -#if defined (USE_HOST_FLOAT_REGS)
14   -#error "implement me."
15   -#else
16   -#define FDT0 (env->ft0.fd)
17   -#define FDT1 (env->ft1.fd)
18   -#define FDT2 (env->ft2.fd)
19   -#define FST0 (env->ft0.fs[FP_ENDIAN_IDX])
20   -#define FST1 (env->ft1.fs[FP_ENDIAN_IDX])
21   -#define FST2 (env->ft2.fs[FP_ENDIAN_IDX])
22   -#define FSTH0 (env->ft0.fs[!FP_ENDIAN_IDX])
23   -#define FSTH1 (env->ft1.fs[!FP_ENDIAN_IDX])
24   -#define FSTH2 (env->ft2.fs[!FP_ENDIAN_IDX])
25   -#define DT0 (env->ft0.d)
26   -#define DT1 (env->ft1.d)
27   -#define DT2 (env->ft2.d)
28   -#define WT0 (env->ft0.w[FP_ENDIAN_IDX])
29   -#define WT1 (env->ft1.w[FP_ENDIAN_IDX])
30   -#define WT2 (env->ft2.w[FP_ENDIAN_IDX])
31   -#define WTH0 (env->ft0.w[!FP_ENDIAN_IDX])
32   -#define WTH1 (env->ft1.w[!FP_ENDIAN_IDX])
33   -#define WTH2 (env->ft2.w[!FP_ENDIAN_IDX])
34   -#endif
35   -
36 13 #include "cpu.h"
37 14 #include "exec-all.h"
38 15  
... ...
target-mips/helper.h
  View file @b6d96be
... ... @@ -159,67 +159,85 @@ DEF_HELPER(target_ulong, do_yield, (target_ulong t0))
159 159 DEF_HELPER(target_ulong, do_cfc1, (uint32_t reg))
160 160 DEF_HELPER(void, do_ctc1, (target_ulong t0, uint32_t reg))
161 161  
162   -DEF_HELPER(void, do_float_cvtd_s, (void))
163   -DEF_HELPER(void, do_float_cvtd_w, (void))
164   -DEF_HELPER(void, do_float_cvtd_l, (void))
165   -DEF_HELPER(void, do_float_cvtl_d, (void))
166   -DEF_HELPER(void, do_float_cvtl_s, (void))
167   -DEF_HELPER(void, do_float_cvtps_pw, (void))
168   -DEF_HELPER(void, do_float_cvtpw_ps, (void))
169   -DEF_HELPER(void, do_float_cvts_d, (void))
170   -DEF_HELPER(void, do_float_cvts_w, (void))
171   -DEF_HELPER(void, do_float_cvts_l, (void))
172   -DEF_HELPER(void, do_float_cvts_pl, (void))
173   -DEF_HELPER(void, do_float_cvts_pu, (void))
174   -DEF_HELPER(void, do_float_cvtw_s, (void))
175   -DEF_HELPER(void, do_float_cvtw_d, (void))
  162 +DEF_HELPER(uint64_t, do_float_cvtd_s, (uint32_t fst0))
  163 +DEF_HELPER(uint64_t, do_float_cvtd_w, (uint32_t wt0))
  164 +DEF_HELPER(uint64_t, do_float_cvtd_l, (uint64_t dt0))
  165 +DEF_HELPER(uint64_t, do_float_cvtl_d, (uint64_t fd0))
  166 +DEF_HELPER(uint64_t, do_float_cvtl_s, (uint32_t fst0))
  167 +DEF_HELPER(uint64_t, do_float_cvtps_pw, (uint64_t dt0))
  168 +DEF_HELPER(uint64_t, do_float_cvtpw_ps, (uint64_t fdt0))
  169 +DEF_HELPER(uint32_t, do_float_cvts_d, (uint64_t fd0))
  170 +DEF_HELPER(uint32_t, do_float_cvts_w, (uint32_t wt0))
  171 +DEF_HELPER(uint32_t, do_float_cvts_l, (uint64_t dt0))
  172 +DEF_HELPER(uint32_t, do_float_cvts_pl, (uint32_t wt0))
  173 +DEF_HELPER(uint32_t, do_float_cvts_pu, (uint32_t wth0))
  174 +DEF_HELPER(uint32_t, do_float_cvtw_s, (uint32_t fst0))
  175 +DEF_HELPER(uint32_t, do_float_cvtw_d, (uint64_t fd0))
176 176  
177   -DEF_HELPER(void, do_float_addr_ps, (void))
178   -DEF_HELPER(void, do_float_mulr_ps, (void))
  177 +DEF_HELPER(uint64_t, do_float_addr_ps, (uint64_t fdt0, uint64_t fdt1))
  178 +DEF_HELPER(uint64_t, do_float_mulr_ps, (uint64_t fdt0, uint64_t fdt1))
179 179  
180   -#define FOP_PROTO(op) \
181   -DEF_HELPER(void, do_float_ ## op ## _s, (void)) \
182   -DEF_HELPER(void, do_float_ ## op ## _d, (void))
  180 +#define FOP_PROTO(op) \
  181 +DEF_HELPER(uint64_t, do_float_ ## op ## l_s, (uint32_t fst0)) \
  182 +DEF_HELPER(uint64_t, do_float_ ## op ## l_d, (uint64_t fdt0)) \
  183 +DEF_HELPER(uint32_t, do_float_ ## op ## w_s, (uint32_t fst0)) \
  184 +DEF_HELPER(uint32_t, do_float_ ## op ## w_d, (uint64_t fdt0))
  185 +FOP_PROTO(round)
  186 +FOP_PROTO(trunc)
  187 +FOP_PROTO(ceil)
  188 +FOP_PROTO(floor)
  189 +#undef FOP_PROTO
  190 +
  191 +#define FOP_PROTO(op) \
  192 +DEF_HELPER(uint32_t, do_float_ ## op ## _s, (uint32_t fst0)) \
  193 +DEF_HELPER(uint64_t, do_float_ ## op ## _d, (uint64_t fdt0))
183 194 FOP_PROTO(sqrt)
184   -FOP_PROTO(roundl)
185   -FOP_PROTO(roundw)
186   -FOP_PROTO(truncl)
187   -FOP_PROTO(truncw)
188   -FOP_PROTO(ceill)
189   -FOP_PROTO(ceilw)
190   -FOP_PROTO(floorl)
191   -FOP_PROTO(floorw)
192 195 FOP_PROTO(rsqrt)
193 196 FOP_PROTO(recip)
194 197 #undef FOP_PROTO
195 198  
196   -#define FOP_PROTO(op) \
197   -DEF_HELPER(void, do_float_ ## op ## _s, (void)) \
198   -DEF_HELPER(void, do_float_ ## op ## _d, (void)) \
199   -DEF_HELPER(void, do_float_ ## op ## _ps, (void))
  199 +#define FOP_PROTO(op) \
  200 +DEF_HELPER(uint32_t, do_float_ ## op ## _s, (uint32_t fst0)) \
  201 +DEF_HELPER(uint64_t, do_float_ ## op ## _d, (uint64_t fdt0)) \
  202 +DEF_HELPER(uint64_t, do_float_ ## op ## _ps, (uint64_t fdt0))
  203 +FOP_PROTO(abs)
  204 +FOP_PROTO(chs)
  205 +FOP_PROTO(recip1)
  206 +FOP_PROTO(rsqrt1)
  207 +#undef FOP_PROTO
  208 +
  209 +#define FOP_PROTO(op) \
  210 +DEF_HELPER(uint32_t, do_float_ ## op ## _s, (uint32_t fst0, uint32_t fst2)) \
  211 +DEF_HELPER(uint64_t, do_float_ ## op ## _d, (uint64_t fdt0, uint64_t fdt2)) \
  212 +DEF_HELPER(uint64_t, do_float_ ## op ## _ps, (uint64_t fdt0, uint64_t fdt2))
200 213 FOP_PROTO(add)
201 214 FOP_PROTO(sub)
202 215 FOP_PROTO(mul)
203 216 FOP_PROTO(div)
204   -FOP_PROTO(abs)
205   -FOP_PROTO(chs)
  217 +FOP_PROTO(recip2)
  218 +FOP_PROTO(rsqrt2)
  219 +#undef FOP_PROTO
  220 +
  221 +#define FOP_PROTO(op) \
  222 +DEF_HELPER(uint32_t, do_float_ ## op ## _s, (uint32_t fst0, uint32_t fst1, \
  223 + uint32_t fst2)) \
  224 +DEF_HELPER(uint64_t, do_float_ ## op ## _d, (uint64_t fdt0, uint64_t fdt1, \
  225 + uint64_t fdt2)) \
  226 +DEF_HELPER(uint64_t, do_float_ ## op ## _ps, (uint64_t fdt0, uint64_t fdt1, \
  227 + uint64_t fdt2))
206 228 FOP_PROTO(muladd)
207 229 FOP_PROTO(mulsub)
208 230 FOP_PROTO(nmuladd)
209 231 FOP_PROTO(nmulsub)
210   -FOP_PROTO(recip1)
211   -FOP_PROTO(recip2)
212   -FOP_PROTO(rsqrt1)
213   -FOP_PROTO(rsqrt2)
214 232 #undef FOP_PROTO
215 233  
216   -#define FOP_PROTO(op) \
217   -DEF_HELPER(void, do_cmp_d_ ## op, (long cc)) \
218   -DEF_HELPER(void, do_cmpabs_d_ ## op, (long cc)) \
219   -DEF_HELPER(void, do_cmp_s_ ## op, (long cc)) \
220   -DEF_HELPER(void, do_cmpabs_s_ ## op, (long cc)) \
221   -DEF_HELPER(void, do_cmp_ps_ ## op, (long cc)) \
222   -DEF_HELPER(void, do_cmpabs_ps_ ## op, (long cc))
  234 +#define FOP_PROTO(op) \
  235 +DEF_HELPER(void, do_cmp_d_ ## op, (uint64_t fdt0, uint64_t fdt1, int cc)) \
  236 +DEF_HELPER(void, do_cmpabs_d_ ## op, (uint64_t fdt0, uint64_t fdt1, int cc)) \
  237 +DEF_HELPER(void, do_cmp_s_ ## op, (uint32_t fst0, uint32_t fst1, int cc)) \
  238 +DEF_HELPER(void, do_cmpabs_s_ ## op, (uint32_t fst0, uint32_t fst1, int cc)) \
  239 +DEF_HELPER(void, do_cmp_ps_ ## op, (uint64_t fdt0, uint64_t fdt1, int cc)) \
  240 +DEF_HELPER(void, do_cmpabs_ps_ ## op, (uint64_t fdt0, uint64_t fdt1, int cc))
223 241 FOP_PROTO(f)
224 242 FOP_PROTO(un)
225 243 FOP_PROTO(eq)
... ...
target-mips/op_helper.c
  View file @b6d96be
... ... @@ -2121,380 +2121,555 @@ static always_inline void update_fcr31(void)
2121 2121 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2122 2122 paired single lower "pl", paired single upper "pu". */
2123 2123  
2124   -#define FLOAT_OP(name, p) void do_float_##name##_##p(void)
2125   -
2126 2124 /* unary operations, modifying fp status */
2127   -#define FLOAT_UNOP(name) \
2128   -FLOAT_OP(name, d) \
2129   -{ \
2130   - FDT2 = float64_ ## name(FDT0, &env->fpu->fp_status); \
2131   -} \
2132   -FLOAT_OP(name, s) \
2133   -{ \
2134   - FST2 = float32_ ## name(FST0, &env->fpu->fp_status); \
2135   -}
2136   -FLOAT_UNOP(sqrt)
2137   -#undef FLOAT_UNOP
  2125 +uint64_t do_float_sqrt_d(uint64_t fdt0)
  2126 +{
  2127 + return float64_sqrt(fdt0, &env->fpu->fp_status);
  2128 +}
  2129 +
  2130 +uint32_t do_float_sqrt_s(uint32_t fst0)
  2131 +{
  2132 + return float32_sqrt(fst0, &env->fpu->fp_status);
  2133 +}
2138 2134  
2139   -FLOAT_OP(cvtd, s)
  2135 +uint64_t do_float_cvtd_s(uint32_t fst0)
2140 2136 {
  2137 + uint64_t fdt2;
  2138 +
2141 2139 set_float_exception_flags(0, &env->fpu->fp_status);
2142   - FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
  2140 + fdt2 = float32_to_float64(fst0, &env->fpu->fp_status);
2143 2141 update_fcr31();
  2142 + return fdt2;
2144 2143 }
2145   -FLOAT_OP(cvtd, w)
  2144 +
  2145 +uint64_t do_float_cvtd_w(uint32_t wt0)
2146 2146 {
  2147 + uint64_t fdt2;
  2148 +
2147 2149 set_float_exception_flags(0, &env->fpu->fp_status);
2148   - FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
  2150 + fdt2 = int32_to_float64(wt0, &env->fpu->fp_status);
2149 2151 update_fcr31();
  2152 + return fdt2;
2150 2153 }
2151   -FLOAT_OP(cvtd, l)
  2154 +
  2155 +uint64_t do_float_cvtd_l(uint64_t dt0)
2152 2156 {
  2157 + uint64_t fdt2;
  2158 +
2153 2159 set_float_exception_flags(0, &env->fpu->fp_status);
2154   - FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
  2160 + fdt2 = int64_to_float64(dt0, &env->fpu->fp_status);
2155 2161 update_fcr31();
  2162 + return fdt2;
2156 2163 }
2157   -FLOAT_OP(cvtl, d)
  2164 +
  2165 +uint64_t do_float_cvtl_d(uint64_t fdt0)
2158 2166 {
  2167 + uint64_t dt2;
  2168 +
2159 2169 set_float_exception_flags(0, &env->fpu->fp_status);
2160   - DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
  2170 + dt2 = float64_to_int64(fdt0, &env->fpu->fp_status);
2161 2171 update_fcr31();
2162 2172 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2163   - DT2 = FLOAT_SNAN64;
  2173 + dt2 = FLOAT_SNAN64;
  2174 + return dt2;
2164 2175 }
2165   -FLOAT_OP(cvtl, s)
  2176 +
  2177 +uint64_t do_float_cvtl_s(uint32_t fst0)
2166 2178 {
  2179 + uint64_t dt2;
  2180 +
2167 2181 set_float_exception_flags(0, &env->fpu->fp_status);
2168   - DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
  2182 + dt2 = float32_to_int64(fst0, &env->fpu->fp_status);
2169 2183 update_fcr31();
2170 2184 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2171   - DT2 = FLOAT_SNAN64;
  2185 + dt2 = FLOAT_SNAN64;
  2186 + return dt2;
2172 2187 }
2173 2188  
2174   -FLOAT_OP(cvtps, pw)
  2189 +uint64_t do_float_cvtps_pw(uint64_t dt0)
2175 2190 {
  2191 + uint32_t fst2;
  2192 + uint32_t fsth2;
  2193 +
2176 2194 set_float_exception_flags(0, &env->fpu->fp_status);
2177   - FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
2178   - FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
  2195 + fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->fpu->fp_status);
  2196 + fsth2 = int32_to_float32(dt0 >> 32, &env->fpu->fp_status);
2179 2197 update_fcr31();
  2198 + return ((uint64_t)fsth2 << 32) | fst2;
2180 2199 }
2181   -FLOAT_OP(cvtpw, ps)
  2200 +
  2201 +uint64_t do_float_cvtpw_ps(uint64_t fdt0)
2182 2202 {
  2203 + uint32_t wt2;
  2204 + uint32_t wth2;
  2205 +
2183 2206 set_float_exception_flags(0, &env->fpu->fp_status);
2184   - WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
2185   - WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
  2207 + wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->fpu->fp_status);
  2208 + wth2 = float32_to_int32(fdt0 >> 32, &env->fpu->fp_status);
2186 2209 update_fcr31();
2187   - if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2188   - WT2 = FLOAT_SNAN32;
  2210 + if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) {
  2211 + wt2 = FLOAT_SNAN32;
  2212 + wth2 = FLOAT_SNAN32;
  2213 + }
  2214 + return ((uint64_t)wth2 << 32) | wt2;
2189 2215 }
2190   -FLOAT_OP(cvts, d)
  2216 +
  2217 +uint32_t do_float_cvts_d(uint64_t fdt0)
2191 2218 {
  2219 + uint32_t fst2;
  2220 +
2192 2221 set_float_exception_flags(0, &env->fpu->fp_status);
2193   - FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
  2222 + fst2 = float64_to_float32(fdt0, &env->fpu->fp_status);
2194 2223 update_fcr31();
  2224 + return fst2;
2195 2225 }
2196   -FLOAT_OP(cvts, w)
  2226 +
  2227 +uint32_t do_float_cvts_w(uint32_t wt0)
2197 2228 {
  2229 + uint32_t fst2;
  2230 +
2198 2231 set_float_exception_flags(0, &env->fpu->fp_status);
2199   - FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
  2232 + fst2 = int32_to_float32(wt0, &env->fpu->fp_status);
2200 2233 update_fcr31();
  2234 + return fst2;
2201 2235 }
2202   -FLOAT_OP(cvts, l)
  2236 +
  2237 +uint32_t do_float_cvts_l(uint64_t dt0)
2203 2238 {
  2239 + uint32_t fst2;
  2240 +
2204 2241 set_float_exception_flags(0, &env->fpu->fp_status);
2205   - FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
  2242 + fst2 = int64_to_float32(dt0, &env->fpu->fp_status);
2206 2243 update_fcr31();
  2244 + return fst2;
2207 2245 }
2208   -FLOAT_OP(cvts, pl)
  2246 +
  2247 +uint32_t do_float_cvts_pl(uint32_t wt0)
2209 2248 {
  2249 + uint32_t wt2;
  2250 +
2210 2251 set_float_exception_flags(0, &env->fpu->fp_status);
2211   - WT2 = WT0;
  2252 + wt2 = wt0;
2212 2253 update_fcr31();
  2254 + return wt2;
2213 2255 }
2214   -FLOAT_OP(cvts, pu)
  2256 +
  2257 +uint32_t do_float_cvts_pu(uint32_t wth0)
2215 2258 {
  2259 + uint32_t wt2;
  2260 +
2216 2261 set_float_exception_flags(0, &env->fpu->fp_status);
2217   - WT2 = WTH0;
  2262 + wt2 = wth0;
2218 2263 update_fcr31();
  2264 + return wt2;
2219 2265 }
2220   -FLOAT_OP(cvtw, s)
  2266 +
  2267 +uint32_t do_float_cvtw_s(uint32_t fst0)
2221 2268 {
  2269 + uint32_t wt2;
  2270 +
2222 2271 set_float_exception_flags(0, &env->fpu->fp_status);
2223   - WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
  2272 + wt2 = float32_to_int32(fst0, &env->fpu->fp_status);
2224 2273 update_fcr31();
2225 2274 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2226   - WT2 = FLOAT_SNAN32;
  2275 + wt2 = FLOAT_SNAN32;
  2276 + return wt2;
2227 2277 }
2228   -FLOAT_OP(cvtw, d)
  2278 +
  2279 +uint32_t do_float_cvtw_d(uint64_t fdt0)
2229 2280 {
  2281 + uint32_t wt2;
  2282 +
2230 2283 set_float_exception_flags(0, &env->fpu->fp_status);
2231   - WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
  2284 + wt2 = float64_to_int32(fdt0, &env->fpu->fp_status);
2232 2285 update_fcr31();
2233 2286 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2234   - WT2 = FLOAT_SNAN32;
  2287 + wt2 = FLOAT_SNAN32;
  2288 + return wt2;
2235 2289 }
2236 2290  
2237   -FLOAT_OP(roundl, d)
  2291 +uint64_t do_float_roundl_d(uint64_t fdt0)
2238 2292 {
  2293 + uint64_t dt2;
  2294 +
2239 2295 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
2240   - DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
  2296 + dt2 = float64_to_int64(fdt0, &env->fpu->fp_status);
2241 2297 RESTORE_ROUNDING_MODE;
2242 2298 update_fcr31();
2243 2299 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2244   - DT2 = FLOAT_SNAN64;
  2300 + dt2 = FLOAT_SNAN64;
  2301 + return dt2;
2245 2302 }
2246   -FLOAT_OP(roundl, s)
  2303 +
  2304 +uint64_t do_float_roundl_s(uint32_t fst0)
2247 2305 {
  2306 + uint64_t dt2;
  2307 +
2248 2308 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
2249   - DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
  2309 + dt2 = float32_to_int64(fst0, &env->fpu->fp_status);
2250 2310 RESTORE_ROUNDING_MODE;
2251 2311 update_fcr31();
2252 2312 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2253   - DT2 = FLOAT_SNAN64;
  2313 + dt2 = FLOAT_SNAN64;
  2314 + return dt2;
2254 2315 }
2255   -FLOAT_OP(roundw, d)
  2316 +
  2317 +uint32_t do_float_roundw_d(uint64_t fdt0)
2256 2318 {
  2319 + uint32_t wt2;
  2320 +
2257 2321 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
2258   - WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
  2322 + wt2 = float64_to_int32(fdt0, &env->fpu->fp_status);
2259 2323 RESTORE_ROUNDING_MODE;
2260 2324 update_fcr31();
2261 2325 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2262   - WT2 = FLOAT_SNAN32;
  2326 + wt2 = FLOAT_SNAN32;
  2327 + return wt2;
2263 2328 }
2264   -FLOAT_OP(roundw, s)
  2329 +
  2330 +uint32_t do_float_roundw_s(uint32_t fst0)
2265 2331 {
  2332 + uint32_t wt2;
  2333 +
2266 2334 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
2267   - WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
  2335 + wt2 = float32_to_int32(fst0, &env->fpu->fp_status);
2268 2336 RESTORE_ROUNDING_MODE;
2269 2337 update_fcr31();
2270 2338 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2271   - WT2 = FLOAT_SNAN32;
  2339 + wt2 = FLOAT_SNAN32;
  2340 + return wt2;
2272 2341 }
2273 2342  
2274   -FLOAT_OP(truncl, d)
  2343 +uint64_t do_float_truncl_d(uint64_t fdt0)
2275 2344 {
2276   - DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
  2345 + uint64_t dt2;
  2346 +
  2347 + dt2 = float64_to_int64_round_to_zero(fdt0, &env->fpu->fp_status);
2277 2348 update_fcr31();
2278 2349 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2279   - DT2 = FLOAT_SNAN64;
  2350 + dt2 = FLOAT_SNAN64;
  2351 + return dt2;
2280 2352 }
2281   -FLOAT_OP(truncl, s)
  2353 +
  2354 +uint64_t do_float_truncl_s(uint32_t fst0)
2282 2355 {
2283   - DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
  2356 + uint64_t dt2;
  2357 +
  2358 + dt2 = float32_to_int64_round_to_zero(fst0, &env->fpu->fp_status);
2284 2359 update_fcr31();
2285 2360 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2286   - DT2 = FLOAT_SNAN64;
  2361 + dt2 = FLOAT_SNAN64;
  2362 + return dt2;
2287 2363 }
2288   -FLOAT_OP(truncw, d)
  2364 +
  2365 +uint32_t do_float_truncw_d(uint64_t fdt0)
2289 2366 {
2290   - WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
  2367 + uint32_t wt2;
  2368 +
  2369 + wt2 = float64_to_int32_round_to_zero(fdt0, &env->fpu->fp_status);
2291 2370 update_fcr31();
2292 2371 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2293   - WT2 = FLOAT_SNAN32;
  2372 + wt2 = FLOAT_SNAN32;
  2373 + return wt2;
2294 2374 }
2295   -FLOAT_OP(truncw, s)
  2375 +
  2376 +uint32_t do_float_truncw_s(uint32_t fst0)
2296 2377 {
2297   - WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
  2378 + uint32_t wt2;
  2379 +
  2380 + wt2 = float32_to_int32_round_to_zero(fst0, &env->fpu->fp_status);
2298 2381 update_fcr31();
2299 2382 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2300   - WT2 = FLOAT_SNAN32;
  2383 + wt2 = FLOAT_SNAN32;
  2384 + return wt2;
2301 2385 }
2302 2386  
2303   -FLOAT_OP(ceill, d)
  2387 +uint64_t do_float_ceill_d(uint64_t fdt0)
2304 2388 {
  2389 + uint64_t dt2;
  2390 +
2305 2391 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
2306   - DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
  2392 + dt2 = float64_to_int64(fdt0, &env->fpu->fp_status);
2307 2393 RESTORE_ROUNDING_MODE;
2308 2394 update_fcr31();
2309 2395 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2310   - DT2 = FLOAT_SNAN64;
  2396 + dt2 = FLOAT_SNAN64;
  2397 + return dt2;
2311 2398 }
2312   -FLOAT_OP(ceill, s)
  2399 +
  2400 +uint64_t do_float_ceill_s(uint32_t fst0)
2313 2401 {
  2402 + uint64_t dt2;
  2403 +
2314 2404 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
2315   - DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
  2405 + dt2 = float32_to_int64(fst0, &env->fpu->fp_status);
2316 2406 RESTORE_ROUNDING_MODE;
2317 2407 update_fcr31();
2318 2408 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2319   - DT2 = FLOAT_SNAN64;
  2409 + dt2 = FLOAT_SNAN64;
  2410 + return dt2;
2320 2411 }
2321   -FLOAT_OP(ceilw, d)
  2412 +
  2413 +uint32_t do_float_ceilw_d(uint64_t fdt0)
2322 2414 {
  2415 + uint32_t wt2;
  2416 +
2323 2417 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
2324   - WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
  2418 + wt2 = float64_to_int32(fdt0, &env->fpu->fp_status);
2325 2419 RESTORE_ROUNDING_MODE;
2326 2420 update_fcr31();
2327 2421 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2328   - WT2 = FLOAT_SNAN32;
  2422 + wt2 = FLOAT_SNAN32;
  2423 + return wt2;
2329 2424 }
2330   -FLOAT_OP(ceilw, s)
  2425 +
  2426 +uint32_t do_float_ceilw_s(uint32_t fst0)
2331 2427 {
  2428 + uint32_t wt2;
  2429 +
2332 2430 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
2333   - WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
  2431 + wt2 = float32_to_int32(fst0, &env->fpu->fp_status);
2334 2432 RESTORE_ROUNDING_MODE;
2335 2433 update_fcr31();
2336 2434 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2337   - WT2 = FLOAT_SNAN32;
  2435 + wt2 = FLOAT_SNAN32;
  2436 + return wt2;
2338 2437 }
2339 2438  
2340   -FLOAT_OP(floorl, d)
  2439 +uint64_t do_float_floorl_d(uint64_t fdt0)
2341 2440 {
  2441 + uint64_t dt2;
  2442 +
2342 2443 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
2343   - DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
  2444 + dt2 = float64_to_int64(fdt0, &env->fpu->fp_status);
2344 2445 RESTORE_ROUNDING_MODE;
2345 2446 update_fcr31();
2346 2447 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2347   - DT2 = FLOAT_SNAN64;
  2448 + dt2 = FLOAT_SNAN64;
  2449 + return dt2;
2348 2450 }
2349   -FLOAT_OP(floorl, s)
  2451 +
  2452 +uint64_t do_float_floorl_s(uint32_t fst0)
2350 2453 {
  2454 + uint64_t dt2;
  2455 +
2351 2456 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
2352   - DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
  2457 + dt2 = float32_to_int64(fst0, &env->fpu->fp_status);
2353 2458 RESTORE_ROUNDING_MODE;
2354 2459 update_fcr31();
2355 2460 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2356   - DT2 = FLOAT_SNAN64;
  2461 + dt2 = FLOAT_SNAN64;
  2462 + return dt2;
2357 2463 }
2358   -FLOAT_OP(floorw, d)
  2464 +
  2465 +uint32_t do_float_floorw_d(uint64_t fdt0)
2359 2466 {
  2467 + uint32_t wt2;
  2468 +
2360 2469 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
2361   - WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
  2470 + wt2 = float64_to_int32(fdt0, &env->fpu->fp_status);
2362 2471 RESTORE_ROUNDING_MODE;
2363 2472 update_fcr31();
2364 2473 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2365   - WT2 = FLOAT_SNAN32;
  2474 + wt2 = FLOAT_SNAN32;
  2475 + return wt2;
2366 2476 }
2367   -FLOAT_OP(floorw, s)
  2477 +
  2478 +uint32_t do_float_floorw_s(uint32_t fst0)
2368 2479 {
  2480 + uint32_t wt2;
  2481 +
2369 2482 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
2370   - WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
  2483 + wt2 = float32_to_int32(fst0, &env->fpu->fp_status);
2371 2484 RESTORE_ROUNDING_MODE;
2372 2485 update_fcr31();
2373 2486 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
2374   - WT2 = FLOAT_SNAN32;
  2487 + wt2 = FLOAT_SNAN32;
  2488 + return wt2;
2375 2489 }
2376 2490  
2377 2491 /* unary operations, not modifying fp status */
2378   -#define FLOAT_UNOP(name) \
2379   -FLOAT_OP(name, d) \
2380   -{ \
2381   - FDT2 = float64_ ## name(FDT0); \
2382   -} \
2383   -FLOAT_OP(name, s) \
2384   -{ \
2385   - FST2 = float32_ ## name(FST0); \
2386   -} \
2387   -FLOAT_OP(name, ps) \
2388   -{ \
2389   - FST2 = float32_ ## name(FST0); \
2390   - FSTH2 = float32_ ## name(FSTH0); \
  2492 +#define FLOAT_UNOP(name) \
  2493 +uint64_t do_float_ ## name ## _d(uint64_t fdt0) \
  2494 +{ \
  2495 + return float64_ ## name(fdt0); \
  2496 +} \
  2497 +uint32_t do_float_ ## name ## _s(uint32_t fst0) \
  2498 +{ \
  2499 + return float32_ ## name(fst0); \
  2500 +} \
  2501 +uint64_t do_float_ ## name ## _ps(uint64_t fdt0) \
  2502 +{ \
  2503 + uint32_t wt0; \
  2504 + uint32_t wth0; \
  2505 + \
  2506 + wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
  2507 + wth0 = float32_ ## name(fdt0 >> 32); \
  2508 + return ((uint64_t)wth0 << 32) | wt0; \
2391 2509 }
2392 2510 FLOAT_UNOP(abs)
2393 2511 FLOAT_UNOP(chs)
2394 2512 #undef FLOAT_UNOP
2395 2513  
2396 2514 /* MIPS specific unary operations */
2397   -FLOAT_OP(recip, d)
  2515 +uint64_t do_float_recip_d(uint64_t fdt0)
2398 2516 {
  2517 + uint64_t fdt2;
  2518 +
2399 2519 set_float_exception_flags(0, &env->fpu->fp_status);
2400   - FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
  2520 + fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->fpu->fp_status);
2401 2521 update_fcr31();
  2522 + return fdt2;
2402 2523 }
2403   -FLOAT_OP(recip, s)
  2524 +
  2525 +uint32_t do_float_recip_s(uint32_t fst0)
2404 2526 {
  2527 + uint32_t fst2;
  2528 +
2405 2529 set_float_exception_flags(0, &env->fpu->fp_status);
2406   - FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
  2530 + fst2 = float32_div(FLOAT_ONE32, fst0, &env->fpu->fp_status);
2407 2531 update_fcr31();
  2532 + return fst2;
2408 2533 }
2409 2534  
2410   -FLOAT_OP(rsqrt, d)
  2535 +uint64_t do_float_rsqrt_d(uint64_t fdt0)
2411 2536 {
  2537 + uint64_t fdt2;
  2538 +
2412 2539 set_float_exception_flags(0, &env->fpu->fp_status);
2413   - FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
2414   - FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
  2540 + fdt2 = float64_sqrt(fdt0, &env->fpu->fp_status);
  2541 + fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->fpu->fp_status);
2415 2542 update_fcr31();
  2543 + return fdt2;
2416 2544 }
2417   -FLOAT_OP(rsqrt, s)
  2545 +
  2546 +uint32_t do_float_rsqrt_s(uint32_t fst0)
2418 2547 {
  2548 + uint32_t fst2;
  2549 +
2419 2550 set_float_exception_flags(0, &env->fpu->fp_status);
2420   - FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
2421   - FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
  2551 + fst2 = float32_sqrt(fst0, &env->fpu->fp_status);
  2552 + fst2 = float32_div(FLOAT_ONE32, fst2, &env->fpu->fp_status);
2422 2553 update_fcr31();
  2554 + return fst2;
2423 2555 }
2424 2556  
2425   -FLOAT_OP(recip1, d)
  2557 +uint64_t do_float_recip1_d(uint64_t fdt0)
2426 2558 {
  2559 + uint64_t fdt2;
  2560 +
2427 2561 set_float_exception_flags(0, &env->fpu->fp_status);
2428   - FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
  2562 + fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->fpu->fp_status);
2429 2563 update_fcr31();
  2564 + return fdt2;
2430 2565 }
2431   -FLOAT_OP(recip1, s)
  2566 +
  2567 +uint32_t do_float_recip1_s(uint32_t fst0)
2432 2568 {
  2569 + uint32_t fst2;
  2570 +
2433 2571 set_float_exception_flags(0, &env->fpu->fp_status);
2434   - FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
  2572 + fst2 = float32_div(FLOAT_ONE32, fst0, &env->fpu->fp_status);
2435 2573 update_fcr31();
  2574 + return fst2;
2436 2575 }
2437   -FLOAT_OP(recip1, ps)
  2576 +
  2577 +uint64_t do_float_recip1_ps(uint64_t fdt0)
2438 2578 {
  2579 + uint32_t fst2;
  2580 + uint32_t fsth2;
  2581 +
2439 2582 set_float_exception_flags(0, &env->fpu->fp_status);
2440   - FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
2441   - FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
  2583 + fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->fpu->fp_status);
  2584 + fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->fpu->fp_status);
2442 2585 update_fcr31();
  2586 + return ((uint64_t)fsth2 << 32) | fst2;
2443 2587 }
2444 2588  
2445   -FLOAT_OP(rsqrt1, d)
  2589 +uint64_t do_float_rsqrt1_d(uint64_t fdt0)
2446 2590 {
  2591 + uint64_t fdt2;
  2592 +
2447 2593 set_float_exception_flags(0, &env->fpu->fp_status);
2448   - FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
2449   - FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
  2594 + fdt2 = float64_sqrt(fdt0, &env->fpu->fp_status);
  2595 + fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->fpu->fp_status);
2450 2596 update_fcr31();
  2597 + return fdt2;
2451 2598 }
2452   -FLOAT_OP(rsqrt1, s)
  2599 +
  2600 +uint32_t do_float_rsqrt1_s(uint32_t fst0)
2453 2601 {
  2602 + uint32_t fst2;
  2603 +
2454 2604 set_float_exception_flags(0, &env->fpu->fp_status);
2455   - FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
2456   - FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
  2605 + fst2 = float32_sqrt(fst0, &env->fpu->fp_status);
  2606 + fst2 = float32_div(FLOAT_ONE32, fst2, &env->fpu->fp_status);
2457 2607 update_fcr31();
  2608 + return fst2;
2458 2609 }
2459   -FLOAT_OP(rsqrt1, ps)
  2610 +
  2611 +uint64_t do_float_rsqrt1_ps(uint64_t fdt0)
2460 2612 {
  2613 + uint32_t fst2;
  2614 + uint32_t fsth2;
  2615 +
2461 2616 set_float_exception_flags(0, &env->fpu->fp_status);
2462   - FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
2463   - FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
2464   - FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
2465   - FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
  2617 + fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->fpu->fp_status);
  2618 + fsth2 = float32_sqrt(fdt0 >> 32, &env->fpu->fp_status);
  2619 + fst2 = float32_div(FLOAT_ONE32, fst2, &env->fpu->fp_status);
  2620 + fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->fpu->fp_status);
2466 2621 update_fcr31();
  2622 + return ((uint64_t)fsth2 << 32) | fst2;
2467 2623 }
2468 2624  
  2625 +#define FLOAT_OP(name, p) void do_float_##name##_##p(void)
  2626 +
2469 2627 /* binary operations */
2470   -#define FLOAT_BINOP(name) \
2471   -FLOAT_OP(name, d) \
2472   -{ \
  2628 +#define FLOAT_BINOP(name) \
  2629 +uint64_t do_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
  2630 +{ \
  2631 + uint64_t dt2; \
  2632 + \
2473 2633 set_float_exception_flags(0, &env->fpu->fp_status); \
2474   - FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
  2634 + dt2 = float64_ ## name (fdt0, fdt1, &env->fpu->fp_status); \
2475 2635 update_fcr31(); \
2476 2636 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
2477   - DT2 = FLOAT_QNAN64; \
2478   -} \
2479   -FLOAT_OP(name, s) \
2480   -{ \
  2637 + dt2 = FLOAT_QNAN64; \
  2638 + return dt2; \
  2639 +} \
  2640 + \
  2641 +uint32_t do_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
  2642 +{ \
  2643 + uint32_t wt2; \
  2644 + \
2481 2645 set_float_exception_flags(0, &env->fpu->fp_status); \
2482   - FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
  2646 + wt2 = float32_ ## name (fst0, fst1, &env->fpu->fp_status); \
2483 2647 update_fcr31(); \
2484 2648 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
2485   - WT2 = FLOAT_QNAN32; \
2486   -} \
2487   -FLOAT_OP(name, ps) \
2488   -{ \
  2649 + wt2 = FLOAT_QNAN32; \
  2650 + return wt2; \
  2651 +} \
  2652 + \
  2653 +uint64_t do_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
  2654 +{ \
  2655 + uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
  2656 + uint32_t fsth0 = fdt0 >> 32; \
  2657 + uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
  2658 + uint32_t fsth1 = fdt1 >> 32; \
  2659 + uint32_t wt2; \
  2660 + uint32_t wth2; \
  2661 + \
2489 2662 set_float_exception_flags(0, &env->fpu->fp_status); \
2490   - FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
2491   - FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
2492   - update_fcr31(); \
  2663 + wt2 = float32_ ## name (fst0, fst1, &env->fpu->fp_status); \
  2664 + wth2 = float32_ ## name (fsth0, fsth1, &env->fpu->fp_status); \
  2665 + update_fcr31(); \
2493 2666 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
2494   - WT2 = FLOAT_QNAN32; \
2495   - WTH2 = FLOAT_QNAN32; \
2496   - } \
  2667 + wt2 = FLOAT_QNAN32; \
  2668 + wth2 = FLOAT_QNAN32; \
  2669 + } \
  2670 + return ((uint64_t)wth2 << 32) | wt2; \
2497 2671 }
  2672 +
2498 2673 FLOAT_BINOP(add)
2499 2674 FLOAT_BINOP(sub)
2500 2675 FLOAT_BINOP(mul)
... ... @@ -2502,146 +2677,210 @@ FLOAT_BINOP(div)
2502 2677 #undef FLOAT_BINOP
2503 2678  
2504 2679 /* ternary operations */
2505   -#define FLOAT_TERNOP(name1, name2) \
2506   -FLOAT_OP(name1 ## name2, d) \
2507   -{ \
2508   - FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \
2509   - FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
2510   -} \
2511   -FLOAT_OP(name1 ## name2, s) \
2512   -{ \
2513   - FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2514   - FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2515   -} \
2516   -FLOAT_OP(name1 ## name2, ps) \
2517   -{ \
2518   - FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2519   - FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
2520   - FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2521   - FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
  2680 +#define FLOAT_TERNOP(name1, name2) \
  2681 +uint64_t do_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
  2682 + uint64_t fdt2) \
  2683 +{ \
  2684 + fdt0 = float64_ ## name1 (fdt0, fdt1, &env->fpu->fp_status); \
  2685 + return float64_ ## name2 (fdt0, fdt2, &env->fpu->fp_status); \
  2686 +} \
  2687 + \
  2688 +uint32_t do_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
  2689 + uint32_t fst2) \
  2690 +{ \
  2691 + fst0 = float32_ ## name1 (fst0, fst1, &env->fpu->fp_status); \
  2692 + return float32_ ## name2 (fst0, fst2, &env->fpu->fp_status); \
  2693 +} \
  2694 + \
  2695 +uint64_t do_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
  2696 + uint64_t fdt2) \
  2697 +{ \
  2698 + uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
  2699 + uint32_t fsth0 = fdt0 >> 32; \
  2700 + uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
  2701 + uint32_t fsth1 = fdt1 >> 32; \
  2702 + uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
  2703 + uint32_t fsth2 = fdt2 >> 32; \
  2704 + \
  2705 + fst0 = float32_ ## name1 (fst0, fst1, &env->fpu->fp_status); \
  2706 + fsth0 = float32_ ## name1 (fsth0, fsth1, &env->fpu->fp_status); \
  2707 + fst2 = float32_ ## name2 (fst0, fst2, &env->fpu->fp_status); \
  2708 + fsth2 = float32_ ## name2 (fsth0, fsth2, &env->fpu->fp_status); \
  2709 + return ((uint64_t)fsth2 << 32) | fst2; \
2522 2710 }
  2711 +
2523 2712 FLOAT_TERNOP(mul, add)
2524 2713 FLOAT_TERNOP(mul, sub)
2525 2714 #undef FLOAT_TERNOP
2526 2715  
2527 2716 /* negated ternary operations */
2528   -#define FLOAT_NTERNOP(name1, name2) \
2529   -FLOAT_OP(n ## name1 ## name2, d) \
2530   -{ \
2531   - FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \
2532   - FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
2533   - FDT2 = float64_chs(FDT2); \
2534   -} \
2535   -FLOAT_OP(n ## name1 ## name2, s) \
2536   -{ \
2537   - FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2538   - FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2539   - FST2 = float32_chs(FST2); \
2540   -} \
2541   -FLOAT_OP(n ## name1 ## name2, ps) \
2542   -{ \
2543   - FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2544   - FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
2545   - FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2546   - FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2547   - FST2 = float32_chs(FST2); \
2548   - FSTH2 = float32_chs(FSTH2); \
  2717 +#define FLOAT_NTERNOP(name1, name2) \
  2718 +uint64_t do_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
  2719 + uint64_t fdt2) \
  2720 +{ \
  2721 + fdt0 = float64_ ## name1 (fdt0, fdt1, &env->fpu->fp_status); \
  2722 + fdt2 = float64_ ## name2 (fdt0, fdt2, &env->fpu->fp_status); \
  2723 + return float64_chs(fdt2); \
  2724 +} \
  2725 + \
  2726 +uint32_t do_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
  2727 + uint32_t fst2) \
  2728 +{ \
  2729 + fst0 = float32_ ## name1 (fst0, fst1, &env->fpu->fp_status); \
  2730 + fst2 = float32_ ## name2 (fst0, fst2, &env->fpu->fp_status); \
  2731 + return float32_chs(fst2); \
  2732 +} \
  2733 + \
  2734 +uint64_t do_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
  2735 + uint64_t fdt2) \
  2736 +{ \
  2737 + uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
  2738 + uint32_t fsth0 = fdt0 >> 32; \
  2739 + uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
  2740 + uint32_t fsth1 = fdt1 >> 32; \
  2741 + uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
  2742 + uint32_t fsth2 = fdt2 >> 32; \
  2743 + \
  2744 + fst0 = float32_ ## name1 (fst0, fst1, &env->fpu->fp_status); \
  2745 + fsth0 = float32_ ## name1 (fsth0, fsth1, &env->fpu->fp_status); \
  2746 + fst2 = float32_ ## name2 (fst0, fst2, &env->fpu->fp_status); \
  2747 + fsth2 = float32_ ## name2 (fsth0, fsth2, &env->fpu->fp_status); \
  2748 + fst2 = float32_chs(fst2); \
  2749 + fsth2 = float32_chs(fsth2); \
  2750 + return ((uint64_t)fsth2 << 32) | fst2; \
2549 2751 }
  2752 +
2550 2753 FLOAT_NTERNOP(mul, add)
2551 2754 FLOAT_NTERNOP(mul, sub)
2552 2755 #undef FLOAT_NTERNOP
2553 2756  
2554 2757 /* MIPS specific binary operations */
2555   -FLOAT_OP(recip2, d)
  2758 +uint64_t do_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
2556 2759 {
2557 2760 set_float_exception_flags(0, &env->fpu->fp_status);
2558   - FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
2559   - FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status));
  2761 + fdt2 = float64_mul(fdt0, fdt2, &env->fpu->fp_status);
  2762 + fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->fpu->fp_status));
2560 2763 update_fcr31();
  2764 + return fdt2;
2561 2765 }
2562   -FLOAT_OP(recip2, s)
  2766 +
  2767 +uint32_t do_float_recip2_s(uint32_t fst0, uint32_t fst2)
2563 2768 {
2564 2769 set_float_exception_flags(0, &env->fpu->fp_status);
2565   - FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
2566   - FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
  2770 + fst2 = float32_mul(fst0, fst2, &env->fpu->fp_status);
  2771 + fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->fpu->fp_status));
2567 2772 update_fcr31();
  2773 + return fst2;
2568 2774 }
2569   -FLOAT_OP(recip2, ps)
  2775 +
  2776 +uint64_t do_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
2570 2777 {
  2778 + uint32_t fst0 = fdt0 & 0XFFFFFFFF;
  2779 + uint32_t fsth0 = fdt0 >> 32;
  2780 + uint32_t fst2 = fdt2 & 0XFFFFFFFF;
  2781 + uint32_t fsth2 = fdt2 >> 32;
  2782 +
2571 2783 set_float_exception_flags(0, &env->fpu->fp_status);
2572   - FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
2573   - FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
2574   - FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
2575   - FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status));
  2784 + fst2 = float32_mul(fst0, fst2, &env->fpu->fp_status);
  2785 + fsth2 = float32_mul(fsth0, fsth2, &env->fpu->fp_status);
  2786 + fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->fpu->fp_status));
  2787 + fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->fpu->fp_status));
2576 2788 update_fcr31();
  2789 + return ((uint64_t)fsth2 << 32) | fst2;
2577 2790 }
2578 2791  
2579   -FLOAT_OP(rsqrt2, d)
  2792 +uint64_t do_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
2580 2793 {
2581 2794 set_float_exception_flags(0, &env->fpu->fp_status);
2582   - FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
2583   - FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
2584   - FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status));
  2795 + fdt2 = float64_mul(fdt0, fdt2, &env->fpu->fp_status);
  2796 + fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->fpu->fp_status);
  2797 + fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->fpu->fp_status));
2585 2798 update_fcr31();
  2799 + return fdt2;
2586 2800 }
2587   -FLOAT_OP(rsqrt2, s)
  2801 +
  2802 +uint32_t do_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
2588 2803 {
2589 2804 set_float_exception_flags(0, &env->fpu->fp_status);
2590   - FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
2591   - FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
2592   - FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
  2805 + fst2 = float32_mul(fst0, fst2, &env->fpu->fp_status);
  2806 + fst2 = float32_sub(fst2, FLOAT_ONE32, &env->fpu->fp_status);
  2807 + fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->fpu->fp_status));
2593 2808 update_fcr31();
  2809 + return fst2;
2594 2810 }
2595   -FLOAT_OP(rsqrt2, ps)
  2811 +
  2812 +uint64_t do_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
2596 2813 {
  2814 + uint32_t fst0 = fdt0 & 0XFFFFFFFF;
  2815 + uint32_t fsth0 = fdt0 >> 32;
  2816 + uint32_t fst2 = fdt2 & 0XFFFFFFFF;
  2817 + uint32_t fsth2 = fdt2 >> 32;
  2818 +
2597 2819 set_float_exception_flags(0, &env->fpu->fp_status);
2598   - FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
2599   - FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
2600   - FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
2601   - FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
2602   - FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
2603   - FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status));
  2820 + fst2 = float32_mul(fst0, fst2, &env->fpu->fp_status);
  2821 + fsth2 = float32_mul(fsth0, fsth2, &env->fpu->fp_status);
  2822 + fst2 = float32_sub(fst2, FLOAT_ONE32, &env->fpu->fp_status);
  2823 + fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->fpu->fp_status);
  2824 + fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->fpu->fp_status));
  2825 + fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->fpu->fp_status));
2604 2826 update_fcr31();
  2827 + return ((uint64_t)fsth2 << 32) | fst2;
2605 2828 }
2606 2829  
2607   -FLOAT_OP(addr, ps)
  2830 +uint64_t do_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
2608 2831 {
  2832 + uint32_t fst0 = fdt0 & 0XFFFFFFFF;
  2833 + uint32_t fsth0 = fdt0 >> 32;
  2834 + uint32_t fst1 = fdt1 & 0XFFFFFFFF;
  2835 + uint32_t fsth1 = fdt1 >> 32;
  2836 + uint32_t fst2;
  2837 + uint32_t fsth2;
  2838 +
2609 2839 set_float_exception_flags(0, &env->fpu->fp_status);
2610   - FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
2611   - FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
  2840 + fst2 = float32_add (fst0, fsth0, &env->fpu->fp_status);
  2841 + fsth2 = float32_add (fst1, fsth1, &env->fpu->fp_status);
2612 2842 update_fcr31();
  2843 + return ((uint64_t)fsth2 << 32) | fst2;
2613 2844 }
2614 2845  
2615   -FLOAT_OP(mulr, ps)
  2846 +uint64_t do_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
2616 2847 {
  2848 + uint32_t fst0 = fdt0 & 0XFFFFFFFF;
  2849 + uint32_t fsth0 = fdt0 >> 32;
  2850 + uint32_t fst1 = fdt1 & 0XFFFFFFFF;
  2851 + uint32_t fsth1 = fdt1 >> 32;
  2852 + uint32_t fst2;
  2853 + uint32_t fsth2;
  2854 +
2617 2855 set_float_exception_flags(0, &env->fpu->fp_status);
2618   - FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
2619   - FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
  2856 + fst2 = float32_mul (fst0, fsth0, &env->fpu->fp_status);
  2857 + fsth2 = float32_mul (fst1, fsth1, &env->fpu->fp_status);
2620 2858 update_fcr31();
  2859 + return ((uint64_t)fsth2 << 32) | fst2;
2621 2860 }
2622 2861  
2623 2862 /* compare operations */
2624   -#define FOP_COND_D(op, cond) \
2625   -void do_cmp_d_ ## op (long cc) \
2626   -{ \
2627   - int c = cond; \
2628   - update_fcr31(); \
2629   - if (c) \
2630   - SET_FP_COND(cc, env->fpu); \
2631   - else \
2632   - CLEAR_FP_COND(cc, env->fpu); \
2633   -} \
2634   -void do_cmpabs_d_ ## op (long cc) \
2635   -{ \
2636   - int c; \
2637   - FDT0 = float64_abs(FDT0); \
2638   - FDT1 = float64_abs(FDT1); \
2639   - c = cond; \
2640   - update_fcr31(); \
2641   - if (c) \
2642   - SET_FP_COND(cc, env->fpu); \
2643   - else \
2644   - CLEAR_FP_COND(cc, env->fpu); \
  2863 +#define FOP_COND_D(op, cond) \
  2864 +void do_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
  2865 +{ \
  2866 + int c = cond; \
  2867 + update_fcr31(); \
  2868 + if (c) \
  2869 + SET_FP_COND(cc, env->fpu); \
  2870 + else \
  2871 + CLEAR_FP_COND(cc, env->fpu); \
  2872 +} \
  2873 +void do_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
  2874 +{ \
  2875 + int c; \
  2876 + fdt0 = float64_abs(fdt0); \
  2877 + fdt1 = float64_abs(fdt1); \
  2878 + c = cond; \
  2879 + update_fcr31(); \
  2880 + if (c) \
  2881 + SET_FP_COND(cc, env->fpu); \
  2882 + else \
  2883 + CLEAR_FP_COND(cc, env->fpu); \
2645 2884 }
2646 2885  
2647 2886 int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
... ... @@ -2660,46 +2899,46 @@ int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
2660 2899  
2661 2900 /* NOTE: the comma operator will make "cond" to eval to false,
2662 2901 * but float*_is_unordered() is still called. */
2663   -FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
2664   -FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
2665   -FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2666   -FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2667   -FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2668   -FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2669   -FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
2670   -FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
  2902 +FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status), 0))
  2903 +FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status))
  2904 +FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) && float64_eq(fdt0, fdt1, &env->fpu->fp_status))
  2905 +FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) || float64_eq(fdt0, fdt1, &env->fpu->fp_status))
  2906 +FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) && float64_lt(fdt0, fdt1, &env->fpu->fp_status))
  2907 +FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) || float64_lt(fdt0, fdt1, &env->fpu->fp_status))
  2908 +FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) && float64_le(fdt0, fdt1, &env->fpu->fp_status))
  2909 +FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) || float64_le(fdt0, fdt1, &env->fpu->fp_status))
2671 2910 /* NOTE: the comma operator will make "cond" to eval to false,
2672 2911 * but float*_is_unordered() is still called. */
2673   -FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
2674   -FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
2675   -FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2676   -FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2677   -FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2678   -FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2679   -FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
2680   -FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
2681   -
2682   -#define FOP_COND_S(op, cond) \
2683   -void do_cmp_s_ ## op (long cc) \
2684   -{ \
2685   - int c = cond; \
2686   - update_fcr31(); \
2687   - if (c) \
2688   - SET_FP_COND(cc, env->fpu); \
2689   - else \
2690   - CLEAR_FP_COND(cc, env->fpu); \
2691   -} \
2692   -void do_cmpabs_s_ ## op (long cc) \
2693   -{ \
2694   - int c; \
2695   - FST0 = float32_abs(FST0); \
2696   - FST1 = float32_abs(FST1); \
2697   - c = cond; \
2698   - update_fcr31(); \
2699   - if (c) \
2700   - SET_FP_COND(cc, env->fpu); \
2701   - else \
2702   - CLEAR_FP_COND(cc, env->fpu); \
  2912 +FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status), 0))
  2913 +FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status))
  2914 +FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) && float64_eq(fdt0, fdt1, &env->fpu->fp_status))
  2915 +FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) || float64_eq(fdt0, fdt1, &env->fpu->fp_status))
  2916 +FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) && float64_lt(fdt0, fdt1, &env->fpu->fp_status))
  2917 +FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) || float64_lt(fdt0, fdt1, &env->fpu->fp_status))
  2918 +FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) && float64_le(fdt0, fdt1, &env->fpu->fp_status))
  2919 +FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) || float64_le(fdt0, fdt1, &env->fpu->fp_status))
  2920 +
  2921 +#define FOP_COND_S(op, cond) \
  2922 +void do_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
  2923 +{ \
  2924 + int c = cond; \
  2925 + update_fcr31(); \
  2926 + if (c) \
  2927 + SET_FP_COND(cc, env->fpu); \
  2928 + else \
  2929 + CLEAR_FP_COND(cc, env->fpu); \
  2930 +} \
  2931 +void do_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
  2932 +{ \
  2933 + int c; \
  2934 + fst0 = float32_abs(fst0); \
  2935 + fst1 = float32_abs(fst1); \
  2936 + c = cond; \
  2937 + update_fcr31(); \
  2938 + if (c) \
  2939 + SET_FP_COND(cc, env->fpu); \
  2940 + else \
  2941 + CLEAR_FP_COND(cc, env->fpu); \
2703 2942 }
2704 2943  
2705 2944 flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
... ... @@ -2718,93 +2957,98 @@ flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
2718 2957  
2719 2958 /* NOTE: the comma operator will make "cond" to eval to false,
2720 2959 * but float*_is_unordered() is still called. */
2721   -FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
2722   -FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
2723   -FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
2724   -FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
2725   -FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
2726   -FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
2727   -FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
2728   -FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
  2960 +FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status), 0))
  2961 +FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status))
  2962 +FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_eq(fst0, fst1, &env->fpu->fp_status))
  2963 +FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) || float32_eq(fst0, fst1, &env->fpu->fp_status))
  2964 +FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_lt(fst0, fst1, &env->fpu->fp_status))
  2965 +FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) || float32_lt(fst0, fst1, &env->fpu->fp_status))
  2966 +FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_le(fst0, fst1, &env->fpu->fp_status))
  2967 +FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) || float32_le(fst0, fst1, &env->fpu->fp_status))
2729 2968 /* NOTE: the comma operator will make "cond" to eval to false,
2730 2969 * but float*_is_unordered() is still called. */
2731   -FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
2732   -FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
2733   -FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
2734   -FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
2735   -FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
2736   -FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
2737   -FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
2738   -FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
2739   -
2740   -#define FOP_COND_PS(op, condl, condh) \
2741   -void do_cmp_ps_ ## op (long cc) \
2742   -{ \
2743   - int cl = condl; \
2744   - int ch = condh; \
2745   - update_fcr31(); \
2746   - if (cl) \
2747   - SET_FP_COND(cc, env->fpu); \
2748   - else \
2749   - CLEAR_FP_COND(cc, env->fpu); \
2750   - if (ch) \
2751   - SET_FP_COND(cc + 1, env->fpu); \
2752   - else \
2753   - CLEAR_FP_COND(cc + 1, env->fpu); \
2754   -} \
2755   -void do_cmpabs_ps_ ## op (long cc) \
2756   -{ \
2757   - int cl, ch; \
2758   - FST0 = float32_abs(FST0); \
2759   - FSTH0 = float32_abs(FSTH0); \
2760   - FST1 = float32_abs(FST1); \
2761   - FSTH1 = float32_abs(FSTH1); \
2762   - cl = condl; \
2763   - ch = condh; \
2764   - update_fcr31(); \
2765   - if (cl) \
2766   - SET_FP_COND(cc, env->fpu); \
2767   - else \
2768   - CLEAR_FP_COND(cc, env->fpu); \
2769   - if (ch) \
2770   - SET_FP_COND(cc + 1, env->fpu); \
2771   - else \
2772   - CLEAR_FP_COND(cc + 1, env->fpu); \
  2970 +FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status), 0))
  2971 +FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status))
  2972 +FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_eq(fst0, fst1, &env->fpu->fp_status))
  2973 +FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) || float32_eq(fst0, fst1, &env->fpu->fp_status))
  2974 +FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_lt(fst0, fst1, &env->fpu->fp_status))
  2975 +FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) || float32_lt(fst0, fst1, &env->fpu->fp_status))
  2976 +FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_le(fst0, fst1, &env->fpu->fp_status))
  2977 +FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) || float32_le(fst0, fst1, &env->fpu->fp_status))
  2978 +
  2979 +#define FOP_COND_PS(op, condl, condh) \
  2980 +void do_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
  2981 +{ \
  2982 + uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
  2983 + uint32_t fsth0 = float32_abs(fdt0 >> 32); \
  2984 + uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
  2985 + uint32_t fsth1 = float32_abs(fdt1 >> 32); \
  2986 + int cl = condl; \
  2987 + int ch = condh; \
  2988 + \
  2989 + update_fcr31(); \
  2990 + if (cl) \
  2991 + SET_FP_COND(cc, env->fpu); \
  2992 + else \
  2993 + CLEAR_FP_COND(cc, env->fpu); \
  2994 + if (ch) \
  2995 + SET_FP_COND(cc + 1, env->fpu); \
  2996 + else \
  2997 + CLEAR_FP_COND(cc + 1, env->fpu); \
  2998 +} \
  2999 +void do_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
  3000 +{ \
  3001 + uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
  3002 + uint32_t fsth0 = float32_abs(fdt0 >> 32); \
  3003 + uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
  3004 + uint32_t fsth1 = float32_abs(fdt1 >> 32); \
  3005 + int cl = condl; \
  3006 + int ch = condh; \
  3007 + \
  3008 + update_fcr31(); \
  3009 + if (cl) \
  3010 + SET_FP_COND(cc, env->fpu); \
  3011 + else \
  3012 + CLEAR_FP_COND(cc, env->fpu); \
  3013 + if (ch) \
  3014 + SET_FP_COND(cc + 1, env->fpu); \
  3015 + else \
  3016 + CLEAR_FP_COND(cc + 1, env->fpu); \
2773 3017 }
2774 3018  
2775 3019 /* NOTE: the comma operator will make "cond" to eval to false,
2776 3020 * but float*_is_unordered() is still called. */
2777   -FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
2778   - (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
2779   -FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
2780   - float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
2781   -FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
2782   - !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2783   -FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
2784   - float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2785   -FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
2786   - !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2787   -FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
2788   - float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2789   -FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
2790   - !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
2791   -FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
2792   - float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
  3021 +FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status), 0),
  3022 + (float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status), 0))
  3023 +FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status),
  3024 + float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status))
  3025 +FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_eq(fst0, fst1, &env->fpu->fp_status),
  3026 + !float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) && float32_eq(fsth0, fsth1, &env->fpu->fp_status))
  3027 +FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) || float32_eq(fst0, fst1, &env->fpu->fp_status),
  3028 + float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) || float32_eq(fsth0, fsth1, &env->fpu->fp_status))
  3029 +FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_lt(fst0, fst1, &env->fpu->fp_status),
  3030 + !float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) && float32_lt(fsth0, fsth1, &env->fpu->fp_status))
  3031 +FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) || float32_lt(fst0, fst1, &env->fpu->fp_status),
  3032 + float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) || float32_lt(fsth0, fsth1, &env->fpu->fp_status))
  3033 +FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_le(fst0, fst1, &env->fpu->fp_status),
  3034 + !float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) && float32_le(fsth0, fsth1, &env->fpu->fp_status))
  3035 +FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) || float32_le(fst0, fst1, &env->fpu->fp_status),
  3036 + float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) || float32_le(fsth0, fsth1, &env->fpu->fp_status))
2793 3037 /* NOTE: the comma operator will make "cond" to eval to false,
2794 3038 * but float*_is_unordered() is still called. */
2795   -FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
2796   - (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
2797   -FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
2798   - float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
2799   -FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
2800   - !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2801   -FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
2802   - float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2803   -FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
2804   - !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2805   -FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
2806   - float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2807   -FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
2808   - !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
2809   -FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
2810   - float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
  3039 +FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status), 0),
  3040 + (float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status), 0))
  3041 +FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status),
  3042 + float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status))
  3043 +FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_eq(fst0, fst1, &env->fpu->fp_status),
  3044 + !float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) && float32_eq(fsth0, fsth1, &env->fpu->fp_status))
  3045 +FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) || float32_eq(fst0, fst1, &env->fpu->fp_status),
  3046 + float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) || float32_eq(fsth0, fsth1, &env->fpu->fp_status))
  3047 +FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_lt(fst0, fst1, &env->fpu->fp_status),
  3048 + !float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) && float32_lt(fsth0, fsth1, &env->fpu->fp_status))
  3049 +FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) || float32_lt(fst0, fst1, &env->fpu->fp_status),
  3050 + float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) || float32_lt(fsth0, fsth1, &env->fpu->fp_status))
  3051 +FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_le(fst0, fst1, &env->fpu->fp_status),
  3052 + !float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) && float32_le(fsth0, fsth1, &env->fpu->fp_status))
  3053 +FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) || float32_le(fst0, fst1, &env->fpu->fp_status),
  3054 + float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) || float32_le(fsth0, fsth1, &env->fpu->fp_status))
... ...
target-mips/translate.c
  View file @b6d96be
... ... @@ -425,9 +425,6 @@ enum {
425 425 /* global register indices */
426 426 static TCGv cpu_env, bcond, btarget, current_fpu;
427 427  
428   -/* FPU TNs, global for now. */
429   -static TCGv fpu32_T[3], fpu64_T[3], fpu32h_T[3];
430   -
431 428 #include "gen-icount.h"
432 429  
433 430 static inline void tcg_gen_helper_0_i(void *func, TCGv arg)
... ... @@ -723,36 +720,39 @@ static inline void get_fp_cond (TCGv t)
723 720 tcg_temp_free(r_tmp2);
724 721 }
725 722  
726   -#define FOP_CONDS(type, fmt) \
727   -static GenOpFunc1 * fcmp ## type ## _ ## fmt ## _table[16] = { \
728   - do_cmp ## type ## _ ## fmt ## _f, \
729   - do_cmp ## type ## _ ## fmt ## _un, \
730   - do_cmp ## type ## _ ## fmt ## _eq, \
731   - do_cmp ## type ## _ ## fmt ## _ueq, \
732   - do_cmp ## type ## _ ## fmt ## _olt, \
733   - do_cmp ## type ## _ ## fmt ## _ult, \
734   - do_cmp ## type ## _ ## fmt ## _ole, \
735   - do_cmp ## type ## _ ## fmt ## _ule, \
736   - do_cmp ## type ## _ ## fmt ## _sf, \
737   - do_cmp ## type ## _ ## fmt ## _ngle, \
738   - do_cmp ## type ## _ ## fmt ## _seq, \
739   - do_cmp ## type ## _ ## fmt ## _ngl, \
740   - do_cmp ## type ## _ ## fmt ## _lt, \
741   - do_cmp ## type ## _ ## fmt ## _nge, \
742   - do_cmp ## type ## _ ## fmt ## _le, \
743   - do_cmp ## type ## _ ## fmt ## _ngt, \
744   -}; \
745   -static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
746   -{ \
747   - tcg_gen_helper_0_i(fcmp ## type ## _ ## fmt ## _table[n], cc); \
  723 +typedef void (fcmp_fun32)(uint32_t, uint32_t, int);
  724 +typedef void (fcmp_fun64)(uint64_t, uint64_t, int);
  725 +
  726 +#define FOP_CONDS(fcmp_fun, type, arg0, arg1, fmt) \
  727 +static fcmp_fun * fcmp ## type ## _ ## fmt ## _table[16] = { \
  728 + do_cmp ## type ## _ ## fmt ## _f, \
  729 + do_cmp ## type ## _ ## fmt ## _un, \
  730 + do_cmp ## type ## _ ## fmt ## _eq, \
  731 + do_cmp ## type ## _ ## fmt ## _ueq, \
  732 + do_cmp ## type ## _ ## fmt ## _olt, \
  733 + do_cmp ## type ## _ ## fmt ## _ult, \
  734 + do_cmp ## type ## _ ## fmt ## _ole, \
  735 + do_cmp ## type ## _ ## fmt ## _ule, \
  736 + do_cmp ## type ## _ ## fmt ## _sf, \
  737 + do_cmp ## type ## _ ## fmt ## _ngle, \
  738 + do_cmp ## type ## _ ## fmt ## _seq, \
  739 + do_cmp ## type ## _ ## fmt ## _ngl, \
  740 + do_cmp ## type ## _ ## fmt ## _lt, \
  741 + do_cmp ## type ## _ ## fmt ## _nge, \
  742 + do_cmp ## type ## _ ## fmt ## _le, \
  743 + do_cmp ## type ## _ ## fmt ## _ngt, \
  744 +}; \
  745 +static inline void gen_cmp ## type ## _ ## fmt(int n, arg0 a, arg1 b, int cc) \
  746 +{ \
  747 + tcg_gen_helper_0_2i(fcmp ## type ## _ ## fmt ## _table[n], a, b, cc); \
748 748 }
749 749  
750   -FOP_CONDS(, d)
751   -FOP_CONDS(abs, d)
752   -FOP_CONDS(, s)
753   -FOP_CONDS(abs, s)
754   -FOP_CONDS(, ps)
755   -FOP_CONDS(abs, ps)
  750 +FOP_CONDS(fcmp_fun64, , uint64_t, uint64_t, d)
  751 +FOP_CONDS(fcmp_fun64, abs, uint64_t, uint64_t, d)
  752 +FOP_CONDS(fcmp_fun32, , uint32_t, uint32_t, s)
  753 +FOP_CONDS(fcmp_fun32, abs, uint32_t, uint32_t, s)
  754 +FOP_CONDS(fcmp_fun64, , uint64_t, uint64_t, ps)
  755 +FOP_CONDS(fcmp_fun64, abs, uint64_t, uint64_t, ps)
756 756 #undef FOP_CONDS
757 757  
758 758 /* Tests */
... ... @@ -1234,23 +1234,43 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
1234 1234 memory access. */
1235 1235 switch (opc) {
1236 1236 case OPC_LWC1:
1237   - tcg_gen_qemu_ld32s(fpu32_T[0], t0, ctx->mem_idx);
1238   - gen_store_fpr32(fpu32_T[0], ft);
  1237 + {
  1238 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  1239 +
  1240 + tcg_gen_qemu_ld32s(fp0, t0, ctx->mem_idx);
  1241 + gen_store_fpr32(fp0, ft);
  1242 + tcg_temp_free(fp0);
  1243 + }
1239 1244 opn = "lwc1";
1240 1245 break;
1241 1246 case OPC_SWC1:
1242   - gen_load_fpr32(fpu32_T[0], ft);
1243   - tcg_gen_qemu_st32(fpu32_T[0], t0, ctx->mem_idx);
  1247 + {
  1248 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  1249 +
  1250 + gen_load_fpr32(fp0, ft);
  1251 + tcg_gen_qemu_st32(fp0, t0, ctx->mem_idx);
  1252 + tcg_temp_free(fp0);
  1253 + }
1244 1254 opn = "swc1";
1245 1255 break;
1246 1256 case OPC_LDC1:
1247   - tcg_gen_qemu_ld64(fpu64_T[0], t0, ctx->mem_idx);
1248   - gen_store_fpr64(ctx, fpu64_T[0], ft);
  1257 + {
  1258 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  1259 +
  1260 + tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
  1261 + gen_store_fpr64(ctx, fp0, ft);
  1262 + tcg_temp_free(fp0);
  1263 + }
1249 1264 opn = "ldc1";
1250 1265 break;
1251 1266 case OPC_SDC1:
1252   - gen_load_fpr64(ctx, fpu64_T[0], ft);
1253   - tcg_gen_qemu_st64(fpu64_T[0], t0, ctx->mem_idx);
  1267 + {
  1268 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  1269 +
  1270 + gen_load_fpr64(ctx, fp0, ft);
  1271 + tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
  1272 + tcg_temp_free(fp0);
  1273 + }
1254 1274 opn = "sdc1";
1255 1275 break;
1256 1276 default:
... ... @@ -5318,11 +5338,17 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
5318 5338 case 2:
5319 5339 /* XXX: For now we support only a single FPU context. */
5320 5340 if (h == 0) {
5321   - gen_load_fpr32(fpu32_T[0], rt);
5322   - tcg_gen_ext_i32_tl(t0, fpu32_T[0]);
  5341 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  5342 +
  5343 + gen_load_fpr32(fp0, rt);
  5344 + tcg_gen_ext_i32_tl(t0, fp0);
  5345 + tcg_temp_free(fp0);
5323 5346 } else {
5324   - gen_load_fpr32h(fpu32h_T[0], rt);
5325   - tcg_gen_ext_i32_tl(t0, fpu32h_T[0]);
  5347 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  5348 +
  5349 + gen_load_fpr32h(fp0, rt);
  5350 + tcg_gen_ext_i32_tl(t0, fp0);
  5351 + tcg_temp_free(fp0);
5326 5352 }
5327 5353 break;
5328 5354 case 3:
... ... @@ -5487,11 +5513,17 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5487 5513 case 2:
5488 5514 /* XXX: For now we support only a single FPU context. */
5489 5515 if (h == 0) {
5490   - tcg_gen_trunc_tl_i32(fpu32_T[0], t0);
5491   - gen_store_fpr32(fpu32_T[0], rd);
  5516 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  5517 +
  5518 + tcg_gen_trunc_tl_i32(fp0, t0);
  5519 + gen_store_fpr32(fp0, rd);
  5520 + tcg_temp_free(fp0);
5492 5521 } else {
5493   - tcg_gen_trunc_tl_i32(fpu32h_T[0], t0);
5494   - gen_store_fpr32h(fpu32h_T[0], rd);
  5522 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  5523 +
  5524 + tcg_gen_trunc_tl_i32(fp0, t0);
  5525 + gen_store_fpr32h(fp0, rd);
  5526 + tcg_temp_free(fp0);
5495 5527 }
5496 5528 break;
5497 5529 case 3:
... ... @@ -5873,15 +5905,25 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5873 5905  
5874 5906 switch (opc) {
5875 5907 case OPC_MFC1:
5876   - gen_load_fpr32(fpu32_T[0], fs);
5877   - tcg_gen_ext_i32_tl(t0, fpu32_T[0]);
  5908 + {
  5909 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  5910 +
  5911 + gen_load_fpr32(fp0, fs);
  5912 + tcg_gen_ext_i32_tl(t0, fp0);
  5913 + tcg_temp_free(fp0);
  5914 + }
5878 5915 gen_store_gpr(t0, rt);
5879 5916 opn = "mfc1";
5880 5917 break;
5881 5918 case OPC_MTC1:
5882 5919 gen_load_gpr(t0, rt);
5883   - tcg_gen_trunc_tl_i32(fpu32_T[0], t0);
5884   - gen_store_fpr32(fpu32_T[0], fs);
  5920 + {
  5921 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  5922 +
  5923 + tcg_gen_trunc_tl_i32(fp0, t0);
  5924 + gen_store_fpr32(fp0, fs);
  5925 + tcg_temp_free(fp0);
  5926 + }
5885 5927 opn = "mtc1";
5886 5928 break;
5887 5929 case OPC_CFC1:
... ... @@ -5895,27 +5937,47 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5895 5937 opn = "ctc1";
5896 5938 break;
5897 5939 case OPC_DMFC1:
5898   - gen_load_fpr64(ctx, fpu64_T[0], fs);
5899   - tcg_gen_mov_tl(t0, fpu64_T[0]);
  5940 + {
  5941 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  5942 +
  5943 + gen_load_fpr64(ctx, fp0, fs);
  5944 + tcg_gen_mov_tl(t0, fp0);
  5945 + tcg_temp_free(fp0);
  5946 + }
5900 5947 gen_store_gpr(t0, rt);
5901 5948 opn = "dmfc1";
5902 5949 break;
5903 5950 case OPC_DMTC1:
5904 5951 gen_load_gpr(t0, rt);
5905   - tcg_gen_mov_tl(fpu64_T[0], t0);
5906   - gen_store_fpr64(ctx, fpu64_T[0], fs);
  5952 + {
  5953 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  5954 +
  5955 + tcg_gen_mov_tl(fp0, t0);
  5956 + gen_store_fpr64(ctx, fp0, fs);
  5957 + tcg_temp_free(fp0);
  5958 + }
5907 5959 opn = "dmtc1";
5908 5960 break;
5909 5961 case OPC_MFHC1:
5910   - gen_load_fpr32h(fpu32h_T[0], fs);
5911   - tcg_gen_ext_i32_tl(t0, fpu32h_T[0]);
  5962 + {
  5963 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  5964 +
  5965 + gen_load_fpr32h(fp0, fs);
  5966 + tcg_gen_ext_i32_tl(t0, fp0);
  5967 + tcg_temp_free(fp0);
  5968 + }
5912 5969 gen_store_gpr(t0, rt);
5913 5970 opn = "mfhc1";
5914 5971 break;
5915 5972 case OPC_MTHC1:
5916 5973 gen_load_gpr(t0, rt);
5917   - tcg_gen_trunc_tl_i32(fpu32h_T[0], t0);
5918   - gen_store_fpr32h(fpu32h_T[0], fs);
  5974 + {
  5975 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  5976 +
  5977 + tcg_gen_trunc_tl_i32(fp0, t0);
  5978 + gen_store_fpr32h(fp0, fs);
  5979 + tcg_temp_free(fp0);
  5980 + }
5919 5981 opn = "mthc1";
5920 5982 break;
5921 5983 default:
... ... @@ -5967,11 +6029,13 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
5967 6029 tcg_temp_free(t0);
5968 6030 }
5969 6031  
5970   -static inline void gen_movcf_s (int cc, int tf)
  6032 +static inline void gen_movcf_s (int fs, int fd, int cc, int tf)
5971 6033 {
5972 6034 uint32_t ccbit;
5973 6035 int cond;
5974   - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
  6036 + TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_I32);
  6037 + TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
  6038 + TCGv fp1 = tcg_temp_local_new(TCG_TYPE_I32);
5975 6039 int l1 = gen_new_label();
5976 6040  
5977 6041 if (cc)
... ... @@ -5984,19 +6048,26 @@ static inline void gen_movcf_s (int cc, int tf)
5984 6048 else
5985 6049 cond = TCG_COND_NE;
5986 6050  
  6051 + gen_load_fpr32(fp0, fs);
  6052 + gen_load_fpr32(fp1, fd);
5987 6053 tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));
5988 6054 tcg_gen_andi_i32(r_tmp1, r_tmp1, ccbit);
5989 6055 tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1);
5990   - tcg_gen_movi_i32(fpu32_T[2], fpu32_T[0]);
  6056 + tcg_gen_movi_i32(fp1, fp0);
  6057 + tcg_temp_free(fp0);
5991 6058 gen_set_label(l1);
5992 6059 tcg_temp_free(r_tmp1);
  6060 + gen_store_fpr32(fp1, fd);
  6061 + tcg_temp_free(fp1);
5993 6062 }
5994 6063  
5995   -static inline void gen_movcf_d (int cc, int tf)
  6064 +static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf)
5996 6065 {
5997 6066 uint32_t ccbit;
5998 6067 int cond;
5999   - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
  6068 + TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_I32);
  6069 + TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I64);
  6070 + TCGv fp1 = tcg_temp_local_new(TCG_TYPE_I64);
6000 6071 int l1 = gen_new_label();
6001 6072  
6002 6073 if (cc)
... ... @@ -6009,19 +6080,28 @@ static inline void gen_movcf_d (int cc, int tf)
6009 6080 else
6010 6081 cond = TCG_COND_NE;
6011 6082  
  6083 + gen_load_fpr64(ctx, fp0, fs);
  6084 + gen_load_fpr64(ctx, fp1, fd);
6012 6085 tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));
6013 6086 tcg_gen_andi_i32(r_tmp1, r_tmp1, ccbit);
6014 6087 tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1);
6015   - tcg_gen_movi_i64(fpu64_T[2], fpu64_T[0]);
  6088 + tcg_gen_movi_i64(fp1, fp0);
  6089 + tcg_temp_free(fp0);
6016 6090 gen_set_label(l1);
6017 6091 tcg_temp_free(r_tmp1);
  6092 + gen_store_fpr64(ctx, fp1, fd);
  6093 + tcg_temp_free(fp1);
6018 6094 }
6019 6095  
6020   -static inline void gen_movcf_ps (int cc, int tf)
  6096 +static inline void gen_movcf_ps (int fs, int fd, int cc, int tf)
6021 6097 {
6022 6098 int cond;
6023 6099 TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_I32);
6024 6100 TCGv r_tmp2 = tcg_temp_local_new(TCG_TYPE_I32);
  6101 + TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
  6102 + TCGv fph0 = tcg_temp_local_new(TCG_TYPE_I32);
  6103 + TCGv fp1 = tcg_temp_local_new(TCG_TYPE_I32);
  6104 + TCGv fph1 = tcg_temp_local_new(TCG_TYPE_I32);
6025 6105 int l1 = gen_new_label();
6026 6106 int l2 = gen_new_label();
6027 6107  
... ... @@ -6030,18 +6110,28 @@ static inline void gen_movcf_ps (int cc, int tf)
6030 6110 else
6031 6111 cond = TCG_COND_NE;
6032 6112  
  6113 + gen_load_fpr32(fp0, fs);
  6114 + gen_load_fpr32h(fph0, fs);
  6115 + gen_load_fpr32(fp1, fd);
  6116 + gen_load_fpr32h(fph1, fd);
6033 6117 get_fp_cond(r_tmp1);
6034 6118 tcg_gen_shri_i32(r_tmp1, r_tmp1, cc);
6035 6119 tcg_gen_andi_i32(r_tmp2, r_tmp1, 0x1);
6036 6120 tcg_gen_brcondi_i32(cond, r_tmp2, 0, l1);
6037   - tcg_gen_movi_i32(fpu32_T[2], fpu32_T[0]);
  6121 + tcg_gen_movi_i32(fp1, fp0);
  6122 + tcg_temp_free(fp0);
6038 6123 gen_set_label(l1);
6039 6124 tcg_gen_andi_i32(r_tmp2, r_tmp1, 0x2);
6040 6125 tcg_gen_brcondi_i32(cond, r_tmp2, 0, l2);
6041   - tcg_gen_movi_i32(fpu32h_T[2], fpu32h_T[0]);
  6126 + tcg_gen_movi_i32(fph1, fph0);
  6127 + tcg_temp_free(fph0);
6042 6128 gen_set_label(l2);
6043 6129 tcg_temp_free(r_tmp1);
6044 6130 tcg_temp_free(r_tmp2);
  6131 + gen_store_fpr32(fp1, fd);
  6132 + gen_store_fpr32h(fph1, fd);
  6133 + tcg_temp_free(fp1);
  6134 + tcg_temp_free(fph1);
6045 6135 }
6046 6136  
6047 6137  
... ... @@ -6090,224 +6180,381 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6090 6180  
6091 6181 switch (ctx->opcode & FOP(0x3f, 0x1f)) {
6092 6182 case FOP(0, 16):
6093   - gen_load_fpr32(fpu32_T[0], fs);
6094   - gen_load_fpr32(fpu32_T[1], ft);
6095   - tcg_gen_helper_0_0(do_float_add_s);
6096   - gen_store_fpr32(fpu32_T[2], fd);
  6183 + {
  6184 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6185 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  6186 +
  6187 + gen_load_fpr32(fp0, fs);
  6188 + gen_load_fpr32(fp1, ft);
  6189 + tcg_gen_helper_1_2(do_float_add_s, fp0, fp0, fp1);
  6190 + tcg_temp_free(fp1);
  6191 + gen_store_fpr32(fp0, fd);
  6192 + tcg_temp_free(fp0);
  6193 + }
6097 6194 opn = "add.s";
6098 6195 optype = BINOP;
6099 6196 break;
6100 6197 case FOP(1, 16):
6101   - gen_load_fpr32(fpu32_T[0], fs);
6102   - gen_load_fpr32(fpu32_T[1], ft);
6103   - tcg_gen_helper_0_0(do_float_sub_s);
6104   - gen_store_fpr32(fpu32_T[2], fd);
  6198 + {
  6199 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6200 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  6201 +
  6202 + gen_load_fpr32(fp0, fs);
  6203 + gen_load_fpr32(fp1, ft);
  6204 + tcg_gen_helper_1_2(do_float_sub_s, fp0, fp0, fp1);
  6205 + tcg_temp_free(fp1);
  6206 + gen_store_fpr32(fp0, fd);
  6207 + tcg_temp_free(fp0);
  6208 + }
6105 6209 opn = "sub.s";
6106 6210 optype = BINOP;
6107 6211 break;
6108 6212 case FOP(2, 16):
6109   - gen_load_fpr32(fpu32_T[0], fs);
6110   - gen_load_fpr32(fpu32_T[1], ft);
6111   - tcg_gen_helper_0_0(do_float_mul_s);
6112   - gen_store_fpr32(fpu32_T[2], fd);
  6213 + {
  6214 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6215 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  6216 +
  6217 + gen_load_fpr32(fp0, fs);
  6218 + gen_load_fpr32(fp1, ft);
  6219 + tcg_gen_helper_1_2(do_float_mul_s, fp0, fp0, fp1);
  6220 + tcg_temp_free(fp1);
  6221 + gen_store_fpr32(fp0, fd);
  6222 + tcg_temp_free(fp0);
  6223 + }
6113 6224 opn = "mul.s";
6114 6225 optype = BINOP;
6115 6226 break;
6116 6227 case FOP(3, 16):
6117   - gen_load_fpr32(fpu32_T[0], fs);
6118   - gen_load_fpr32(fpu32_T[1], ft);
6119   - tcg_gen_helper_0_0(do_float_div_s);
6120   - gen_store_fpr32(fpu32_T[2], fd);
  6228 + {
  6229 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6230 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  6231 +
  6232 + gen_load_fpr32(fp0, fs);
  6233 + gen_load_fpr32(fp1, ft);
  6234 + tcg_gen_helper_1_2(do_float_div_s, fp0, fp0, fp1);
  6235 + tcg_temp_free(fp1);
  6236 + gen_store_fpr32(fp0, fd);
  6237 + tcg_temp_free(fp0);
  6238 + }
6121 6239 opn = "div.s";
6122 6240 optype = BINOP;
6123 6241 break;
6124 6242 case FOP(4, 16):
6125   - gen_load_fpr32(fpu32_T[0], fs);
6126   - tcg_gen_helper_0_0(do_float_sqrt_s);
6127   - gen_store_fpr32(fpu32_T[2], fd);
  6243 + {
  6244 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6245 +
  6246 + gen_load_fpr32(fp0, fs);
  6247 + tcg_gen_helper_1_1(do_float_sqrt_s, fp0, fp0);
  6248 + gen_store_fpr32(fp0, fd);
  6249 + tcg_temp_free(fp0);
  6250 + }
6128 6251 opn = "sqrt.s";
6129 6252 break;
6130 6253 case FOP(5, 16):
6131   - gen_load_fpr32(fpu32_T[0], fs);
6132   - tcg_gen_helper_0_0(do_float_abs_s);
6133   - gen_store_fpr32(fpu32_T[2], fd);
  6254 + {
  6255 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6256 +
  6257 + gen_load_fpr32(fp0, fs);
  6258 + tcg_gen_helper_1_1(do_float_abs_s, fp0, fp0);
  6259 + gen_store_fpr32(fp0, fd);
  6260 + tcg_temp_free(fp0);
  6261 + }
6134 6262 opn = "abs.s";
6135 6263 break;
6136 6264 case FOP(6, 16):
6137   - gen_load_fpr32(fpu32_T[0], fs);
6138   - gen_store_fpr32(fpu32_T[0], fd);
  6265 + {
  6266 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6267 +
  6268 + gen_load_fpr32(fp0, fs);
  6269 + gen_store_fpr32(fp0, fd);
  6270 + tcg_temp_free(fp0);
  6271 + }
6139 6272 opn = "mov.s";
6140 6273 break;
6141 6274 case FOP(7, 16):
6142   - gen_load_fpr32(fpu32_T[0], fs);
6143   - tcg_gen_helper_0_0(do_float_chs_s);
6144   - gen_store_fpr32(fpu32_T[2], fd);
  6275 + {
  6276 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6277 +
  6278 + gen_load_fpr32(fp0, fs);
  6279 + tcg_gen_helper_1_1(do_float_chs_s, fp0, fp0);
  6280 + gen_store_fpr32(fp0, fd);
  6281 + tcg_temp_free(fp0);
  6282 + }
6145 6283 opn = "neg.s";
6146 6284 break;
6147 6285 case FOP(8, 16):
6148 6286 check_cp1_64bitmode(ctx);
6149   - gen_load_fpr32(fpu32_T[0], fs);
6150   - tcg_gen_helper_0_0(do_float_roundl_s);
6151   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6287 + {
  6288 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  6289 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  6290 +
  6291 + gen_load_fpr32(fp32, fs);
  6292 + tcg_gen_helper_1_1(do_float_roundl_s, fp64, fp32);
  6293 + tcg_temp_free(fp32);
  6294 + gen_store_fpr64(ctx, fp64, fd);
  6295 + tcg_temp_free(fp64);
  6296 + }
6152 6297 opn = "round.l.s";
6153 6298 break;
6154 6299 case FOP(9, 16):
6155 6300 check_cp1_64bitmode(ctx);
6156   - gen_load_fpr32(fpu32_T[0], fs);
6157   - tcg_gen_helper_0_0(do_float_truncl_s);
6158   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6301 + {
  6302 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  6303 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  6304 +
  6305 + gen_load_fpr32(fp32, fs);
  6306 + tcg_gen_helper_1_1(do_float_truncl_s, fp64, fp32);
  6307 + tcg_temp_free(fp32);
  6308 + gen_store_fpr64(ctx, fp64, fd);
  6309 + tcg_temp_free(fp64);
  6310 + }
6159 6311 opn = "trunc.l.s";
6160 6312 break;
6161 6313 case FOP(10, 16):
6162 6314 check_cp1_64bitmode(ctx);
6163   - gen_load_fpr32(fpu32_T[0], fs);
6164   - tcg_gen_helper_0_0(do_float_ceill_s);
6165   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6315 + {
  6316 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  6317 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  6318 +
  6319 + gen_load_fpr32(fp32, fs);
  6320 + tcg_gen_helper_1_1(do_float_ceill_s, fp64, fp32);
  6321 + tcg_temp_free(fp32);
  6322 + gen_store_fpr64(ctx, fp64, fd);
  6323 + tcg_temp_free(fp64);
  6324 + }
6166 6325 opn = "ceil.l.s";
6167 6326 break;
6168 6327 case FOP(11, 16):
6169 6328 check_cp1_64bitmode(ctx);
6170   - gen_load_fpr32(fpu32_T[0], fs);
6171   - tcg_gen_helper_0_0(do_float_floorl_s);
6172   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6329 + {
  6330 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  6331 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  6332 +
  6333 + gen_load_fpr32(fp32, fs);
  6334 + tcg_gen_helper_1_1(do_float_floorl_s, fp64, fp32);
  6335 + tcg_temp_free(fp32);
  6336 + gen_store_fpr64(ctx, fp64, fd);
  6337 + tcg_temp_free(fp64);
  6338 + }
6173 6339 opn = "floor.l.s";
6174 6340 break;
6175 6341 case FOP(12, 16):
6176   - gen_load_fpr32(fpu32_T[0], fs);
6177   - tcg_gen_helper_0_0(do_float_roundw_s);
6178   - gen_store_fpr32(fpu32_T[2], fd);
  6342 + {
  6343 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6344 +
  6345 + gen_load_fpr32(fp0, fs);
  6346 + tcg_gen_helper_1_1(do_float_roundw_s, fp0, fp0);
  6347 + gen_store_fpr32(fp0, fd);
  6348 + tcg_temp_free(fp0);
  6349 + }
6179 6350 opn = "round.w.s";
6180 6351 break;
6181 6352 case FOP(13, 16):
6182   - gen_load_fpr32(fpu32_T[0], fs);
6183   - tcg_gen_helper_0_0(do_float_truncw_s);
6184   - gen_store_fpr32(fpu32_T[2], fd);
  6353 + {
  6354 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6355 +
  6356 + gen_load_fpr32(fp0, fs);
  6357 + tcg_gen_helper_1_1(do_float_truncw_s, fp0, fp0);
  6358 + gen_store_fpr32(fp0, fd);
  6359 + tcg_temp_free(fp0);
  6360 + }
6185 6361 opn = "trunc.w.s";
6186 6362 break;
6187 6363 case FOP(14, 16):
6188   - gen_load_fpr32(fpu32_T[0], fs);
6189   - tcg_gen_helper_0_0(do_float_ceilw_s);
6190   - gen_store_fpr32(fpu32_T[2], fd);
  6364 + {
  6365 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6366 +
  6367 + gen_load_fpr32(fp0, fs);
  6368 + tcg_gen_helper_1_1(do_float_ceilw_s, fp0, fp0);
  6369 + gen_store_fpr32(fp0, fd);
  6370 + tcg_temp_free(fp0);
  6371 + }
6191 6372 opn = "ceil.w.s";
6192 6373 break;
6193 6374 case FOP(15, 16):
6194   - gen_load_fpr32(fpu32_T[0], fs);
6195   - tcg_gen_helper_0_0(do_float_floorw_s);
6196   - gen_store_fpr32(fpu32_T[2], fd);
  6375 + {
  6376 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6377 +
  6378 + gen_load_fpr32(fp0, fs);
  6379 + tcg_gen_helper_1_1(do_float_floorw_s, fp0, fp0);
  6380 + gen_store_fpr32(fp0, fd);
  6381 + tcg_temp_free(fp0);
  6382 + }
6197 6383 opn = "floor.w.s";
6198 6384 break;
6199 6385 case FOP(17, 16):
6200   - gen_load_fpr32(fpu32_T[0], fs);
6201   - gen_load_fpr32(fpu32_T[2], fd);
6202   - gen_movcf_s((ft >> 2) & 0x7, ft & 0x1);
6203   - gen_store_fpr32(fpu32_T[2], fd);
  6386 + gen_movcf_s(fs, fd, (ft >> 2) & 0x7, ft & 0x1);
6204 6387 opn = "movcf.s";
6205 6388 break;
6206 6389 case FOP(18, 16):
6207   - gen_load_fpr32(fpu32_T[0], fs);
6208   - gen_load_fpr32(fpu32_T[2], fd);
6209 6390 {
6210 6391 int l1 = gen_new_label();
6211 6392 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  6393 + TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
6212 6394  
6213 6395 gen_load_gpr(t0, ft);
6214 6396 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
6215 6397 tcg_temp_free(t0);
6216   - tcg_gen_mov_i32(fpu32_T[2], fpu32_T[0]);
  6398 + gen_load_fpr32(fp0, fs);
  6399 + gen_store_fpr32(fp0, fd);
  6400 + tcg_temp_free(fp0);
6217 6401 gen_set_label(l1);
6218 6402 }
6219   - gen_store_fpr32(fpu32_T[2], fd);
6220 6403 opn = "movz.s";
6221 6404 break;
6222 6405 case FOP(19, 16):
6223   - gen_load_fpr32(fpu32_T[0], fs);
6224   - gen_load_fpr32(fpu32_T[2], fd);
6225 6406 {
6226 6407 int l1 = gen_new_label();
6227 6408 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  6409 + TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
6228 6410  
6229 6411 gen_load_gpr(t0, ft);
6230 6412 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6231 6413 tcg_temp_free(t0);
6232   - tcg_gen_mov_i32(fpu32_T[2], fpu32_T[0]);
  6414 + gen_load_fpr32(fp0, fs);
  6415 + gen_store_fpr32(fp0, fd);
  6416 + tcg_temp_free(fp0);
6233 6417 gen_set_label(l1);
6234 6418 }
6235   - gen_store_fpr32(fpu32_T[2], fd);
6236 6419 opn = "movn.s";
6237 6420 break;
6238 6421 case FOP(21, 16):
6239 6422 check_cop1x(ctx);
6240   - gen_load_fpr32(fpu32_T[0], fs);
6241   - tcg_gen_helper_0_0(do_float_recip_s);
6242   - gen_store_fpr32(fpu32_T[2], fd);
  6423 + {
  6424 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6425 +
  6426 + gen_load_fpr32(fp0, fs);
  6427 + tcg_gen_helper_1_1(do_float_recip_s, fp0, fp0);
  6428 + gen_store_fpr32(fp0, fd);
  6429 + tcg_temp_free(fp0);
  6430 + }
6243 6431 opn = "recip.s";
6244 6432 break;
6245 6433 case FOP(22, 16):
6246 6434 check_cop1x(ctx);
6247   - gen_load_fpr32(fpu32_T[0], fs);
6248   - tcg_gen_helper_0_0(do_float_rsqrt_s);
6249   - gen_store_fpr32(fpu32_T[2], fd);
  6435 + {
  6436 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6437 +
  6438 + gen_load_fpr32(fp0, fs);
  6439 + tcg_gen_helper_1_1(do_float_rsqrt_s, fp0, fp0);
  6440 + gen_store_fpr32(fp0, fd);
  6441 + tcg_temp_free(fp0);
  6442 + }
6250 6443 opn = "rsqrt.s";
6251 6444 break;
6252 6445 case FOP(28, 16):
6253 6446 check_cp1_64bitmode(ctx);
6254   - gen_load_fpr32(fpu32_T[0], fs);
6255   - gen_load_fpr32(fpu32_T[2], fd);
6256   - tcg_gen_helper_0_0(do_float_recip2_s);
6257   - gen_store_fpr32(fpu32_T[2], fd);
  6447 + {
  6448 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6449 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  6450 +
  6451 + gen_load_fpr32(fp0, fs);
  6452 + gen_load_fpr32(fp1, fd);
  6453 + tcg_gen_helper_1_2(do_float_recip2_s, fp0, fp0, fp1);
  6454 + tcg_temp_free(fp1);
  6455 + gen_store_fpr32(fp0, fd);
  6456 + tcg_temp_free(fp0);
  6457 + }
6258 6458 opn = "recip2.s";
6259 6459 break;
6260 6460 case FOP(29, 16):
6261 6461 check_cp1_64bitmode(ctx);
6262   - gen_load_fpr32(fpu32_T[0], fs);
6263   - tcg_gen_helper_0_0(do_float_recip1_s);
6264   - gen_store_fpr32(fpu32_T[2], fd);
  6462 + {
  6463 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6464 +
  6465 + gen_load_fpr32(fp0, fs);
  6466 + tcg_gen_helper_1_1(do_float_recip1_s, fp0, fp0);
  6467 + gen_store_fpr32(fp0, fd);
  6468 + tcg_temp_free(fp0);
  6469 + }
6265 6470 opn = "recip1.s";
6266 6471 break;
6267 6472 case FOP(30, 16):
6268 6473 check_cp1_64bitmode(ctx);
6269   - gen_load_fpr32(fpu32_T[0], fs);
6270   - tcg_gen_helper_0_0(do_float_rsqrt1_s);
6271   - gen_store_fpr32(fpu32_T[2], fd);
  6474 + {
  6475 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6476 +
  6477 + gen_load_fpr32(fp0, fs);
  6478 + tcg_gen_helper_1_1(do_float_rsqrt1_s, fp0, fp0);
  6479 + gen_store_fpr32(fp0, fd);
  6480 + tcg_temp_free(fp0);
  6481 + }
6272 6482 opn = "rsqrt1.s";
6273 6483 break;
6274 6484 case FOP(31, 16):
6275 6485 check_cp1_64bitmode(ctx);
6276   - gen_load_fpr32(fpu32_T[0], fs);
6277   - gen_load_fpr32(fpu32_T[2], ft);
6278   - tcg_gen_helper_0_0(do_float_rsqrt2_s);
6279   - gen_store_fpr32(fpu32_T[2], fd);
  6486 + {
  6487 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6488 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  6489 +
  6490 + gen_load_fpr32(fp0, fs);
  6491 + gen_load_fpr32(fp1, ft);
  6492 + tcg_gen_helper_1_2(do_float_rsqrt2_s, fp0, fp0, fp1);
  6493 + tcg_temp_free(fp1);
  6494 + gen_store_fpr32(fp0, fd);
  6495 + tcg_temp_free(fp0);
  6496 + }
6280 6497 opn = "rsqrt2.s";
6281 6498 break;
6282 6499 case FOP(33, 16):
6283 6500 check_cp1_registers(ctx, fd);
6284   - gen_load_fpr32(fpu32_T[0], fs);
6285   - tcg_gen_helper_0_0(do_float_cvtd_s);
6286   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6501 + {
  6502 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  6503 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  6504 +
  6505 + gen_load_fpr32(fp32, fs);
  6506 + tcg_gen_helper_1_1(do_float_cvtd_s, fp64, fp32);
  6507 + tcg_temp_free(fp32);
  6508 + gen_store_fpr64(ctx, fp64, fd);
  6509 + tcg_temp_free(fp64);
  6510 + }
6287 6511 opn = "cvt.d.s";
6288 6512 break;
6289 6513 case FOP(36, 16):
6290   - gen_load_fpr32(fpu32_T[0], fs);
6291   - tcg_gen_helper_0_0(do_float_cvtw_s);
6292   - gen_store_fpr32(fpu32_T[2], fd);
  6514 + {
  6515 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6516 +
  6517 + gen_load_fpr32(fp0, fs);
  6518 + tcg_gen_helper_1_1(do_float_cvtw_s, fp0, fp0);
  6519 + gen_store_fpr32(fp0, fd);
  6520 + tcg_temp_free(fp0);
  6521 + }
6293 6522 opn = "cvt.w.s";
6294 6523 break;
6295 6524 case FOP(37, 16):
6296 6525 check_cp1_64bitmode(ctx);
6297   - gen_load_fpr32(fpu32_T[0], fs);
6298   - tcg_gen_helper_0_0(do_float_cvtl_s);
6299   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6526 + {
  6527 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  6528 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  6529 +
  6530 + gen_load_fpr32(fp32, fs);
  6531 + tcg_gen_helper_1_1(do_float_cvtl_s, fp64, fp32);
  6532 + tcg_temp_free(fp32);
  6533 + gen_store_fpr64(ctx, fp64, fd);
  6534 + tcg_temp_free(fp64);
  6535 + }
6300 6536 opn = "cvt.l.s";
6301 6537 break;
6302 6538 case FOP(38, 16):
6303 6539 check_cp1_64bitmode(ctx);
6304   - gen_load_fpr32(fpu32_T[0], fs);
6305   - gen_load_fpr32(fpu32_T[1], ft);
6306   - tcg_gen_extu_i32_i64(fpu64_T[0], fpu32_T[0]);
6307   - tcg_gen_extu_i32_i64(fpu64_T[1], fpu32_T[1]);
6308   - tcg_gen_shli_i64(fpu64_T[1], fpu64_T[1], 32);
6309   - tcg_gen_or_i64(fpu64_T[2], fpu64_T[0], fpu64_T[1]);
6310   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6540 + {
  6541 + TCGv fp64_0 = tcg_temp_new(TCG_TYPE_I64);
  6542 + TCGv fp64_1 = tcg_temp_new(TCG_TYPE_I64);
  6543 + TCGv fp32_0 = tcg_temp_new(TCG_TYPE_I32);
  6544 + TCGv fp32_1 = tcg_temp_new(TCG_TYPE_I32);
  6545 +
  6546 + gen_load_fpr32(fp32_0, fs);
  6547 + gen_load_fpr32(fp32_1, ft);
  6548 + tcg_gen_extu_i32_i64(fp64_0, fp32_0);
  6549 + tcg_gen_extu_i32_i64(fp64_1, fp32_1);
  6550 + tcg_temp_free(fp32_0);
  6551 + tcg_temp_free(fp32_1);
  6552 + tcg_gen_shli_i64(fp64_1, fp64_1, 32);
  6553 + tcg_gen_or_i64(fp64_0, fp64_0, fp64_1);
  6554 + tcg_temp_free(fp64_1);
  6555 + gen_store_fpr64(ctx, fp64_0, fd);
  6556 + tcg_temp_free(fp64_0);
  6557 + }
6311 6558 opn = "cvt.ps.s";
6312 6559 break;
6313 6560 case FOP(48, 16):
... ... @@ -6326,217 +6573,351 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6326 6573 case FOP(61, 16):
6327 6574 case FOP(62, 16):
6328 6575 case FOP(63, 16):
6329   - gen_load_fpr32(fpu32_T[0], fs);
6330   - gen_load_fpr32(fpu32_T[1], ft);
6331   - if (ctx->opcode & (1 << 6)) {
6332   - check_cop1x(ctx);
6333   - gen_cmpabs_s(func-48, cc);
6334   - opn = condnames_abs[func-48];
6335   - } else {
6336   - gen_cmp_s(func-48, cc);
6337   - opn = condnames[func-48];
  6576 + {
  6577 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  6578 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  6579 +
  6580 + gen_load_fpr32(fp0, fs);
  6581 + gen_load_fpr32(fp1, ft);
  6582 + if (ctx->opcode & (1 << 6)) {
  6583 + check_cop1x(ctx);
  6584 + gen_cmpabs_s(func-48, fp0, fp1, cc);
  6585 + opn = condnames_abs[func-48];
  6586 + } else {
  6587 + gen_cmp_s(func-48, fp0, fp1, cc);
  6588 + opn = condnames[func-48];
  6589 + }
  6590 + tcg_temp_free(fp0);
  6591 + tcg_temp_free(fp1);
6338 6592 }
6339 6593 break;
6340 6594 case FOP(0, 17):
6341 6595 check_cp1_registers(ctx, fs | ft | fd);
6342   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6343   - gen_load_fpr64(ctx, fpu64_T[1], ft);
6344   - tcg_gen_helper_0_0(do_float_add_d);
6345   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6596 + {
  6597 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6598 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  6599 +
  6600 + gen_load_fpr64(ctx, fp0, fs);
  6601 + gen_load_fpr64(ctx, fp1, ft);
  6602 + tcg_gen_helper_1_2(do_float_add_d, fp0, fp0, fp1);
  6603 + tcg_temp_free(fp1);
  6604 + gen_store_fpr64(ctx, fp0, fd);
  6605 + tcg_temp_free(fp0);
  6606 + }
6346 6607 opn = "add.d";
6347 6608 optype = BINOP;
6348 6609 break;
6349 6610 case FOP(1, 17):
6350 6611 check_cp1_registers(ctx, fs | ft | fd);
6351   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6352   - gen_load_fpr64(ctx, fpu64_T[1], ft);
6353   - tcg_gen_helper_0_0(do_float_sub_d);
6354   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6612 + {
  6613 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6614 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  6615 +
  6616 + gen_load_fpr64(ctx, fp0, fs);
  6617 + gen_load_fpr64(ctx, fp1, ft);
  6618 + tcg_gen_helper_1_2(do_float_sub_d, fp0, fp0, fp1);
  6619 + tcg_temp_free(fp1);
  6620 + gen_store_fpr64(ctx, fp0, fd);
  6621 + tcg_temp_free(fp0);
  6622 + }
6355 6623 opn = "sub.d";
6356 6624 optype = BINOP;
6357 6625 break;
6358 6626 case FOP(2, 17):
6359 6627 check_cp1_registers(ctx, fs | ft | fd);
6360   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6361   - gen_load_fpr64(ctx, fpu64_T[1], ft);
6362   - tcg_gen_helper_0_0(do_float_mul_d);
6363   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6628 + {
  6629 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6630 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  6631 +
  6632 + gen_load_fpr64(ctx, fp0, fs);
  6633 + gen_load_fpr64(ctx, fp1, ft);
  6634 + tcg_gen_helper_1_2(do_float_mul_d, fp0, fp0, fp1);
  6635 + tcg_temp_free(fp1);
  6636 + gen_store_fpr64(ctx, fp0, fd);
  6637 + tcg_temp_free(fp0);
  6638 + }
6364 6639 opn = "mul.d";
6365 6640 optype = BINOP;
6366 6641 break;
6367 6642 case FOP(3, 17):
6368 6643 check_cp1_registers(ctx, fs | ft | fd);
6369   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6370   - gen_load_fpr64(ctx, fpu64_T[1], ft);
6371   - tcg_gen_helper_0_0(do_float_div_d);
6372   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6644 + {
  6645 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6646 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  6647 +
  6648 + gen_load_fpr64(ctx, fp0, fs);
  6649 + gen_load_fpr64(ctx, fp1, ft);
  6650 + tcg_gen_helper_1_2(do_float_div_d, fp0, fp0, fp1);
  6651 + tcg_temp_free(fp1);
  6652 + gen_store_fpr64(ctx, fp0, fd);
  6653 + tcg_temp_free(fp0);
  6654 + }
6373 6655 opn = "div.d";
6374 6656 optype = BINOP;
6375 6657 break;
6376 6658 case FOP(4, 17):
6377 6659 check_cp1_registers(ctx, fs | fd);
6378   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6379   - tcg_gen_helper_0_0(do_float_sqrt_d);
6380   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6660 + {
  6661 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6662 +
  6663 + gen_load_fpr64(ctx, fp0, fs);
  6664 + tcg_gen_helper_1_1(do_float_sqrt_d, fp0, fp0);
  6665 + gen_store_fpr64(ctx, fp0, fd);
  6666 + tcg_temp_free(fp0);
  6667 + }
6381 6668 opn = "sqrt.d";
6382 6669 break;
6383 6670 case FOP(5, 17):
6384 6671 check_cp1_registers(ctx, fs | fd);
6385   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6386   - tcg_gen_helper_0_0(do_float_abs_d);
6387   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6672 + {
  6673 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6674 +
  6675 + gen_load_fpr64(ctx, fp0, fs);
  6676 + tcg_gen_helper_1_1(do_float_abs_d, fp0, fp0);
  6677 + gen_store_fpr64(ctx, fp0, fd);
  6678 + tcg_temp_free(fp0);
  6679 + }
6388 6680 opn = "abs.d";
6389 6681 break;
6390 6682 case FOP(6, 17):
6391 6683 check_cp1_registers(ctx, fs | fd);
6392   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6393   - gen_store_fpr64(ctx, fpu64_T[0], fd);
  6684 + {
  6685 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6686 +
  6687 + gen_load_fpr64(ctx, fp0, fs);
  6688 + gen_store_fpr64(ctx, fp0, fd);
  6689 + tcg_temp_free(fp0);
  6690 + }
6394 6691 opn = "mov.d";
6395 6692 break;
6396 6693 case FOP(7, 17):
6397 6694 check_cp1_registers(ctx, fs | fd);
6398   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6399   - tcg_gen_helper_0_0(do_float_chs_d);
6400   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6695 + {
  6696 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6697 +
  6698 + gen_load_fpr64(ctx, fp0, fs);
  6699 + tcg_gen_helper_1_1(do_float_chs_d, fp0, fp0);
  6700 + gen_store_fpr64(ctx, fp0, fd);
  6701 + tcg_temp_free(fp0);
  6702 + }
6401 6703 opn = "neg.d";
6402 6704 break;
6403 6705 case FOP(8, 17):
6404 6706 check_cp1_64bitmode(ctx);
6405   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6406   - tcg_gen_helper_0_0(do_float_roundl_d);
6407   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6707 + {
  6708 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6709 +
  6710 + gen_load_fpr64(ctx, fp0, fs);
  6711 + tcg_gen_helper_1_1(do_float_roundl_d, fp0, fp0);
  6712 + gen_store_fpr64(ctx, fp0, fd);
  6713 + tcg_temp_free(fp0);
  6714 + }
6408 6715 opn = "round.l.d";
6409 6716 break;
6410 6717 case FOP(9, 17):
6411 6718 check_cp1_64bitmode(ctx);
6412   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6413   - tcg_gen_helper_0_0(do_float_truncl_d);
6414   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6719 + {
  6720 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6721 +
  6722 + gen_load_fpr64(ctx, fp0, fs);
  6723 + tcg_gen_helper_1_1(do_float_truncl_d, fp0, fp0);
  6724 + gen_store_fpr64(ctx, fp0, fd);
  6725 + tcg_temp_free(fp0);
  6726 + }
6415 6727 opn = "trunc.l.d";
6416 6728 break;
6417 6729 case FOP(10, 17):
6418 6730 check_cp1_64bitmode(ctx);
6419   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6420   - tcg_gen_helper_0_0(do_float_ceill_d);
6421   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6731 + {
  6732 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6733 +
  6734 + gen_load_fpr64(ctx, fp0, fs);
  6735 + tcg_gen_helper_1_1(do_float_ceill_d, fp0, fp0);
  6736 + gen_store_fpr64(ctx, fp0, fd);
  6737 + tcg_temp_free(fp0);
  6738 + }
6422 6739 opn = "ceil.l.d";
6423 6740 break;
6424 6741 case FOP(11, 17):
6425 6742 check_cp1_64bitmode(ctx);
6426   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6427   - tcg_gen_helper_0_0(do_float_floorl_d);
6428   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6743 + {
  6744 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6745 +
  6746 + gen_load_fpr64(ctx, fp0, fs);
  6747 + tcg_gen_helper_1_1(do_float_floorl_d, fp0, fp0);
  6748 + gen_store_fpr64(ctx, fp0, fd);
  6749 + tcg_temp_free(fp0);
  6750 + }
6429 6751 opn = "floor.l.d";
6430 6752 break;
6431 6753 case FOP(12, 17):
6432 6754 check_cp1_registers(ctx, fs);
6433   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6434   - tcg_gen_helper_0_0(do_float_roundw_d);
6435   - gen_store_fpr32(fpu32_T[2], fd);
  6755 + {
  6756 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  6757 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  6758 +
  6759 + gen_load_fpr64(ctx, fp64, fs);
  6760 + tcg_gen_helper_1_1(do_float_roundw_d, fp32, fp64);
  6761 + tcg_temp_free(fp64);
  6762 + gen_store_fpr32(fp32, fd);
  6763 + tcg_temp_free(fp32);
  6764 + }
6436 6765 opn = "round.w.d";
6437 6766 break;
6438 6767 case FOP(13, 17):
6439 6768 check_cp1_registers(ctx, fs);
6440   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6441   - tcg_gen_helper_0_0(do_float_truncw_d);
6442   - gen_store_fpr32(fpu32_T[2], fd);
  6769 + {
  6770 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  6771 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  6772 +
  6773 + gen_load_fpr64(ctx, fp64, fs);
  6774 + tcg_gen_helper_1_1(do_float_truncw_d, fp32, fp64);
  6775 + tcg_temp_free(fp64);
  6776 + gen_store_fpr32(fp32, fd);
  6777 + tcg_temp_free(fp32);
  6778 + }
6443 6779 opn = "trunc.w.d";
6444 6780 break;
6445 6781 case FOP(14, 17):
6446 6782 check_cp1_registers(ctx, fs);
6447   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6448   - tcg_gen_helper_0_0(do_float_ceilw_d);
6449   - gen_store_fpr32(fpu32_T[2], fd);
  6783 + {
  6784 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  6785 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  6786 +
  6787 + gen_load_fpr64(ctx, fp64, fs);
  6788 + tcg_gen_helper_1_1(do_float_ceilw_d, fp32, fp64);
  6789 + tcg_temp_free(fp64);
  6790 + gen_store_fpr32(fp32, fd);
  6791 + tcg_temp_free(fp32);
  6792 + }
6450 6793 opn = "ceil.w.d";
6451 6794 break;
6452 6795 case FOP(15, 17):
6453 6796 check_cp1_registers(ctx, fs);
6454   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6455   - tcg_gen_helper_0_0(do_float_floorw_d);
6456   - gen_store_fpr32(fpu32_T[2], fd);
  6797 + {
  6798 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  6799 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  6800 +
  6801 + gen_load_fpr64(ctx, fp64, fs);
  6802 + tcg_gen_helper_1_1(do_float_floorw_d, fp32, fp64);
  6803 + tcg_temp_free(fp64);
  6804 + gen_store_fpr32(fp32, fd);
  6805 + tcg_temp_free(fp32);
  6806 + }
6457 6807 opn = "floor.w.d";
6458 6808 break;
6459 6809 case FOP(17, 17):
6460   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6461   - gen_load_fpr64(ctx, fpu64_T[2], fd);
6462   - gen_movcf_d((ft >> 2) & 0x7, ft & 0x1);
6463   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6810 + gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
6464 6811 opn = "movcf.d";
6465 6812 break;
6466 6813 case FOP(18, 17):
6467   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6468   - gen_load_fpr64(ctx, fpu64_T[2], fd);
6469 6814 {
6470 6815 int l1 = gen_new_label();
6471 6816 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  6817 + TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I64);
6472 6818  
6473 6819 gen_load_gpr(t0, ft);
6474 6820 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
6475 6821 tcg_temp_free(t0);
6476   - tcg_gen_mov_i64(fpu64_T[2], fpu64_T[0]);
  6822 + gen_load_fpr64(ctx, fp0, fs);
  6823 + gen_store_fpr64(ctx, fp0, fd);
  6824 + tcg_temp_free(fp0);
6477 6825 gen_set_label(l1);
6478 6826 }
6479   - gen_store_fpr64(ctx, fpu64_T[2], fd);
6480 6827 opn = "movz.d";
6481 6828 break;
6482 6829 case FOP(19, 17):
6483   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6484   - gen_load_fpr64(ctx, fpu64_T[2], fd);
6485 6830 {
6486 6831 int l1 = gen_new_label();
6487 6832 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  6833 + TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I64);
6488 6834  
6489 6835 gen_load_gpr(t0, ft);
6490 6836 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6491 6837 tcg_temp_free(t0);
6492   - tcg_gen_mov_i64(fpu64_T[2], fpu64_T[0]);
  6838 + gen_load_fpr64(ctx, fp0, fs);
  6839 + gen_store_fpr64(ctx, fp0, fd);
  6840 + tcg_temp_free(fp0);
6493 6841 gen_set_label(l1);
6494 6842 }
6495   - gen_store_fpr64(ctx, fpu64_T[2], fd);
6496 6843 opn = "movn.d";
6497 6844 break;
6498 6845 case FOP(21, 17):
6499 6846 check_cp1_64bitmode(ctx);
6500   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6501   - tcg_gen_helper_0_0(do_float_recip_d);
6502   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6847 + {
  6848 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6849 +
  6850 + gen_load_fpr64(ctx, fp0, fs);
  6851 + tcg_gen_helper_1_1(do_float_recip_d, fp0, fp0);
  6852 + gen_store_fpr64(ctx, fp0, fd);
  6853 + tcg_temp_free(fp0);
  6854 + }
6503 6855 opn = "recip.d";
6504 6856 break;
6505 6857 case FOP(22, 17):
6506 6858 check_cp1_64bitmode(ctx);
6507   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6508   - tcg_gen_helper_0_0(do_float_rsqrt_d);
6509   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6859 + {
  6860 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6861 +
  6862 + gen_load_fpr64(ctx, fp0, fs);
  6863 + tcg_gen_helper_1_1(do_float_rsqrt_d, fp0, fp0);
  6864 + gen_store_fpr64(ctx, fp0, fd);
  6865 + tcg_temp_free(fp0);
  6866 + }
6510 6867 opn = "rsqrt.d";
6511 6868 break;
6512 6869 case FOP(28, 17):
6513 6870 check_cp1_64bitmode(ctx);
6514   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6515   - gen_load_fpr64(ctx, fpu64_T[2], ft);
6516   - tcg_gen_helper_0_0(do_float_recip2_d);
6517   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6871 + {
  6872 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6873 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  6874 +
  6875 + gen_load_fpr64(ctx, fp0, fs);
  6876 + gen_load_fpr64(ctx, fp1, ft);
  6877 + tcg_gen_helper_1_2(do_float_recip2_d, fp0, fp0, fp1);
  6878 + tcg_temp_free(fp1);
  6879 + gen_store_fpr64(ctx, fp0, fd);
  6880 + tcg_temp_free(fp0);
  6881 + }
6518 6882 opn = "recip2.d";
6519 6883 break;
6520 6884 case FOP(29, 17):
6521 6885 check_cp1_64bitmode(ctx);
6522   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6523   - tcg_gen_helper_0_0(do_float_recip1_d);
6524   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6886 + {
  6887 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6888 +
  6889 + gen_load_fpr64(ctx, fp0, fs);
  6890 + tcg_gen_helper_1_1(do_float_recip1_d, fp0, fp0);
  6891 + gen_store_fpr64(ctx, fp0, fd);
  6892 + tcg_temp_free(fp0);
  6893 + }
6525 6894 opn = "recip1.d";
6526 6895 break;
6527 6896 case FOP(30, 17):
6528 6897 check_cp1_64bitmode(ctx);
6529   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6530   - tcg_gen_helper_0_0(do_float_rsqrt1_d);
6531   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6898 + {
  6899 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6900 +
  6901 + gen_load_fpr64(ctx, fp0, fs);
  6902 + tcg_gen_helper_1_1(do_float_rsqrt1_d, fp0, fp0);
  6903 + gen_store_fpr64(ctx, fp0, fd);
  6904 + tcg_temp_free(fp0);
  6905 + }
6532 6906 opn = "rsqrt1.d";
6533 6907 break;
6534 6908 case FOP(31, 17):
6535 6909 check_cp1_64bitmode(ctx);
6536   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6537   - gen_load_fpr64(ctx, fpu64_T[2], ft);
6538   - tcg_gen_helper_0_0(do_float_rsqrt2_d);
6539   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6910 + {
  6911 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6912 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  6913 +
  6914 + gen_load_fpr64(ctx, fp0, fs);
  6915 + gen_load_fpr64(ctx, fp1, ft);
  6916 + tcg_gen_helper_1_2(do_float_rsqrt2_d, fp0, fp0, fp1);
  6917 + tcg_temp_free(fp1);
  6918 + gen_store_fpr64(ctx, fp0, fd);
  6919 + tcg_temp_free(fp0);
  6920 + }
6540 6921 opn = "rsqrt2.d";
6541 6922 break;
6542 6923 case FOP(48, 17):
... ... @@ -6555,303 +6936,434 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6555 6936 case FOP(61, 17):
6556 6937 case FOP(62, 17):
6557 6938 case FOP(63, 17):
6558   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6559   - gen_load_fpr64(ctx, fpu64_T[1], ft);
6560   - if (ctx->opcode & (1 << 6)) {
6561   - check_cop1x(ctx);
6562   - check_cp1_registers(ctx, fs | ft);
6563   - gen_cmpabs_d(func-48, cc);
6564   - opn = condnames_abs[func-48];
6565   - } else {
6566   - check_cp1_registers(ctx, fs | ft);
6567   - gen_cmp_d(func-48, cc);
6568   - opn = condnames[func-48];
  6939 + {
  6940 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6941 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  6942 +
  6943 + gen_load_fpr64(ctx, fp0, fs);
  6944 + gen_load_fpr64(ctx, fp1, ft);
  6945 + if (ctx->opcode & (1 << 6)) {
  6946 + check_cop1x(ctx);
  6947 + check_cp1_registers(ctx, fs | ft);
  6948 + gen_cmpabs_d(func-48, fp0, fp1, cc);
  6949 + opn = condnames_abs[func-48];
  6950 + } else {
  6951 + check_cp1_registers(ctx, fs | ft);
  6952 + gen_cmp_d(func-48, fp0, fp1, cc);
  6953 + opn = condnames[func-48];
  6954 + }
  6955 + tcg_temp_free(fp0);
  6956 + tcg_temp_free(fp1);
6569 6957 }
6570 6958 break;
6571 6959 case FOP(32, 17):
6572 6960 check_cp1_registers(ctx, fs);
6573   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6574   - tcg_gen_helper_0_0(do_float_cvts_d);
6575   - gen_store_fpr32(fpu32_T[2], fd);
  6961 + {
  6962 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  6963 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  6964 +
  6965 + gen_load_fpr64(ctx, fp64, fs);
  6966 + tcg_gen_helper_1_1(do_float_cvts_d, fp32, fp64);
  6967 + tcg_temp_free(fp64);
  6968 + gen_store_fpr32(fp32, fd);
  6969 + tcg_temp_free(fp32);
  6970 + }
6576 6971 opn = "cvt.s.d";
6577 6972 break;
6578 6973 case FOP(36, 17):
6579 6974 check_cp1_registers(ctx, fs);
6580   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6581   - tcg_gen_helper_0_0(do_float_cvtw_d);
6582   - gen_store_fpr32(fpu32_T[2], fd);
  6975 + {
  6976 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  6977 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  6978 +
  6979 + gen_load_fpr64(ctx, fp64, fs);
  6980 + tcg_gen_helper_1_1(do_float_cvtw_d, fp32, fp64);
  6981 + tcg_temp_free(fp64);
  6982 + gen_store_fpr32(fp32, fd);
  6983 + tcg_temp_free(fp32);
  6984 + }
6583 6985 opn = "cvt.w.d";
6584 6986 break;
6585 6987 case FOP(37, 17):
6586 6988 check_cp1_64bitmode(ctx);
6587   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6588   - tcg_gen_helper_0_0(do_float_cvtl_d);
6589   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  6989 + {
  6990 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  6991 +
  6992 + gen_load_fpr64(ctx, fp0, fs);
  6993 + tcg_gen_helper_1_1(do_float_cvtl_d, fp0, fp0);
  6994 + gen_store_fpr64(ctx, fp0, fd);
  6995 + tcg_temp_free(fp0);
  6996 + }
6590 6997 opn = "cvt.l.d";
6591 6998 break;
6592 6999 case FOP(32, 20):
6593   - gen_load_fpr32(fpu32_T[0], fs);
6594   - tcg_gen_helper_0_0(do_float_cvts_w);
6595   - gen_store_fpr32(fpu32_T[2], fd);
  7000 + {
  7001 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  7002 +
  7003 + gen_load_fpr32(fp0, fs);
  7004 + tcg_gen_helper_1_1(do_float_cvts_w, fp0, fp0);
  7005 + gen_store_fpr32(fp0, fd);
  7006 + tcg_temp_free(fp0);
  7007 + }
6596 7008 opn = "cvt.s.w";
6597 7009 break;
6598 7010 case FOP(33, 20):
6599 7011 check_cp1_registers(ctx, fd);
6600   - gen_load_fpr32(fpu32_T[0], fs);
6601   - tcg_gen_helper_0_0(do_float_cvtd_w);
6602   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  7012 + {
  7013 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  7014 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  7015 +
  7016 + gen_load_fpr32(fp32, fs);
  7017 + tcg_gen_helper_1_1(do_float_cvtd_w, fp64, fp32);
  7018 + tcg_temp_free(fp32);
  7019 + gen_store_fpr64(ctx, fp64, fd);
  7020 + tcg_temp_free(fp64);
  7021 + }
6603 7022 opn = "cvt.d.w";
6604 7023 break;
6605 7024 case FOP(32, 21):
6606 7025 check_cp1_64bitmode(ctx);
6607   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6608   - tcg_gen_helper_0_0(do_float_cvts_l);
6609   - gen_store_fpr32(fpu32_T[2], fd);
  7026 + {
  7027 + TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
  7028 + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
  7029 +
  7030 + gen_load_fpr64(ctx, fp64, fs);
  7031 + tcg_gen_helper_1_1(do_float_cvts_l, fp32, fp64);
  7032 + tcg_temp_free(fp64);
  7033 + gen_store_fpr32(fp32, fd);
  7034 + tcg_temp_free(fp32);
  7035 + }
6610 7036 opn = "cvt.s.l";
6611 7037 break;
6612 7038 case FOP(33, 21):
6613 7039 check_cp1_64bitmode(ctx);
6614   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6615   - tcg_gen_helper_0_0(do_float_cvtd_l);
6616   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  7040 + {
  7041 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7042 +
  7043 + gen_load_fpr64(ctx, fp0, fs);
  7044 + tcg_gen_helper_1_1(do_float_cvtd_l, fp0, fp0);
  7045 + gen_store_fpr64(ctx, fp0, fd);
  7046 + tcg_temp_free(fp0);
  7047 + }
6617 7048 opn = "cvt.d.l";
6618 7049 break;
6619 7050 case FOP(38, 20):
6620 7051 check_cp1_64bitmode(ctx);
6621   - gen_load_fpr32(fpu32_T[0], fs);
6622   - gen_load_fpr32h(fpu32h_T[0], fs);
6623   - tcg_gen_helper_0_0(do_float_cvtps_pw);
6624   - gen_store_fpr32(fpu32_T[2], fd);
6625   - gen_store_fpr32h(fpu32h_T[2], fd);
  7052 + {
  7053 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7054 +
  7055 + gen_load_fpr64(ctx, fp0, fs);
  7056 + tcg_gen_helper_1_1(do_float_cvtps_pw, fp0, fp0);
  7057 + gen_store_fpr64(ctx, fp0, fd);
  7058 + tcg_temp_free(fp0);
  7059 + }
6626 7060 opn = "cvt.ps.pw";
6627 7061 break;
6628 7062 case FOP(0, 22):
6629 7063 check_cp1_64bitmode(ctx);
6630   - gen_load_fpr32(fpu32_T[0], fs);
6631   - gen_load_fpr32h(fpu32h_T[0], fs);
6632   - gen_load_fpr32(fpu32_T[1], ft);
6633   - gen_load_fpr32h(fpu32h_T[1], ft);
6634   - tcg_gen_helper_0_0(do_float_add_ps);
6635   - gen_store_fpr32(fpu32_T[2], fd);
6636   - gen_store_fpr32h(fpu32h_T[2], fd);
  7064 + {
  7065 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7066 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7067 +
  7068 + gen_load_fpr64(ctx, fp0, fs);
  7069 + gen_load_fpr64(ctx, fp1, ft);
  7070 + tcg_gen_helper_1_2(do_float_add_ps, fp0, fp0, fp1);
  7071 + tcg_temp_free(fp1);
  7072 + gen_store_fpr64(ctx, fp0, fd);
  7073 + tcg_temp_free(fp0);
  7074 + }
6637 7075 opn = "add.ps";
6638 7076 break;
6639 7077 case FOP(1, 22):
6640 7078 check_cp1_64bitmode(ctx);
6641   - gen_load_fpr32(fpu32_T[0], fs);
6642   - gen_load_fpr32h(fpu32h_T[0], fs);
6643   - gen_load_fpr32(fpu32_T[1], ft);
6644   - gen_load_fpr32h(fpu32h_T[1], ft);
6645   - tcg_gen_helper_0_0(do_float_sub_ps);
6646   - gen_store_fpr32(fpu32_T[2], fd);
6647   - gen_store_fpr32h(fpu32h_T[2], fd);
  7079 + {
  7080 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7081 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7082 +
  7083 + gen_load_fpr64(ctx, fp0, fs);
  7084 + gen_load_fpr64(ctx, fp1, ft);
  7085 + tcg_gen_helper_1_2(do_float_sub_ps, fp0, fp0, fp1);
  7086 + tcg_temp_free(fp1);
  7087 + gen_store_fpr64(ctx, fp0, fd);
  7088 + tcg_temp_free(fp0);
  7089 + }
6648 7090 opn = "sub.ps";
6649 7091 break;
6650 7092 case FOP(2, 22):
6651 7093 check_cp1_64bitmode(ctx);
6652   - gen_load_fpr32(fpu32_T[0], fs);
6653   - gen_load_fpr32h(fpu32h_T[0], fs);
6654   - gen_load_fpr32(fpu32_T[1], ft);
6655   - gen_load_fpr32h(fpu32h_T[1], ft);
6656   - tcg_gen_helper_0_0(do_float_mul_ps);
6657   - gen_store_fpr32(fpu32_T[2], fd);
6658   - gen_store_fpr32h(fpu32h_T[2], fd);
  7094 + {
  7095 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7096 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7097 +
  7098 + gen_load_fpr64(ctx, fp0, fs);
  7099 + gen_load_fpr64(ctx, fp1, ft);
  7100 + tcg_gen_helper_1_2(do_float_mul_ps, fp0, fp0, fp1);
  7101 + tcg_temp_free(fp1);
  7102 + gen_store_fpr64(ctx, fp0, fd);
  7103 + tcg_temp_free(fp0);
  7104 + }
6659 7105 opn = "mul.ps";
6660 7106 break;
6661 7107 case FOP(5, 22):
6662 7108 check_cp1_64bitmode(ctx);
6663   - gen_load_fpr32(fpu32_T[0], fs);
6664   - gen_load_fpr32h(fpu32h_T[0], fs);
6665   - tcg_gen_helper_0_0(do_float_abs_ps);
6666   - gen_store_fpr32(fpu32_T[2], fd);
6667   - gen_store_fpr32h(fpu32h_T[2], fd);
  7109 + {
  7110 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7111 +
  7112 + gen_load_fpr64(ctx, fp0, fs);
  7113 + tcg_gen_helper_1_1(do_float_abs_ps, fp0, fp0);
  7114 + gen_store_fpr64(ctx, fp0, fd);
  7115 + tcg_temp_free(fp0);
  7116 + }
6668 7117 opn = "abs.ps";
6669 7118 break;
6670 7119 case FOP(6, 22):
6671 7120 check_cp1_64bitmode(ctx);
6672   - gen_load_fpr32(fpu32_T[0], fs);
6673   - gen_load_fpr32h(fpu32h_T[0], fs);
6674   - gen_store_fpr32(fpu32_T[0], fd);
6675   - gen_store_fpr32h(fpu32h_T[0], fd);
  7121 + {
  7122 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7123 +
  7124 + gen_load_fpr64(ctx, fp0, fs);
  7125 + gen_store_fpr64(ctx, fp0, fd);
  7126 + tcg_temp_free(fp0);
  7127 + }
6676 7128 opn = "mov.ps";
6677 7129 break;
6678 7130 case FOP(7, 22):
6679 7131 check_cp1_64bitmode(ctx);
6680   - gen_load_fpr32(fpu32_T[0], fs);
6681   - gen_load_fpr32h(fpu32h_T[0], fs);
6682   - tcg_gen_helper_0_0(do_float_chs_ps);
6683   - gen_store_fpr32(fpu32_T[2], fd);
6684   - gen_store_fpr32h(fpu32h_T[2], fd);
  7132 + {
  7133 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7134 +
  7135 + gen_load_fpr64(ctx, fp0, fs);
  7136 + tcg_gen_helper_1_1(do_float_chs_ps, fp0, fp0);
  7137 + gen_store_fpr64(ctx, fp0, fd);
  7138 + tcg_temp_free(fp0);
  7139 + }
6685 7140 opn = "neg.ps";
6686 7141 break;
6687 7142 case FOP(17, 22):
6688 7143 check_cp1_64bitmode(ctx);
6689   - gen_load_fpr32(fpu32_T[0], fs);
6690   - gen_load_fpr32h(fpu32h_T[0], fs);
6691   - gen_load_fpr32(fpu32_T[2], fd);
6692   - gen_load_fpr32h(fpu32h_T[2], fd);
6693   - gen_movcf_ps((ft >> 2) & 0x7, ft & 0x1);
6694   - gen_store_fpr32(fpu32_T[2], fd);
6695   - gen_store_fpr32h(fpu32h_T[2], fd);
  7144 + gen_movcf_ps(fs, fd, (ft >> 2) & 0x7, ft & 0x1);
6696 7145 opn = "movcf.ps";
6697 7146 break;
6698 7147 case FOP(18, 22):
6699 7148 check_cp1_64bitmode(ctx);
6700   - gen_load_fpr32(fpu32_T[0], fs);
6701   - gen_load_fpr32h(fpu32h_T[0], fs);
6702   - gen_load_fpr32(fpu32_T[2], fd);
6703   - gen_load_fpr32h(fpu32h_T[2], fd);
6704 7149 {
6705 7150 int l1 = gen_new_label();
6706 7151 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  7152 + TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
  7153 + TCGv fph0 = tcg_temp_local_new(TCG_TYPE_I32);
6707 7154  
6708 7155 gen_load_gpr(t0, ft);
6709 7156 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
6710 7157 tcg_temp_free(t0);
6711   - tcg_gen_mov_i32(fpu32_T[2], fpu32_T[0]);
6712   - tcg_gen_mov_i32(fpu32h_T[2], fpu32h_T[0]);
  7158 + gen_load_fpr32(fp0, fs);
  7159 + gen_load_fpr32h(fph0, fs);
  7160 + gen_store_fpr32(fp0, fd);
  7161 + gen_store_fpr32h(fph0, fd);
  7162 + tcg_temp_free(fp0);
  7163 + tcg_temp_free(fph0);
6713 7164 gen_set_label(l1);
6714 7165 }
6715   - gen_store_fpr32(fpu32_T[2], fd);
6716   - gen_store_fpr32h(fpu32h_T[2], fd);
6717 7166 opn = "movz.ps";
6718 7167 break;
6719 7168 case FOP(19, 22):
6720 7169 check_cp1_64bitmode(ctx);
6721   - gen_load_fpr32(fpu32_T[0], fs);
6722   - gen_load_fpr32h(fpu32h_T[0], fs);
6723   - gen_load_fpr32(fpu32_T[2], fd);
6724   - gen_load_fpr32h(fpu32h_T[2], fd);
6725 7170 {
6726 7171 int l1 = gen_new_label();
6727 7172 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  7173 + TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
  7174 + TCGv fph0 = tcg_temp_local_new(TCG_TYPE_I32);
6728 7175  
6729 7176 gen_load_gpr(t0, ft);
6730 7177 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6731 7178 tcg_temp_free(t0);
6732   - tcg_gen_mov_i32(fpu32_T[2], fpu32_T[0]);
6733   - tcg_gen_mov_i32(fpu32h_T[2], fpu32h_T[0]);
  7179 + gen_load_fpr32(fp0, fs);
  7180 + gen_load_fpr32h(fph0, fs);
  7181 + gen_store_fpr32(fp0, fd);
  7182 + gen_store_fpr32h(fph0, fd);
  7183 + tcg_temp_free(fp0);
  7184 + tcg_temp_free(fph0);
6734 7185 gen_set_label(l1);
6735 7186 }
6736   - gen_store_fpr32(fpu32_T[2], fd);
6737   - gen_store_fpr32h(fpu32h_T[2], fd);
6738 7187 opn = "movn.ps";
6739 7188 break;
6740 7189 case FOP(24, 22):
6741 7190 check_cp1_64bitmode(ctx);
6742   - gen_load_fpr32(fpu32_T[0], ft);
6743   - gen_load_fpr32h(fpu32h_T[0], ft);
6744   - gen_load_fpr32(fpu32_T[1], fs);
6745   - gen_load_fpr32h(fpu32h_T[1], fs);
6746   - tcg_gen_helper_0_0(do_float_addr_ps);
6747   - gen_store_fpr32(fpu32_T[2], fd);
6748   - gen_store_fpr32h(fpu32h_T[2], fd);
  7191 + {
  7192 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7193 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7194 +
  7195 + gen_load_fpr64(ctx, fp0, ft);
  7196 + gen_load_fpr64(ctx, fp1, fs);
  7197 + tcg_gen_helper_1_2(do_float_addr_ps, fp0, fp0, fp1);
  7198 + tcg_temp_free(fp1);
  7199 + gen_store_fpr64(ctx, fp0, fd);
  7200 + tcg_temp_free(fp0);
  7201 + }
6749 7202 opn = "addr.ps";
6750 7203 break;
6751 7204 case FOP(26, 22):
6752 7205 check_cp1_64bitmode(ctx);
6753   - gen_load_fpr32(fpu32_T[0], ft);
6754   - gen_load_fpr32h(fpu32h_T[0], ft);
6755   - gen_load_fpr32(fpu32_T[1], fs);
6756   - gen_load_fpr32h(fpu32h_T[1], fs);
6757   - tcg_gen_helper_0_0(do_float_mulr_ps);
6758   - gen_store_fpr32(fpu32_T[2], fd);
6759   - gen_store_fpr32h(fpu32h_T[2], fd);
  7206 + {
  7207 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7208 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7209 +
  7210 + gen_load_fpr64(ctx, fp0, ft);
  7211 + gen_load_fpr64(ctx, fp1, fs);
  7212 + tcg_gen_helper_1_2(do_float_mulr_ps, fp0, fp0, fp1);
  7213 + tcg_temp_free(fp1);
  7214 + gen_store_fpr64(ctx, fp0, fd);
  7215 + tcg_temp_free(fp0);
  7216 + }
6760 7217 opn = "mulr.ps";
6761 7218 break;
6762 7219 case FOP(28, 22):
6763 7220 check_cp1_64bitmode(ctx);
6764   - gen_load_fpr32(fpu32_T[0], fs);
6765   - gen_load_fpr32h(fpu32h_T[0], fs);
6766   - gen_load_fpr32(fpu32_T[2], fd);
6767   - gen_load_fpr32h(fpu32h_T[2], fd);
6768   - tcg_gen_helper_0_0(do_float_recip2_ps);
6769   - gen_store_fpr32(fpu32_T[2], fd);
6770   - gen_store_fpr32h(fpu32h_T[2], fd);
  7221 + {
  7222 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7223 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7224 +
  7225 + gen_load_fpr64(ctx, fp0, fs);
  7226 + gen_load_fpr64(ctx, fp1, fd);
  7227 + tcg_gen_helper_1_2(do_float_recip2_ps, fp0, fp0, fp1);
  7228 + tcg_temp_free(fp1);
  7229 + gen_store_fpr64(ctx, fp0, fd);
  7230 + tcg_temp_free(fp0);
  7231 + }
6771 7232 opn = "recip2.ps";
6772 7233 break;
6773 7234 case FOP(29, 22):
6774 7235 check_cp1_64bitmode(ctx);
6775   - gen_load_fpr32(fpu32_T[0], fs);
6776   - gen_load_fpr32h(fpu32h_T[0], fs);
6777   - tcg_gen_helper_0_0(do_float_recip1_ps);
6778   - gen_store_fpr32(fpu32_T[2], fd);
6779   - gen_store_fpr32h(fpu32h_T[2], fd);
  7236 + {
  7237 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7238 +
  7239 + gen_load_fpr64(ctx, fp0, fs);
  7240 + tcg_gen_helper_1_1(do_float_recip1_ps, fp0, fp0);
  7241 + gen_store_fpr64(ctx, fp0, fd);
  7242 + tcg_temp_free(fp0);
  7243 + }
6780 7244 opn = "recip1.ps";
6781 7245 break;
6782 7246 case FOP(30, 22):
6783 7247 check_cp1_64bitmode(ctx);
6784   - gen_load_fpr32(fpu32_T[0], fs);
6785   - gen_load_fpr32h(fpu32h_T[0], fs);
6786   - tcg_gen_helper_0_0(do_float_rsqrt1_ps);
6787   - gen_store_fpr32(fpu32_T[2], fd);
6788   - gen_store_fpr32h(fpu32h_T[2], fd);
  7248 + {
  7249 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7250 +
  7251 + gen_load_fpr64(ctx, fp0, fs);
  7252 + tcg_gen_helper_1_1(do_float_rsqrt1_ps, fp0, fp0);
  7253 + gen_store_fpr64(ctx, fp0, fd);
  7254 + tcg_temp_free(fp0);
  7255 + }
6789 7256 opn = "rsqrt1.ps";
6790 7257 break;
6791 7258 case FOP(31, 22):
6792 7259 check_cp1_64bitmode(ctx);
6793   - gen_load_fpr32(fpu32_T[0], fs);
6794   - gen_load_fpr32h(fpu32h_T[0], fs);
6795   - gen_load_fpr32(fpu32_T[2], ft);
6796   - gen_load_fpr32h(fpu32h_T[2], ft);
6797   - tcg_gen_helper_0_0(do_float_rsqrt2_ps);
6798   - gen_store_fpr32(fpu32_T[2], fd);
6799   - gen_store_fpr32h(fpu32h_T[2], fd);
  7260 + {
  7261 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7262 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7263 +
  7264 + gen_load_fpr64(ctx, fp0, fs);
  7265 + gen_load_fpr64(ctx, fp1, ft);
  7266 + tcg_gen_helper_1_2(do_float_rsqrt2_ps, fp0, fp0, fp1);
  7267 + tcg_temp_free(fp1);
  7268 + gen_store_fpr64(ctx, fp0, fd);
  7269 + tcg_temp_free(fp0);
  7270 + }
6800 7271 opn = "rsqrt2.ps";
6801 7272 break;
6802 7273 case FOP(32, 22):
6803 7274 check_cp1_64bitmode(ctx);
6804   - gen_load_fpr32h(fpu32h_T[0], fs);
6805   - tcg_gen_helper_0_0(do_float_cvts_pu);
6806   - gen_store_fpr32(fpu32_T[2], fd);
  7275 + {
  7276 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  7277 +
  7278 + gen_load_fpr32h(fp0, fs);
  7279 + tcg_gen_helper_1_1(do_float_cvts_pu, fp0, fp0);
  7280 + gen_store_fpr32(fp0, fd);
  7281 + tcg_temp_free(fp0);
  7282 + }
6807 7283 opn = "cvt.s.pu";
6808 7284 break;
6809 7285 case FOP(36, 22):
6810 7286 check_cp1_64bitmode(ctx);
6811   - gen_load_fpr32(fpu32_T[0], fs);
6812   - gen_load_fpr32h(fpu32h_T[0], fs);
6813   - tcg_gen_helper_0_0(do_float_cvtpw_ps);
6814   - gen_store_fpr32(fpu32_T[2], fd);
6815   - gen_store_fpr32h(fpu32h_T[2], fd);
  7287 + {
  7288 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7289 +
  7290 + gen_load_fpr64(ctx, fp0, fs);
  7291 + tcg_gen_helper_1_1(do_float_cvtpw_ps, fp0, fp0);
  7292 + gen_store_fpr64(ctx, fp0, fd);
  7293 + tcg_temp_free(fp0);
  7294 + }
6816 7295 opn = "cvt.pw.ps";
6817 7296 break;
6818 7297 case FOP(40, 22):
6819 7298 check_cp1_64bitmode(ctx);
6820   - gen_load_fpr32(fpu32_T[0], fs);
6821   - tcg_gen_helper_0_0(do_float_cvts_pl);
6822   - gen_store_fpr32(fpu32_T[2], fd);
  7299 + {
  7300 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  7301 +
  7302 + gen_load_fpr32(fp0, fs);
  7303 + tcg_gen_helper_1_1(do_float_cvts_pl, fp0, fp0);
  7304 + gen_store_fpr32(fp0, fd);
  7305 + tcg_temp_free(fp0);
  7306 + }
6823 7307 opn = "cvt.s.pl";
6824 7308 break;
6825 7309 case FOP(44, 22):
6826 7310 check_cp1_64bitmode(ctx);
6827   - gen_load_fpr32(fpu32_T[0], fs);
6828   - gen_load_fpr32(fpu32_T[1], ft);
6829   - gen_store_fpr32h(fpu32_T[0], fd);
6830   - gen_store_fpr32(fpu32_T[1], fd);
  7311 + {
  7312 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  7313 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  7314 +
  7315 + gen_load_fpr32(fp0, fs);
  7316 + gen_load_fpr32(fp1, ft);
  7317 + gen_store_fpr32h(fp0, fd);
  7318 + gen_store_fpr32(fp1, fd);
  7319 + tcg_temp_free(fp0);
  7320 + tcg_temp_free(fp1);
  7321 + }
6831 7322 opn = "pll.ps";
6832 7323 break;
6833 7324 case FOP(45, 22):
6834 7325 check_cp1_64bitmode(ctx);
6835   - gen_load_fpr32(fpu32_T[0], fs);
6836   - gen_load_fpr32h(fpu32h_T[1], ft);
6837   - gen_store_fpr32(fpu32h_T[1], fd);
6838   - gen_store_fpr32h(fpu32_T[0], fd);
  7326 + {
  7327 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  7328 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  7329 +
  7330 + gen_load_fpr32(fp0, fs);
  7331 + gen_load_fpr32h(fp1, ft);
  7332 + gen_store_fpr32(fp1, fd);
  7333 + gen_store_fpr32h(fp0, fd);
  7334 + tcg_temp_free(fp0);
  7335 + tcg_temp_free(fp1);
  7336 + }
6839 7337 opn = "plu.ps";
6840 7338 break;
6841 7339 case FOP(46, 22):
6842 7340 check_cp1_64bitmode(ctx);
6843   - gen_load_fpr32h(fpu32h_T[0], fs);
6844   - gen_load_fpr32(fpu32_T[1], ft);
6845   - gen_store_fpr32(fpu32_T[1], fd);
6846   - gen_store_fpr32h(fpu32h_T[0], fd);
  7341 + {
  7342 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  7343 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  7344 +
  7345 + gen_load_fpr32h(fp0, fs);
  7346 + gen_load_fpr32(fp1, ft);
  7347 + gen_store_fpr32(fp1, fd);
  7348 + gen_store_fpr32h(fp0, fd);
  7349 + tcg_temp_free(fp0);
  7350 + tcg_temp_free(fp1);
  7351 + }
6847 7352 opn = "pul.ps";
6848 7353 break;
6849 7354 case FOP(47, 22):
6850 7355 check_cp1_64bitmode(ctx);
6851   - gen_load_fpr32h(fpu32h_T[0], fs);
6852   - gen_load_fpr32h(fpu32h_T[1], ft);
6853   - gen_store_fpr32(fpu32h_T[1], fd);
6854   - gen_store_fpr32h(fpu32h_T[0], fd);
  7356 + {
  7357 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  7358 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  7359 +
  7360 + gen_load_fpr32h(fp0, fs);
  7361 + gen_load_fpr32h(fp1, ft);
  7362 + gen_store_fpr32(fp1, fd);
  7363 + gen_store_fpr32h(fp0, fd);
  7364 + tcg_temp_free(fp0);
  7365 + tcg_temp_free(fp1);
  7366 + }
6855 7367 opn = "puu.ps";
6856 7368 break;
6857 7369 case FOP(48, 22):
... ... @@ -6871,16 +7383,21 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6871 7383 case FOP(62, 22):
6872 7384 case FOP(63, 22):
6873 7385 check_cp1_64bitmode(ctx);
6874   - gen_load_fpr32(fpu32_T[0], fs);
6875   - gen_load_fpr32h(fpu32h_T[0], fs);
6876   - gen_load_fpr32(fpu32_T[1], ft);
6877   - gen_load_fpr32h(fpu32h_T[1], ft);
6878   - if (ctx->opcode & (1 << 6)) {
6879   - gen_cmpabs_ps(func-48, cc);
6880   - opn = condnames_abs[func-48];
6881   - } else {
6882   - gen_cmp_ps(func-48, cc);
6883   - opn = condnames[func-48];
  7386 + {
  7387 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7388 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7389 +
  7390 + gen_load_fpr64(ctx, fp0, fs);
  7391 + gen_load_fpr64(ctx, fp1, ft);
  7392 + if (ctx->opcode & (1 << 6)) {
  7393 + gen_cmpabs_ps(func-48, fp0, fp1, cc);
  7394 + opn = condnames_abs[func-48];
  7395 + } else {
  7396 + gen_cmp_ps(func-48, fp0, fp1, cc);
  7397 + opn = condnames[func-48];
  7398 + }
  7399 + tcg_temp_free(fp0);
  7400 + tcg_temp_free(fp1);
6884 7401 }
6885 7402 break;
6886 7403 default:
... ... @@ -6924,44 +7441,74 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
6924 7441 switch (opc) {
6925 7442 case OPC_LWXC1:
6926 7443 check_cop1x(ctx);
6927   - tcg_gen_qemu_ld32s(fpu32_T[0], t0, ctx->mem_idx);
6928   - gen_store_fpr32(fpu32_T[0], fd);
  7444 + {
  7445 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  7446 +
  7447 + tcg_gen_qemu_ld32s(fp0, t0, ctx->mem_idx);
  7448 + gen_store_fpr32(fp0, fd);
  7449 + tcg_temp_free(fp0);
  7450 + }
6929 7451 opn = "lwxc1";
6930 7452 break;
6931 7453 case OPC_LDXC1:
6932 7454 check_cop1x(ctx);
6933 7455 check_cp1_registers(ctx, fd);
6934   - tcg_gen_qemu_ld64(fpu64_T[0], t0, ctx->mem_idx);
6935   - gen_store_fpr64(ctx, fpu64_T[0], fd);
  7456 + {
  7457 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7458 +
  7459 + tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
  7460 + gen_store_fpr64(ctx, fp0, fd);
  7461 + tcg_temp_free(fp0);
  7462 + }
6936 7463 opn = "ldxc1";
6937 7464 break;
6938 7465 case OPC_LUXC1:
6939 7466 check_cp1_64bitmode(ctx);
6940 7467 tcg_gen_andi_tl(t0, t0, ~0x7);
6941   - tcg_gen_qemu_ld64(fpu64_T[0], t0, ctx->mem_idx);
6942   - gen_store_fpr64(ctx, fpu64_T[0], fd);
  7468 + {
  7469 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7470 +
  7471 + tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
  7472 + gen_store_fpr64(ctx, fp0, fd);
  7473 + tcg_temp_free(fp0);
  7474 + }
6943 7475 opn = "luxc1";
6944 7476 break;
6945 7477 case OPC_SWXC1:
6946 7478 check_cop1x(ctx);
6947   - gen_load_fpr32(fpu32_T[0], fs);
6948   - tcg_gen_qemu_st32(fpu32_T[0], t0, ctx->mem_idx);
  7479 + {
  7480 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  7481 +
  7482 + gen_load_fpr32(fp0, fs);
  7483 + tcg_gen_qemu_st32(fp0, t0, ctx->mem_idx);
  7484 + tcg_temp_free(fp0);
  7485 + }
6949 7486 opn = "swxc1";
6950 7487 store = 1;
6951 7488 break;
6952 7489 case OPC_SDXC1:
6953 7490 check_cop1x(ctx);
6954 7491 check_cp1_registers(ctx, fs);
6955   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6956   - tcg_gen_qemu_st64(fpu64_T[0], t0, ctx->mem_idx);
  7492 + {
  7493 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7494 +
  7495 + gen_load_fpr64(ctx, fp0, fs);
  7496 + tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
  7497 + tcg_temp_free(fp0);
  7498 + }
6957 7499 opn = "sdxc1";
6958 7500 store = 1;
6959 7501 break;
6960 7502 case OPC_SUXC1:
6961 7503 check_cp1_64bitmode(ctx);
6962   - gen_load_fpr64(ctx, fpu64_T[0], fs);
6963 7504 tcg_gen_andi_tl(t0, t0, ~0x7);
6964   - tcg_gen_qemu_st64(fpu64_T[0], t0, ctx->mem_idx);
  7505 + {
  7506 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7507 +
  7508 + gen_load_fpr64(ctx, fp0, fs);
  7509 + tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
  7510 + tcg_temp_free(fp0);
  7511 + }
6965 7512 opn = "suxc1";
6966 7513 store = 1;
6967 7514 break;
... ... @@ -6988,162 +7535,260 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
6988 7535 check_cp1_64bitmode(ctx);
6989 7536 {
6990 7537 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  7538 + TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
  7539 + TCGv fph0 = tcg_temp_local_new(TCG_TYPE_I32);
  7540 + TCGv fp1 = tcg_temp_local_new(TCG_TYPE_I32);
  7541 + TCGv fph1 = tcg_temp_local_new(TCG_TYPE_I32);
6991 7542 int l1 = gen_new_label();
6992 7543 int l2 = gen_new_label();
6993 7544  
6994 7545 gen_load_gpr(t0, fr);
6995 7546 tcg_gen_andi_tl(t0, t0, 0x7);
6996   - gen_load_fpr32(fpu32_T[0], fs);
6997   - gen_load_fpr32h(fpu32h_T[0], fs);
6998   - gen_load_fpr32(fpu32_T[1], ft);
6999   - gen_load_fpr32h(fpu32h_T[1], ft);
  7547 + gen_load_fpr32(fp0, fs);
  7548 + gen_load_fpr32h(fph0, fs);
  7549 + gen_load_fpr32(fp1, ft);
  7550 + gen_load_fpr32h(fph1, ft);
7000 7551  
7001 7552 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
7002   - tcg_gen_mov_i32(fpu32_T[2], fpu32_T[0]);
7003   - tcg_gen_mov_i32(fpu32h_T[2], fpu32h_T[0]);
  7553 + gen_store_fpr32(fp0, fd);
  7554 + gen_store_fpr32h(fph0, fd);
7004 7555 tcg_gen_br(l2);
7005 7556 gen_set_label(l1);
7006 7557 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
7007 7558 tcg_temp_free(t0);
7008 7559 #ifdef TARGET_WORDS_BIGENDIAN
7009   - tcg_gen_mov_i32(fpu32h_T[2], fpu32_T[0]);
7010   - tcg_gen_mov_i32(fpu32_T[2], fpu32h_T[1]);
  7560 + gen_store_fpr32(fph1, fd);
  7561 + gen_store_fpr32h(fp0, fd);
7011 7562 #else
7012   - tcg_gen_mov_i32(fpu32h_T[2], fpu32_T[1]);
7013   - tcg_gen_mov_i32(fpu32_T[2], fpu32h_T[0]);
  7563 + gen_store_fpr32(fph0, fd);
  7564 + gen_store_fpr32h(fp1, fd);
7014 7565 #endif
7015 7566 gen_set_label(l2);
  7567 + tcg_temp_free(fp0);
  7568 + tcg_temp_free(fph0);
  7569 + tcg_temp_free(fp1);
  7570 + tcg_temp_free(fph1);
7016 7571 }
7017   - gen_store_fpr32(fpu32_T[2], fd);
7018   - gen_store_fpr32h(fpu32h_T[2], fd);
7019 7572 opn = "alnv.ps";
7020 7573 break;
7021 7574 case OPC_MADD_S:
7022 7575 check_cop1x(ctx);
7023   - gen_load_fpr32(fpu32_T[0], fs);
7024   - gen_load_fpr32(fpu32_T[1], ft);
7025   - gen_load_fpr32(fpu32_T[2], fr);
7026   - tcg_gen_helper_0_0(do_float_muladd_s);
7027   - gen_store_fpr32(fpu32_T[2], fd);
  7576 + {
  7577 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  7578 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  7579 + TCGv fp2 = tcg_temp_new(TCG_TYPE_I32);
  7580 +
  7581 + gen_load_fpr32(fp0, fs);
  7582 + gen_load_fpr32(fp1, ft);
  7583 + gen_load_fpr32(fp2, fr);
  7584 + tcg_gen_helper_1_3(do_float_muladd_s, fp2, fp0, fp1, fp2);
  7585 + tcg_temp_free(fp0);
  7586 + tcg_temp_free(fp1);
  7587 + gen_store_fpr32(fp2, fd);
  7588 + tcg_temp_free(fp2);
  7589 + }
7028 7590 opn = "madd.s";
7029 7591 break;
7030 7592 case OPC_MADD_D:
7031 7593 check_cop1x(ctx);
7032 7594 check_cp1_registers(ctx, fd | fs | ft | fr);
7033   - gen_load_fpr64(ctx, fpu64_T[0], fs);
7034   - gen_load_fpr64(ctx, fpu64_T[1], ft);
7035   - gen_load_fpr64(ctx, fpu64_T[2], fr);
7036   - tcg_gen_helper_0_0(do_float_muladd_d);
7037   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  7595 + {
  7596 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7597 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7598 + TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
  7599 +
  7600 + gen_load_fpr64(ctx, fp0, fs);
  7601 + gen_load_fpr64(ctx, fp1, ft);
  7602 + gen_load_fpr64(ctx, fp2, fr);
  7603 + tcg_gen_helper_1_3(do_float_muladd_d, fp2, fp0, fp1, fp2);
  7604 + tcg_temp_free(fp0);
  7605 + tcg_temp_free(fp1);
  7606 + gen_store_fpr64(ctx, fp2, fd);
  7607 + tcg_temp_free(fp2);
  7608 + }
7038 7609 opn = "madd.d";
7039 7610 break;
7040 7611 case OPC_MADD_PS:
7041 7612 check_cp1_64bitmode(ctx);
7042   - gen_load_fpr32(fpu32_T[0], fs);
7043   - gen_load_fpr32h(fpu32h_T[0], fs);
7044   - gen_load_fpr32(fpu32_T[1], ft);
7045   - gen_load_fpr32h(fpu32h_T[1], ft);
7046   - gen_load_fpr32(fpu32_T[2], fr);
7047   - gen_load_fpr32h(fpu32h_T[2], fr);
7048   - tcg_gen_helper_0_0(do_float_muladd_ps);
7049   - gen_store_fpr32(fpu32_T[2], fd);
7050   - gen_store_fpr32h(fpu32h_T[2], fd);
  7613 + {
  7614 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7615 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7616 + TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
  7617 +
  7618 + gen_load_fpr64(ctx, fp0, fs);
  7619 + gen_load_fpr64(ctx, fp1, ft);
  7620 + gen_load_fpr64(ctx, fp2, fr);
  7621 + tcg_gen_helper_1_3(do_float_muladd_ps, fp2, fp0, fp1, fp2);
  7622 + tcg_temp_free(fp0);
  7623 + tcg_temp_free(fp1);
  7624 + gen_store_fpr64(ctx, fp2, fd);
  7625 + tcg_temp_free(fp2);
  7626 + }
7051 7627 opn = "madd.ps";
7052 7628 break;
7053 7629 case OPC_MSUB_S:
7054 7630 check_cop1x(ctx);
7055   - gen_load_fpr32(fpu32_T[0], fs);
7056   - gen_load_fpr32(fpu32_T[1], ft);
7057   - gen_load_fpr32(fpu32_T[2], fr);
7058   - tcg_gen_helper_0_0(do_float_mulsub_s);
7059   - gen_store_fpr32(fpu32_T[2], fd);
  7631 + {
  7632 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  7633 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  7634 + TCGv fp2 = tcg_temp_new(TCG_TYPE_I32);
  7635 +
  7636 + gen_load_fpr32(fp0, fs);
  7637 + gen_load_fpr32(fp1, ft);
  7638 + gen_load_fpr32(fp2, fr);
  7639 + tcg_gen_helper_1_3(do_float_mulsub_s, fp2, fp0, fp1, fp2);
  7640 + tcg_temp_free(fp0);
  7641 + tcg_temp_free(fp1);
  7642 + gen_store_fpr32(fp2, fd);
  7643 + tcg_temp_free(fp2);
  7644 + }
7060 7645 opn = "msub.s";
7061 7646 break;
7062 7647 case OPC_MSUB_D:
7063 7648 check_cop1x(ctx);
7064 7649 check_cp1_registers(ctx, fd | fs | ft | fr);
7065   - gen_load_fpr64(ctx, fpu64_T[0], fs);
7066   - gen_load_fpr64(ctx, fpu64_T[1], ft);
7067   - gen_load_fpr64(ctx, fpu64_T[2], fr);
7068   - tcg_gen_helper_0_0(do_float_mulsub_d);
7069   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  7650 + {
  7651 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7652 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7653 + TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
  7654 +
  7655 + gen_load_fpr64(ctx, fp0, fs);
  7656 + gen_load_fpr64(ctx, fp1, ft);
  7657 + gen_load_fpr64(ctx, fp2, fr);
  7658 + tcg_gen_helper_1_3(do_float_mulsub_d, fp2, fp0, fp1, fp2);
  7659 + tcg_temp_free(fp0);
  7660 + tcg_temp_free(fp1);
  7661 + gen_store_fpr64(ctx, fp2, fd);
  7662 + tcg_temp_free(fp2);
  7663 + }
7070 7664 opn = "msub.d";
7071 7665 break;
7072 7666 case OPC_MSUB_PS:
7073 7667 check_cp1_64bitmode(ctx);
7074   - gen_load_fpr32(fpu32_T[0], fs);
7075   - gen_load_fpr32h(fpu32h_T[0], fs);
7076   - gen_load_fpr32(fpu32_T[1], ft);
7077   - gen_load_fpr32h(fpu32h_T[1], ft);
7078   - gen_load_fpr32(fpu32_T[2], fr);
7079   - gen_load_fpr32h(fpu32h_T[2], fr);
7080   - tcg_gen_helper_0_0(do_float_mulsub_ps);
7081   - gen_store_fpr32(fpu32_T[2], fd);
7082   - gen_store_fpr32h(fpu32h_T[2], fd);
  7668 + {
  7669 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7670 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7671 + TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
  7672 +
  7673 + gen_load_fpr64(ctx, fp0, fs);
  7674 + gen_load_fpr64(ctx, fp1, ft);
  7675 + gen_load_fpr64(ctx, fp2, fr);
  7676 + tcg_gen_helper_1_3(do_float_mulsub_ps, fp2, fp0, fp1, fp2);
  7677 + tcg_temp_free(fp0);
  7678 + tcg_temp_free(fp1);
  7679 + gen_store_fpr64(ctx, fp2, fd);
  7680 + tcg_temp_free(fp2);
  7681 + }
7083 7682 opn = "msub.ps";
7084 7683 break;
7085 7684 case OPC_NMADD_S:
7086 7685 check_cop1x(ctx);
7087   - gen_load_fpr32(fpu32_T[0], fs);
7088   - gen_load_fpr32(fpu32_T[1], ft);
7089   - gen_load_fpr32(fpu32_T[2], fr);
7090   - tcg_gen_helper_0_0(do_float_nmuladd_s);
7091   - gen_store_fpr32(fpu32_T[2], fd);
  7686 + {
  7687 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  7688 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  7689 + TCGv fp2 = tcg_temp_new(TCG_TYPE_I32);
  7690 +
  7691 + gen_load_fpr32(fp0, fs);
  7692 + gen_load_fpr32(fp1, ft);
  7693 + gen_load_fpr32(fp2, fr);
  7694 + tcg_gen_helper_1_3(do_float_nmuladd_s, fp2, fp0, fp1, fp2);
  7695 + tcg_temp_free(fp0);
  7696 + tcg_temp_free(fp1);
  7697 + gen_store_fpr32(fp2, fd);
  7698 + tcg_temp_free(fp2);
  7699 + }
7092 7700 opn = "nmadd.s";
7093 7701 break;
7094 7702 case OPC_NMADD_D:
7095 7703 check_cop1x(ctx);
7096 7704 check_cp1_registers(ctx, fd | fs | ft | fr);
7097   - gen_load_fpr64(ctx, fpu64_T[0], fs);
7098   - gen_load_fpr64(ctx, fpu64_T[1], ft);
7099   - gen_load_fpr64(ctx, fpu64_T[2], fr);
7100   - tcg_gen_helper_0_0(do_float_nmuladd_d);
7101   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  7705 + {
  7706 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7707 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7708 + TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
  7709 +
  7710 + gen_load_fpr64(ctx, fp0, fs);
  7711 + gen_load_fpr64(ctx, fp1, ft);
  7712 + gen_load_fpr64(ctx, fp2, fr);
  7713 + tcg_gen_helper_1_3(do_float_nmuladd_d, fp2, fp0, fp1, fp2);
  7714 + tcg_temp_free(fp0);
  7715 + tcg_temp_free(fp1);
  7716 + gen_store_fpr64(ctx, fp2, fd);
  7717 + tcg_temp_free(fp2);
  7718 + }
7102 7719 opn = "nmadd.d";
7103 7720 break;
7104 7721 case OPC_NMADD_PS:
7105 7722 check_cp1_64bitmode(ctx);
7106   - gen_load_fpr32(fpu32_T[0], fs);
7107   - gen_load_fpr32h(fpu32h_T[0], fs);
7108   - gen_load_fpr32(fpu32_T[1], ft);
7109   - gen_load_fpr32h(fpu32h_T[1], ft);
7110   - gen_load_fpr32(fpu32_T[2], fr);
7111   - gen_load_fpr32h(fpu32h_T[2], fr);
7112   - tcg_gen_helper_0_0(do_float_nmuladd_ps);
7113   - gen_store_fpr32(fpu32_T[2], fd);
7114   - gen_store_fpr32h(fpu32h_T[2], fd);
  7723 + {
  7724 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7725 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7726 + TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
  7727 +
  7728 + gen_load_fpr64(ctx, fp0, fs);
  7729 + gen_load_fpr64(ctx, fp1, ft);
  7730 + gen_load_fpr64(ctx, fp2, fr);
  7731 + tcg_gen_helper_1_3(do_float_nmuladd_ps, fp2, fp0, fp1, fp2);
  7732 + tcg_temp_free(fp0);
  7733 + tcg_temp_free(fp1);
  7734 + gen_store_fpr64(ctx, fp2, fd);
  7735 + tcg_temp_free(fp2);
  7736 + }
7115 7737 opn = "nmadd.ps";
7116 7738 break;
7117 7739 case OPC_NMSUB_S:
7118 7740 check_cop1x(ctx);
7119   - gen_load_fpr32(fpu32_T[0], fs);
7120   - gen_load_fpr32(fpu32_T[1], ft);
7121   - gen_load_fpr32(fpu32_T[2], fr);
7122   - tcg_gen_helper_0_0(do_float_nmulsub_s);
7123   - gen_store_fpr32(fpu32_T[2], fd);
  7741 + {
  7742 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
  7743 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
  7744 + TCGv fp2 = tcg_temp_new(TCG_TYPE_I32);
  7745 +
  7746 + gen_load_fpr32(fp0, fs);
  7747 + gen_load_fpr32(fp1, ft);
  7748 + gen_load_fpr32(fp2, fr);
  7749 + tcg_gen_helper_1_3(do_float_nmulsub_s, fp2, fp0, fp1, fp2);
  7750 + tcg_temp_free(fp0);
  7751 + tcg_temp_free(fp1);
  7752 + gen_store_fpr32(fp2, fd);
  7753 + tcg_temp_free(fp2);
  7754 + }
7124 7755 opn = "nmsub.s";
7125 7756 break;
7126 7757 case OPC_NMSUB_D:
7127 7758 check_cop1x(ctx);
7128 7759 check_cp1_registers(ctx, fd | fs | ft | fr);
7129   - gen_load_fpr64(ctx, fpu64_T[0], fs);
7130   - gen_load_fpr64(ctx, fpu64_T[1], ft);
7131   - gen_load_fpr64(ctx, fpu64_T[2], fr);
7132   - tcg_gen_helper_0_0(do_float_nmulsub_d);
7133   - gen_store_fpr64(ctx, fpu64_T[2], fd);
  7760 + {
  7761 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7762 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7763 + TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
  7764 +
  7765 + gen_load_fpr64(ctx, fp0, fs);
  7766 + gen_load_fpr64(ctx, fp1, ft);
  7767 + gen_load_fpr64(ctx, fp2, fr);
  7768 + tcg_gen_helper_1_3(do_float_nmulsub_d, fp2, fp0, fp1, fp2);
  7769 + tcg_temp_free(fp0);
  7770 + tcg_temp_free(fp1);
  7771 + gen_store_fpr64(ctx, fp2, fd);
  7772 + tcg_temp_free(fp2);
  7773 + }
7134 7774 opn = "nmsub.d";
7135 7775 break;
7136 7776 case OPC_NMSUB_PS:
7137 7777 check_cp1_64bitmode(ctx);
7138   - gen_load_fpr32(fpu32_T[0], fs);
7139   - gen_load_fpr32h(fpu32h_T[0], fs);
7140   - gen_load_fpr32(fpu32_T[1], ft);
7141   - gen_load_fpr32h(fpu32h_T[1], ft);
7142   - gen_load_fpr32(fpu32_T[2], fr);
7143   - gen_load_fpr32h(fpu32h_T[2], fr);
7144   - tcg_gen_helper_0_0(do_float_nmulsub_ps);
7145   - gen_store_fpr32(fpu32_T[2], fd);
7146   - gen_store_fpr32h(fpu32h_T[2], fd);
  7778 + {
  7779 + TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
  7780 + TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
  7781 + TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
  7782 +
  7783 + gen_load_fpr64(ctx, fp0, fs);
  7784 + gen_load_fpr64(ctx, fp1, ft);
  7785 + gen_load_fpr64(ctx, fp2, fr);
  7786 + tcg_gen_helper_1_3(do_float_nmulsub_ps, fp2, fp0, fp1, fp2);
  7787 + tcg_temp_free(fp0);
  7788 + tcg_temp_free(fp1);
  7789 + gen_store_fpr64(ctx, fp2, fd);
  7790 + tcg_temp_free(fp2);
  7791 + }
7147 7792 opn = "nmsub.ps";
7148 7793 break;
7149 7794 default:
... ... @@ -7994,9 +8639,6 @@ void fpu_dump_state(CPUState *env, FILE *f,
7994 8639 fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
7995 8640 env->fpu->fcr0, env->fpu->fcr31, is_fpu64, env->fpu->fp_status,
7996 8641 get_float_exception_flags(&env->fpu->fp_status));
7997   - fpu_fprintf(f, "FT0: "); printfpr(&env->ft0);
7998   - fpu_fprintf(f, "FT1: "); printfpr(&env->ft1);
7999   - fpu_fprintf(f, "FT2: "); printfpr(&env->ft2);
8000 8642 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
8001 8643 fpu_fprintf(f, "%3s: ", fregnames[i]);
8002 8644 printfpr(&env->fpu->fpr[i]);
... ... @@ -8102,16 +8744,6 @@ static void mips_tcg_init(void)
8102 8744 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
8103 8745 #include "helper.h"
8104 8746  
8105   - fpu32_T[0] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, offsetof(CPUState, ft0.w[FP_ENDIAN_IDX]), "WT0");
8106   - fpu32_T[1] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, offsetof(CPUState, ft1.w[FP_ENDIAN_IDX]), "WT1");
8107   - fpu32_T[2] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, offsetof(CPUState, ft2.w[FP_ENDIAN_IDX]), "WT2");
8108   - fpu64_T[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, offsetof(CPUState, ft0.d), "DT0");
8109   - fpu64_T[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, offsetof(CPUState, ft1.d), "DT1");
8110   - fpu64_T[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, offsetof(CPUState, ft2.d), "DT2");
8111   - fpu32h_T[0] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, offsetof(CPUState, ft0.w[!FP_ENDIAN_IDX]), "WTH0");
8112   - fpu32h_T[1] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, offsetof(CPUState, ft1.w[!FP_ENDIAN_IDX]), "WTH1");
8113   - fpu32h_T[2] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, offsetof(CPUState, ft2.w[!FP_ENDIAN_IDX]), "WTH2");
8114   -
8115 8747 inited = 1;
8116 8748 }
8117 8749  
... ...