gwj / at91sam9263 · Commits

Commit b614106a170f77fc83ce9eb3ab0eb88379ee7161

Authored by aurel32
1 parent 43661a95

De-assert ISA PIC IRQs properly 

[ Taking latest isapc changes into account. ]

In case the PIC IRQ gets de-asserted on an isapc machine, we also have
to reset CPU_INTERRUPT_HARD. This is what older qemu (before the
routing-through-APIC changes) used to do as well.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5040 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 6 additions and 4 deletions
@@ -118,17 +118,19 @@ static void pic_irq_request(void *opaque, int irq, int level) @@ -118,17 +118,19 @@ static void pic_irq_request(void *opaque, int irq, int level)
118 { 118 {
119 CPUState *env = first_cpu; 119 CPUState *env = first_cpu;
120 120
121 - if (!level)  
122 - return;  
123 -  
124 if (env->apic_state) { 121 if (env->apic_state) {
  122 + if (!level)
  123 + return;
125 while (env) { 124 while (env) {
126 if (apic_accept_pic_intr(env)) 125 if (apic_accept_pic_intr(env))
127 apic_local_deliver(env, APIC_LINT0); 126 apic_local_deliver(env, APIC_LINT0);
128 env = env->next_cpu; 127 env = env->next_cpu;
129 } 128 }
130 } else { 129 } else {
131 - cpu_interrupt(env, CPU_INTERRUPT_HARD); 130 + if (level)
  131 + cpu_interrupt(env, CPU_INTERRUPT_HARD);
  132 + else
  133 + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
132 } 134 }
133 } 135 }
134 136