gwj / at91sam9263 · Commits

Commit b44c08fab34d35e19e4a58be1012ce0ce2740045

Authored by blueswir1
1 parent 8dea1dd4

Fix configuration 2 register (esp_2_cfg2.diff): 

According to http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt,
"Any bit pattern written to this register may be read back and should be identical"

Signed-off-by: Herve Poussineau <hpoussin@reactos.org>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5812 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 1 additions and 6 deletions
hw/esp.c
  View file @b44c08f
... ... @@ -144,8 +144,6 @@ struct ESPState {
144 144  
145 145 #define CFG1_RESREPT 0x40
146 146  
147   -#define CFG2_MASK 0x15
148   -
149 147 #define TCHI_FAS100A 0x4
150 148  
151 149 static void esp_raise_irq(ESPState *s)
... ... @@ -552,10 +550,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
552 550 break;
553 551 case ESP_WCCF ... ESP_WTEST:
554 552 break;
555   - case ESP_CFG2:
556   - s->rregs[saddr] = val & CFG2_MASK;
557   - break;
558   - case ESP_CFG3 ... ESP_RES4:
  553 + case ESP_CFG2 ... ESP_RES4:
559 554 s->rregs[saddr] = val;
560 555 break;
561 556 default:
... ...