Commit b3c7724cbc70109630227c92df2d59deca4dab64
1 parent
6913ba56
Move CPU save/load registration to common code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
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23 changed files
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21 additions
and
25 deletions
exec.c
@@ -37,6 +37,7 @@ | @@ -37,6 +37,7 @@ | ||
37 | #include "exec-all.h" | 37 | #include "exec-all.h" |
38 | #include "qemu-common.h" | 38 | #include "qemu-common.h" |
39 | #include "tcg.h" | 39 | #include "tcg.h" |
40 | +#include "hw/hw.h" | ||
40 | #if defined(CONFIG_USER_ONLY) | 41 | #if defined(CONFIG_USER_ONLY) |
41 | #include <qemu.h> | 42 | #include <qemu.h> |
42 | #endif | 43 | #endif |
@@ -457,6 +458,10 @@ void cpu_exec_init(CPUState *env) | @@ -457,6 +458,10 @@ void cpu_exec_init(CPUState *env) | ||
457 | env->cpu_index = cpu_index; | 458 | env->cpu_index = cpu_index; |
458 | env->nb_watchpoints = 0; | 459 | env->nb_watchpoints = 0; |
459 | *penv = env; | 460 | *penv = env; |
461 | +#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) | ||
462 | + register_savevm("cpu", cpu_index, CPU_SAVE_VERSION, | ||
463 | + cpu_save, cpu_load, env); | ||
464 | +#endif | ||
460 | } | 465 | } |
461 | 466 | ||
462 | static inline void invalidate_page_bitmap(PageDesc *p) | 467 | static inline void invalidate_page_bitmap(PageDesc *p) |
hw/etraxfs.c
@@ -67,7 +67,6 @@ void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size, | @@ -67,7 +67,6 @@ void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size, | ||
67 | cpu_model = "crisv32"; | 67 | cpu_model = "crisv32"; |
68 | } | 68 | } |
69 | env = cpu_init(cpu_model); | 69 | env = cpu_init(cpu_model); |
70 | - register_savevm("cpu", 0, 1, cpu_save, cpu_load, env); | ||
71 | qemu_register_reset(main_cpu_reset, env); | 70 | qemu_register_reset(main_cpu_reset, env); |
72 | 71 | ||
73 | /* allocate RAM */ | 72 | /* allocate RAM */ |
hw/mips_jazz.c
@@ -146,7 +146,6 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size, | @@ -146,7 +146,6 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size, | ||
146 | fprintf(stderr, "Unable to find CPU definition\n"); | 146 | fprintf(stderr, "Unable to find CPU definition\n"); |
147 | exit(1); | 147 | exit(1); |
148 | } | 148 | } |
149 | - register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); | ||
150 | qemu_register_reset(main_cpu_reset, env); | 149 | qemu_register_reset(main_cpu_reset, env); |
151 | 150 | ||
152 | /* allocate RAM */ | 151 | /* allocate RAM */ |
hw/mips_malta.c
@@ -802,7 +802,6 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size, | @@ -802,7 +802,6 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size, | ||
802 | fprintf(stderr, "Unable to find CPU definition\n"); | 802 | fprintf(stderr, "Unable to find CPU definition\n"); |
803 | exit(1); | 803 | exit(1); |
804 | } | 804 | } |
805 | - register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); | ||
806 | qemu_register_reset(main_cpu_reset, env); | 805 | qemu_register_reset(main_cpu_reset, env); |
807 | 806 | ||
808 | /* allocate RAM */ | 807 | /* allocate RAM */ |
hw/mips_mipssim.c
@@ -129,7 +129,6 @@ mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size, | @@ -129,7 +129,6 @@ mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size, | ||
129 | fprintf(stderr, "Unable to find CPU definition\n"); | 129 | fprintf(stderr, "Unable to find CPU definition\n"); |
130 | exit(1); | 130 | exit(1); |
131 | } | 131 | } |
132 | - register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); | ||
133 | qemu_register_reset(main_cpu_reset, env); | 132 | qemu_register_reset(main_cpu_reset, env); |
134 | 133 | ||
135 | /* Allocate RAM. */ | 134 | /* Allocate RAM. */ |
hw/mips_r4k.c
@@ -175,7 +175,6 @@ void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size, | @@ -175,7 +175,6 @@ void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size, | ||
175 | fprintf(stderr, "Unable to find CPU definition\n"); | 175 | fprintf(stderr, "Unable to find CPU definition\n"); |
176 | exit(1); | 176 | exit(1); |
177 | } | 177 | } |
178 | - register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); | ||
179 | qemu_register_reset(main_cpu_reset, env); | 178 | qemu_register_reset(main_cpu_reset, env); |
180 | 179 | ||
181 | /* allocate RAM */ | 180 | /* allocate RAM */ |
hw/pc.c
@@ -764,7 +764,6 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size, | @@ -764,7 +764,6 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size, | ||
764 | /* XXX: enable it in all cases */ | 764 | /* XXX: enable it in all cases */ |
765 | env->cpuid_features |= CPUID_APIC; | 765 | env->cpuid_features |= CPUID_APIC; |
766 | } | 766 | } |
767 | - register_savevm("cpu", i, 5, cpu_save, cpu_load, env); | ||
768 | qemu_register_reset(main_cpu_reset, env); | 767 | qemu_register_reset(main_cpu_reset, env); |
769 | if (pci_enabled) { | 768 | if (pci_enabled) { |
770 | apic_init(env); | 769 | apic_init(env); |
hw/ppc4xx_devs.c
@@ -56,7 +56,6 @@ CPUState *ppc4xx_init (const unsigned char *cpu_model, | @@ -56,7 +56,6 @@ CPUState *ppc4xx_init (const unsigned char *cpu_model, | ||
56 | ppc_dcr_init(env, NULL, NULL); | 56 | ppc_dcr_init(env, NULL, NULL); |
57 | /* Register qemu callbacks */ | 57 | /* Register qemu callbacks */ |
58 | qemu_register_reset(&cpu_ppc_reset, env); | 58 | qemu_register_reset(&cpu_ppc_reset, env); |
59 | - register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); | ||
60 | 59 | ||
61 | return env; | 60 | return env; |
62 | } | 61 | } |
hw/ppc_chrp.c
@@ -103,7 +103,6 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size, | @@ -103,7 +103,6 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size, | ||
103 | env->osi_call = vga_osi_call; | 103 | env->osi_call = vga_osi_call; |
104 | #endif | 104 | #endif |
105 | qemu_register_reset(&cpu_ppc_reset, env); | 105 | qemu_register_reset(&cpu_ppc_reset, env); |
106 | - register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); | ||
107 | envs[i] = env; | 106 | envs[i] = env; |
108 | } | 107 | } |
109 | if (env->nip < 0xFFF80000) { | 108 | if (env->nip < 0xFFF80000) { |
hw/ppc_oldworld.c
@@ -143,7 +143,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size, | @@ -143,7 +143,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size, | ||
143 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | 143 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
144 | env->osi_call = vga_osi_call; | 144 | env->osi_call = vga_osi_call; |
145 | qemu_register_reset(&cpu_ppc_reset, env); | 145 | qemu_register_reset(&cpu_ppc_reset, env); |
146 | - register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); | ||
147 | envs[i] = env; | 146 | envs[i] = env; |
148 | } | 147 | } |
149 | if (env->nip < 0xFFF80000) { | 148 | if (env->nip < 0xFFF80000) { |
hw/ppc_prep.c
@@ -580,7 +580,6 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size, | @@ -580,7 +580,6 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size, | ||
580 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | 580 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
581 | } | 581 | } |
582 | qemu_register_reset(&cpu_ppc_reset, env); | 582 | qemu_register_reset(&cpu_ppc_reset, env); |
583 | - register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); | ||
584 | envs[i] = env; | 583 | envs[i] = env; |
585 | } | 584 | } |
586 | 585 |
hw/pxa2xx.c
@@ -2046,9 +2046,6 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, | @@ -2046,9 +2046,6 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, | ||
2046 | fprintf(stderr, "Unable to find CPU definition\n"); | 2046 | fprintf(stderr, "Unable to find CPU definition\n"); |
2047 | exit(1); | 2047 | exit(1); |
2048 | } | 2048 | } |
2049 | - register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load, | ||
2050 | - s->env); | ||
2051 | - | ||
2052 | s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; | 2049 | s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; |
2053 | 2050 | ||
2054 | /* SDRAM & Internal Memory Storage */ | 2051 | /* SDRAM & Internal Memory Storage */ |
@@ -2173,9 +2170,6 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, | @@ -2173,9 +2170,6 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, | ||
2173 | fprintf(stderr, "Unable to find CPU definition\n"); | 2170 | fprintf(stderr, "Unable to find CPU definition\n"); |
2174 | exit(1); | 2171 | exit(1); |
2175 | } | 2172 | } |
2176 | - register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load, | ||
2177 | - s->env); | ||
2178 | - | ||
2179 | s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; | 2173 | s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; |
2180 | 2174 | ||
2181 | /* SDRAM & Internal Memory Storage */ | 2175 | /* SDRAM & Internal Memory Storage */ |
hw/sun4m.c
@@ -426,7 +426,6 @@ static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, | @@ -426,7 +426,6 @@ static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, | ||
426 | qemu_register_reset(secondary_cpu_reset, env); | 426 | qemu_register_reset(secondary_cpu_reset, env); |
427 | env->halted = 1; | 427 | env->halted = 1; |
428 | } | 428 | } |
429 | - register_savevm("cpu", i, 4, cpu_save, cpu_load, env); | ||
430 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); | 429 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
431 | env->prom_addr = hwdef->slavio_base; | 430 | env->prom_addr = hwdef->slavio_base; |
432 | } | 431 | } |
@@ -601,7 +600,6 @@ static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, | @@ -601,7 +600,6 @@ static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, | ||
601 | cpu_sparc_set_id(env, 0); | 600 | cpu_sparc_set_id(env, 0); |
602 | 601 | ||
603 | qemu_register_reset(main_cpu_reset, env); | 602 | qemu_register_reset(main_cpu_reset, env); |
604 | - register_savevm("cpu", 0, 4, cpu_save, cpu_load, env); | ||
605 | cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); | 603 | cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
606 | env->prom_addr = hwdef->slavio_base; | 604 | env->prom_addr = hwdef->slavio_base; |
607 | 605 | ||
@@ -1413,7 +1411,6 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, | @@ -1413,7 +1411,6 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, | ||
1413 | qemu_register_reset(secondary_cpu_reset, env); | 1411 | qemu_register_reset(secondary_cpu_reset, env); |
1414 | env->halted = 1; | 1412 | env->halted = 1; |
1415 | } | 1413 | } |
1416 | - register_savevm("cpu", i, 4, cpu_save, cpu_load, env); | ||
1417 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); | 1414 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
1418 | env->prom_addr = hwdef->slavio_base; | 1415 | env->prom_addr = hwdef->slavio_base; |
1419 | } | 1416 | } |
hw/sun4u.c
@@ -282,7 +282,6 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, | @@ -282,7 +282,6 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, | ||
282 | bh = qemu_bh_new(hstick_irq, env); | 282 | bh = qemu_bh_new(hstick_irq, env); |
283 | env->hstick = ptimer_init(bh); | 283 | env->hstick = ptimer_init(bh); |
284 | ptimer_set_period(env->hstick, 1ULL); | 284 | ptimer_set_period(env->hstick, 1ULL); |
285 | - register_savevm("cpu", 0, 4, cpu_save, cpu_load, env); | ||
286 | qemu_register_reset(main_cpu_reset, env); | 285 | qemu_register_reset(main_cpu_reset, env); |
287 | main_cpu_reset(env); | 286 | main_cpu_reset(env); |
288 | 287 |
qemu-common.h
@@ -132,4 +132,8 @@ typedef struct SerialState SerialState; | @@ -132,4 +132,8 @@ typedef struct SerialState SerialState; | ||
132 | typedef struct IRQState *qemu_irq; | 132 | typedef struct IRQState *qemu_irq; |
133 | struct pcmcia_card_s; | 133 | struct pcmcia_card_s; |
134 | 134 | ||
135 | +/* CPU save/load. */ | ||
136 | +void cpu_save(QEMUFile *f, void *opaque); | ||
137 | +int cpu_load(QEMUFile *f, void *opaque, int version_id); | ||
138 | + | ||
135 | #endif | 139 | #endif |
sysemu.h
@@ -41,9 +41,6 @@ void qemu_system_powerdown(void); | @@ -41,9 +41,6 @@ void qemu_system_powerdown(void); | ||
41 | #endif | 41 | #endif |
42 | void qemu_system_reset(void); | 42 | void qemu_system_reset(void); |
43 | 43 | ||
44 | -void cpu_save(QEMUFile *f, void *opaque); | ||
45 | -int cpu_load(QEMUFile *f, void *opaque, int version_id); | ||
46 | - | ||
47 | void do_savevm(const char *name); | 44 | void do_savevm(const char *name); |
48 | void do_loadvm(const char *name); | 45 | void do_loadvm(const char *name); |
49 | void do_delvm(const char *name); | 46 | void do_delvm(const char *name); |
target-arm/cpu.h
@@ -397,7 +397,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, | @@ -397,7 +397,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, | ||
397 | #define cpu_signal_handler cpu_arm_signal_handler | 397 | #define cpu_signal_handler cpu_arm_signal_handler |
398 | #define cpu_list arm_cpu_list | 398 | #define cpu_list arm_cpu_list |
399 | 399 | ||
400 | -#define ARM_CPU_SAVE_VERSION 1 | 400 | +#define CPU_SAVE_VERSION 1 |
401 | 401 | ||
402 | /* MMU modes definitions */ | 402 | /* MMU modes definitions */ |
403 | #define MMU_MODE0_SUFFIX _kernel | 403 | #define MMU_MODE0_SUFFIX _kernel |
target-arm/machine.c
@@ -120,7 +120,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) | @@ -120,7 +120,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) | ||
120 | CPUARMState *env = (CPUARMState *)opaque; | 120 | CPUARMState *env = (CPUARMState *)opaque; |
121 | int i; | 121 | int i; |
122 | 122 | ||
123 | - if (version_id != ARM_CPU_SAVE_VERSION) | 123 | + if (version_id != CPU_SAVE_VERSION) |
124 | return -EINVAL; | 124 | return -EINVAL; |
125 | 125 | ||
126 | for (i = 0; i < 16; i++) { | 126 | for (i = 0; i < 16; i++) { |
target-cris/cpu.h
@@ -210,6 +210,8 @@ enum { | @@ -210,6 +210,8 @@ enum { | ||
210 | #define cpu_gen_code cpu_cris_gen_code | 210 | #define cpu_gen_code cpu_cris_gen_code |
211 | #define cpu_signal_handler cpu_cris_signal_handler | 211 | #define cpu_signal_handler cpu_cris_signal_handler |
212 | 212 | ||
213 | +#define CPU_SAVE_VERSION 1 | ||
214 | + | ||
213 | /* MMU modes definitions */ | 215 | /* MMU modes definitions */ |
214 | #define MMU_MODE0_SUFFIX _kernel | 216 | #define MMU_MODE0_SUFFIX _kernel |
215 | #define MMU_MODE1_SUFFIX _user | 217 | #define MMU_MODE1_SUFFIX _user |
target-i386/cpu.h
@@ -726,6 +726,8 @@ static inline int cpu_get_time_fast(void) | @@ -726,6 +726,8 @@ static inline int cpu_get_time_fast(void) | ||
726 | #define cpu_signal_handler cpu_x86_signal_handler | 726 | #define cpu_signal_handler cpu_x86_signal_handler |
727 | #define cpu_list x86_cpu_list | 727 | #define cpu_list x86_cpu_list |
728 | 728 | ||
729 | +#define CPU_SAVE_VERSION 5 | ||
730 | + | ||
729 | /* MMU modes definitions */ | 731 | /* MMU modes definitions */ |
730 | #define MMU_MODE0_SUFFIX _kernel | 732 | #define MMU_MODE0_SUFFIX _kernel |
731 | #define MMU_MODE1_SUFFIX _user | 733 | #define MMU_MODE1_SUFFIX _user |
target-mips/cpu.h
@@ -489,6 +489,8 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, | @@ -489,6 +489,8 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, | ||
489 | #define cpu_signal_handler cpu_mips_signal_handler | 489 | #define cpu_signal_handler cpu_mips_signal_handler |
490 | #define cpu_list mips_cpu_list | 490 | #define cpu_list mips_cpu_list |
491 | 491 | ||
492 | +#define CPU_SAVE_VERSION 3 | ||
493 | + | ||
492 | /* MMU modes definitions. We carefully match the indices with our | 494 | /* MMU modes definitions. We carefully match the indices with our |
493 | hflags layout. */ | 495 | hflags layout. */ |
494 | #define MMU_MODE0_SUFFIX _kernel | 496 | #define MMU_MODE0_SUFFIX _kernel |
target-ppc/cpu.h
@@ -813,6 +813,8 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); | @@ -813,6 +813,8 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); | ||
813 | #define cpu_signal_handler cpu_ppc_signal_handler | 813 | #define cpu_signal_handler cpu_ppc_signal_handler |
814 | #define cpu_list ppc_cpu_list | 814 | #define cpu_list ppc_cpu_list |
815 | 815 | ||
816 | +#define CPU_SAVE_VERSION 3 | ||
817 | + | ||
816 | /* MMU modes definitions */ | 818 | /* MMU modes definitions */ |
817 | #define MMU_MODE0_SUFFIX _user | 819 | #define MMU_MODE0_SUFFIX _user |
818 | #define MMU_MODE1_SUFFIX _kernel | 820 | #define MMU_MODE1_SUFFIX _kernel |
target-sparc/cpu.h
@@ -388,6 +388,8 @@ void cpu_check_irqs(CPUSPARCState *env); | @@ -388,6 +388,8 @@ void cpu_check_irqs(CPUSPARCState *env); | ||
388 | #define cpu_signal_handler cpu_sparc_signal_handler | 388 | #define cpu_signal_handler cpu_sparc_signal_handler |
389 | #define cpu_list sparc_cpu_list | 389 | #define cpu_list sparc_cpu_list |
390 | 390 | ||
391 | +#define CPU_SAVE_VERSION 4 | ||
392 | + | ||
391 | /* MMU modes definitions */ | 393 | /* MMU modes definitions */ |
392 | #define MMU_MODE0_SUFFIX _user | 394 | #define MMU_MODE0_SUFFIX _user |
393 | #define MMU_MODE1_SUFFIX _kernel | 395 | #define MMU_MODE1_SUFFIX _kernel |