gwj / at91sam9263 · Commits

Commit b2fa17977f3e9b7ced2cbbe14f6d3c4b3e8e314e

Authored by pbrook
1 parent 83c1f87c

Fix ARMv6 translation table base address calculation. 

Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5514 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 23 additions and 22 deletions
target-arm/cpu.h
  View file @b2fa179
@@ -107,7 +107,9 @@ typedef struct CPUARMState { @@ -107,7 +107,9 @@ typedef struct CPUARMState {
107 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 107 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
108 uint32_t c2_base0; /* MMU translation table base 0. */ 108 uint32_t c2_base0; /* MMU translation table base 0. */
109 uint32_t c2_base1; /* MMU translation table base 1. */ 109 uint32_t c2_base1; /* MMU translation table base 1. */
110 - uint32_t c2_mask; /* MMU translation table base mask. */ 110 + uint32_t c2_control; /* MMU translation table base control. */
  111 + uint32_t c2_mask; /* MMU translation table base selection mask. */
  112 + uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
111 uint32_t c2_data; /* MPU data cachable bits. */ 113 uint32_t c2_data; /* MPU data cachable bits. */
112 uint32_t c2_insn; /* MPU instruction cachable bits. */ 114 uint32_t c2_insn; /* MPU instruction cachable bits. */
113 uint32_t c3; /* MMU domain access control register 115 uint32_t c3; /* MMU domain access control register
target-arm/helper.c
  View file @b2fa179
@@ -168,6 +168,7 @@ void cpu_reset(CPUARMState *env) @@ -168,6 +168,7 @@ void cpu_reset(CPUARMState *env)
168 if (IS_M(env)) 168 if (IS_M(env))
169 env->uncached_cpsr &= ~CPSR_I; 169 env->uncached_cpsr &= ~CPSR_I;
170 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 170 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
  171 + env->cp15.c2_base_mask = 0xffffc000u;
171 #endif 172 #endif
172 env->regs[15] = 0; 173 env->regs[15] = 0;
173 tlb_flush(env, 1); 174 tlb_flush(env, 1);
@@ -910,6 +911,19 @@ static inline int check_ap(CPUState *env, int ap, int domain, int access_type, @@ -910,6 +911,19 @@ static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
910 } 911 }
911 } 912 }
912 913
  914 +static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
  915 +{
  916 + uint32_t table;
  917 +
  918 + if (address & env->cp15.c2_mask)
  919 + table = env->cp15.c2_base1 & 0xffffc000;
  920 + else
  921 + table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
  922 +
  923 + table |= (address >> 18) & 0x3ffc;
  924 + return table;
  925 +}
  926 +
913 static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type, 927 static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
914 int is_user, uint32_t *phys_ptr, int *prot) 928 int is_user, uint32_t *phys_ptr, int *prot)
915 { 929 {
@@ -923,11 +937,7 @@ static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type, @@ -923,11 +937,7 @@ static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
923 937
924 /* Pagetable walk. */ 938 /* Pagetable walk. */
925 /* Lookup l1 descriptor. */ 939 /* Lookup l1 descriptor. */
926 - if (address & env->cp15.c2_mask)  
927 - table = env->cp15.c2_base1;  
928 - else  
929 - table = env->cp15.c2_base0;  
930 - table = (table & 0xffffc000) | ((address >> 18) & 0x3ffc); 940 + table = get_level1_table_address(env, address);
931 desc = ldl_phys(table); 941 desc = ldl_phys(table);
932 type = (desc & 3); 942 type = (desc & 3);
933 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3; 943 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
@@ -1015,11 +1025,7 @@ static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type, @@ -1015,11 +1025,7 @@ static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
1015 1025
1016 /* Pagetable walk. */ 1026 /* Pagetable walk. */
1017 /* Lookup l1 descriptor. */ 1027 /* Lookup l1 descriptor. */
1018 - if (address & env->cp15.c2_mask)  
1019 - table = env->cp15.c2_base1;  
1020 - else  
1021 - table = env->cp15.c2_base0;  
1022 - table = (table & 0xffffc000) | ((address >> 18) & 0x3ffc); 1028 + table = get_level1_table_address(env, address);
1023 desc = ldl_phys(table); 1029 desc = ldl_phys(table);
1024 type = (desc & 3); 1030 type = (desc & 3);
1025 if (type == 0) { 1031 if (type == 0) {
@@ -1365,7 +1371,10 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) @@ -1365,7 +1371,10 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
1365 env->cp15.c2_base1 = val; 1371 env->cp15.c2_base1 = val;
1366 break; 1372 break;
1367 case 2: 1373 case 2:
  1374 + val &= 7;
  1375 + env->cp15.c2_control = val;
1368 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val); 1376 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
  1377 + env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
1369 break; 1378 break;
1370 default: 1379 default:
1371 goto bad_reg; 1380 goto bad_reg;
@@ -1683,17 +1692,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) @@ -1683,17 +1692,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
1683 case 1: 1692 case 1:
1684 return env->cp15.c2_base1; 1693 return env->cp15.c2_base1;
1685 case 2: 1694 case 2:
1686 - {  
1687 - int n;  
1688 - uint32_t mask;  
1689 - n = 0;  
1690 - mask = env->cp15.c2_mask;  
1691 - while (mask) {  
1692 - n++;  
1693 - mask <<= 1;  
1694 - }  
1695 - return n;  
1696 - } 1695 + return env->cp15.c2_control;
1697 default: 1696 default:
1698 goto bad_reg; 1697 goto bad_reg;
1699 } 1698 }