Commit b12363e1b7d7454daa21c861290f49de42c2ea71
1 parent
6e35d524
target-ppc: remove FPRF optimization
FPRF optimization is totally broken, remove it. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6033 c046a42c-6fe2-441c-8c8c-71466251a162
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29 deletions
target-ppc/translate.c
@@ -41,7 +41,6 @@ | @@ -41,7 +41,6 @@ | ||
41 | //#define DO_SINGLE_STEP | 41 | //#define DO_SINGLE_STEP |
42 | //#define PPC_DEBUG_DISAS | 42 | //#define PPC_DEBUG_DISAS |
43 | //#define DO_PPC_STATISTICS | 43 | //#define DO_PPC_STATISTICS |
44 | -//#define OPTIMIZE_FPRF_UPDATE | ||
45 | 44 | ||
46 | /*****************************************************************************/ | 45 | /*****************************************************************************/ |
47 | /* Code translation helpers */ | 46 | /* Code translation helpers */ |
@@ -162,11 +161,6 @@ void ppc_translate_init(void) | @@ -162,11 +161,6 @@ void ppc_translate_init(void) | ||
162 | done_init = 1; | 161 | done_init = 1; |
163 | } | 162 | } |
164 | 163 | ||
165 | -#if defined(OPTIMIZE_FPRF_UPDATE) | ||
166 | -static uint16_t *gen_fprf_buf[OPC_BUF_SIZE]; | ||
167 | -static uint16_t **gen_fprf_ptr; | ||
168 | -#endif | ||
169 | - | ||
170 | /* internal defines */ | 164 | /* internal defines */ |
171 | typedef struct DisasContext { | 165 | typedef struct DisasContext { |
172 | struct TranslationBlock *tb; | 166 | struct TranslationBlock *tb; |
@@ -216,9 +210,6 @@ static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_ | @@ -216,9 +210,6 @@ static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_ | ||
216 | 210 | ||
217 | if (set_fprf != 0) { | 211 | if (set_fprf != 0) { |
218 | /* This case might be optimized later */ | 212 | /* This case might be optimized later */ |
219 | -#if defined(OPTIMIZE_FPRF_UPDATE) | ||
220 | - *gen_fprf_ptr++ = gen_opc_ptr; | ||
221 | -#endif | ||
222 | tcg_gen_movi_i32(t0, 1); | 213 | tcg_gen_movi_i32(t0, 1); |
223 | gen_helper_compute_fprf(t0, arg, t0); | 214 | gen_helper_compute_fprf(t0, arg, t0); |
224 | if (unlikely(set_rc)) { | 215 | if (unlikely(set_rc)) { |
@@ -235,17 +226,6 @@ static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_ | @@ -235,17 +226,6 @@ static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_ | ||
235 | tcg_temp_free_i32(t0); | 226 | tcg_temp_free_i32(t0); |
236 | } | 227 | } |
237 | 228 | ||
238 | -static always_inline void gen_optimize_fprf (void) | ||
239 | -{ | ||
240 | -#if defined(OPTIMIZE_FPRF_UPDATE) | ||
241 | - uint16_t **ptr; | ||
242 | - | ||
243 | - for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++) | ||
244 | - *ptr = INDEX_op_nop1; | ||
245 | - gen_fprf_ptr = gen_fprf_buf; | ||
246 | -#endif | ||
247 | -} | ||
248 | - | ||
249 | static always_inline void gen_set_access_type (DisasContext *ctx, int access_type) | 229 | static always_inline void gen_set_access_type (DisasContext *ctx, int access_type) |
250 | { | 230 | { |
251 | if (ctx->access_type != access_type) { | 231 | if (ctx->access_type != access_type) { |
@@ -2326,7 +2306,6 @@ GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT) | @@ -2326,7 +2306,6 @@ GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT) | ||
2326 | gen_exception(ctx, POWERPC_EXCP_FPU); | 2306 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2327 | return; | 2307 | return; |
2328 | } | 2308 | } |
2329 | - gen_optimize_fprf(); | ||
2330 | bfa = 4 * (7 - crfS(ctx->opcode)); | 2309 | bfa = 4 * (7 - crfS(ctx->opcode)); |
2331 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa); | 2310 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa); |
2332 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); | 2311 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); |
@@ -2340,7 +2319,6 @@ GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT) | @@ -2340,7 +2319,6 @@ GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT) | ||
2340 | gen_exception(ctx, POWERPC_EXCP_FPU); | 2319 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2341 | return; | 2320 | return; |
2342 | } | 2321 | } |
2343 | - gen_optimize_fprf(); | ||
2344 | gen_reset_fpstatus(); | 2322 | gen_reset_fpstatus(); |
2345 | tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); | 2323 | tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
2346 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | 2324 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
@@ -2356,7 +2334,6 @@ GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT) | @@ -2356,7 +2334,6 @@ GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT) | ||
2356 | return; | 2334 | return; |
2357 | } | 2335 | } |
2358 | crb = 31 - crbD(ctx->opcode); | 2336 | crb = 31 - crbD(ctx->opcode); |
2359 | - gen_optimize_fprf(); | ||
2360 | gen_reset_fpstatus(); | 2337 | gen_reset_fpstatus(); |
2361 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { | 2338 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { |
2362 | TCGv_i32 t0 = tcg_const_i32(crb); | 2339 | TCGv_i32 t0 = tcg_const_i32(crb); |
@@ -2378,7 +2355,6 @@ GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT) | @@ -2378,7 +2355,6 @@ GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT) | ||
2378 | return; | 2355 | return; |
2379 | } | 2356 | } |
2380 | crb = 31 - crbD(ctx->opcode); | 2357 | crb = 31 - crbD(ctx->opcode); |
2381 | - gen_optimize_fprf(); | ||
2382 | gen_reset_fpstatus(); | 2358 | gen_reset_fpstatus(); |
2383 | /* XXX: we pretend we can only do IEEE floating-point computations */ | 2359 | /* XXX: we pretend we can only do IEEE floating-point computations */ |
2384 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { | 2360 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
@@ -2402,7 +2378,6 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) | @@ -2402,7 +2378,6 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) | ||
2402 | gen_exception(ctx, POWERPC_EXCP_FPU); | 2378 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2403 | return; | 2379 | return; |
2404 | } | 2380 | } |
2405 | - gen_optimize_fprf(); | ||
2406 | gen_reset_fpstatus(); | 2381 | gen_reset_fpstatus(); |
2407 | t0 = tcg_const_i32(FM(ctx->opcode)); | 2382 | t0 = tcg_const_i32(FM(ctx->opcode)); |
2408 | gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0); | 2383 | gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0); |
@@ -2427,7 +2402,6 @@ GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) | @@ -2427,7 +2402,6 @@ GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) | ||
2427 | } | 2402 | } |
2428 | bf = crbD(ctx->opcode) >> 2; | 2403 | bf = crbD(ctx->opcode) >> 2; |
2429 | sh = 7 - bf; | 2404 | sh = 7 - bf; |
2430 | - gen_optimize_fprf(); | ||
2431 | gen_reset_fpstatus(); | 2405 | gen_reset_fpstatus(); |
2432 | t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh)); | 2406 | t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh)); |
2433 | t1 = tcg_const_i32(1 << sh); | 2407 | t1 = tcg_const_i32(1 << sh); |
@@ -7727,9 +7701,6 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, | @@ -7727,9 +7701,6 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, | ||
7727 | 7701 | ||
7728 | pc_start = tb->pc; | 7702 | pc_start = tb->pc; |
7729 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; | 7703 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
7730 | -#if defined(OPTIMIZE_FPRF_UPDATE) | ||
7731 | - gen_fprf_ptr = gen_fprf_buf; | ||
7732 | -#endif | ||
7733 | ctx.nip = pc_start; | 7704 | ctx.nip = pc_start; |
7734 | ctx.tb = tb; | 7705 | ctx.tb = tb; |
7735 | ctx.exception = POWERPC_EXCP_NONE; | 7706 | ctx.exception = POWERPC_EXCP_NONE; |