gwj / at91sam9263 · Commits

Commit b0a21b5334fb31042d555bfb66de864291c53140

Authored by bellard
1 parent dff38e7b

use new timer API 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@689 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 6 changed files with 330 additions and 80 deletions
hw/i8254.c
  View file @b0a21b5
... ... @@ -43,6 +43,8 @@
43 43 #include "cpu.h"
44 44 #include "vl.h"
45 45  
  46 +//#define DEBUG_PIT
  47 +
46 48 #define RW_STATE_LSB 0
47 49 #define RW_STATE_MSB 1
48 50 #define RW_STATE_WORD0 2
... ... @@ -52,12 +54,14 @@
52 54  
53 55 PITChannelState pit_channels[3];
54 56  
  57 +static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
  58 +
55 59 static int pit_get_count(PITChannelState *s)
56 60 {
57 61 uint64_t d;
58 62 int counter;
59 63  
60   - d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
  64 + d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec);
61 65 switch(s->mode) {
62 66 case 0:
63 67 case 1:
... ... @@ -77,12 +81,12 @@ static int pit_get_count(PITChannelState *s)
77 81 }
78 82  
79 83 /* get pit output bit */
80   -int pit_get_out(PITChannelState *s)
  84 +int pit_get_out(PITChannelState *s, int64_t current_time)
81 85 {
82 86 uint64_t d;
83 87 int out;
84 88  
85   - d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
  89 + d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
86 90 switch(s->mode) {
87 91 default:
88 92 case 0:
... ... @@ -108,53 +112,51 @@ int pit_get_out(PITChannelState *s)
108 112 return out;
109 113 }
110 114  
111   -/* get the number of 0 to 1 transitions we had since we call this
112   - function */
113   -/* XXX: maybe better to use ticks precision to avoid getting edges
114   - twice if checks are done at very small intervals */
115   -int pit_get_out_edges(PITChannelState *s)
  115 +/* return -1 if no transition will occur. */
  116 +static int64_t pit_get_next_transition_time(PITChannelState *s,
  117 + int64_t current_time)
116 118 {
117   - uint64_t d1, d2;
118   - int64_t ticks;
119   - int ret, v;
  119 + uint64_t d, next_time, base;
  120 + int period2;
120 121  
121   - ticks = cpu_get_ticks();
122   - d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
123   - PIT_FREQ, ticks_per_sec);
124   - d2 = muldiv64(ticks - s->count_load_time,
125   - PIT_FREQ, ticks_per_sec);
126   - s->count_last_edge_check_time = ticks;
  122 + d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
127 123 switch(s->mode) {
128 124 default:
129 125 case 0:
130   - if (d1 < s->count && d2 >= s->count)
131   - ret = 1;
132   - else
133   - ret = 0;
134   - break;
135 126 case 1:
136   - ret = 0;
  127 + if (d < s->count)
  128 + next_time = s->count;
  129 + else
  130 + return -1;
137 131 break;
138 132 case 2:
139   - d1 /= s->count;
140   - d2 /= s->count;
141   - ret = d2 - d1;
  133 + base = (d / s->count) * s->count;
  134 + if ((d - base) == 0 && d != 0)
  135 + next_time = base + s->count;
  136 + else
  137 + next_time = base + s->count + 1;
142 138 break;
143 139 case 3:
144   - v = s->count - ((s->count + 1) >> 1);
145   - d1 = (d1 + v) / s->count;
146   - d2 = (d2 + v) / s->count;
147   - ret = d2 - d1;
  140 + base = (d / s->count) * s->count;
  141 + period2 = ((s->count + 1) >> 1);
  142 + if ((d - base) < period2)
  143 + next_time = base + period2;
  144 + else
  145 + next_time = base + s->count;
148 146 break;
149 147 case 4:
150 148 case 5:
151   - if (d1 < s->count && d2 >= s->count)
152   - ret = 1;
  149 + if (d < s->count)
  150 + next_time = s->count;
  151 + else if (d == s->count)
  152 + next_time = s->count + 1;
153 153 else
154   - ret = 0;
  154 + return -1;
155 155 break;
156 156 }
157   - return ret;
  157 + /* convert to timer units */
  158 + next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ);
  159 + return next_time;
158 160 }
159 161  
160 162 /* val must be 0 or 1 */
... ... @@ -170,16 +172,16 @@ void pit_set_gate(PITChannelState *s, int val)
170 172 case 5:
171 173 if (s->gate < val) {
172 174 /* restart counting on rising edge */
173   - s->count_load_time = cpu_get_ticks();
174   - s->count_last_edge_check_time = s->count_load_time;
  175 + s->count_load_time = qemu_get_clock(vm_clock);
  176 + pit_irq_timer_update(s, s->count_load_time);
175 177 }
176 178 break;
177 179 case 2:
178 180 case 3:
179 181 if (s->gate < val) {
180 182 /* restart counting on rising edge */
181   - s->count_load_time = cpu_get_ticks();
182   - s->count_last_edge_check_time = s->count_load_time;
  183 + s->count_load_time = qemu_get_clock(vm_clock);
  184 + pit_irq_timer_update(s, s->count_load_time);
183 185 }
184 186 /* XXX: disable/enable counting */
185 187 break;
... ... @@ -191,14 +193,9 @@ static inline void pit_load_count(PITChannelState *s, int val)
191 193 {
192 194 if (val == 0)
193 195 val = 0x10000;
194   - s->count_load_time = cpu_get_ticks();
195   - s->count_last_edge_check_time = s->count_load_time;
  196 + s->count_load_time = qemu_get_clock(vm_clock);
196 197 s->count = val;
197   - if (s == &pit_channels[0] && val <= pit_min_timer_count) {
198   - fprintf(stderr,
199   - "\nWARNING: qemu: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.6 guest Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
200   - PIT_FREQ / pit_min_timer_count);
201   - }
  198 + pit_irq_timer_update(s, s->count_load_time);
202 199 }
203 200  
204 201 static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
... ... @@ -222,6 +219,7 @@ static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
222 219 s->mode = (val >> 1) & 7;
223 220 s->bcd = val & 1;
224 221 s->rw_state = access - 1 + RW_STATE_LSB;
  222 + /* XXX: update irq timer ? */
225 223 break;
226 224 }
227 225 } else {
... ... @@ -279,18 +277,100 @@ static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
279 277 return ret;
280 278 }
281 279  
282   -void pit_init(int base)
  280 +static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
  281 +{
  282 + int64_t expire_time;
  283 + int irq_level;
  284 +
  285 + if (!s->irq_timer)
  286 + return;
  287 + expire_time = pit_get_next_transition_time(s, current_time);
  288 + irq_level = pit_get_out(s, current_time);
  289 + pic_set_irq(s->irq, irq_level);
  290 +#ifdef DEBUG_PIT
  291 + printf("irq_level=%d next_delay=%f\n",
  292 + irq_level,
  293 + (double)(expire_time - current_time) / ticks_per_sec);
  294 +#endif
  295 + s->next_transition_time = expire_time;
  296 + if (expire_time != -1)
  297 + qemu_mod_timer(s->irq_timer, expire_time);
  298 + else
  299 + qemu_del_timer(s->irq_timer);
  300 +}
  301 +
  302 +static void pit_irq_timer(void *opaque)
  303 +{
  304 + PITChannelState *s = opaque;
  305 +
  306 + pit_irq_timer_update(s, s->next_transition_time);
  307 +}
  308 +
  309 +static void pit_save(QEMUFile *f, void *opaque)
  310 +{
  311 + PITChannelState *s;
  312 + int i;
  313 +
  314 + for(i = 0; i < 3; i++) {
  315 + s = &pit_channels[i];
  316 + qemu_put_be32s(f, &s->count);
  317 + qemu_put_be16s(f, &s->latched_count);
  318 + qemu_put_8s(f, &s->rw_state);
  319 + qemu_put_8s(f, &s->mode);
  320 + qemu_put_8s(f, &s->bcd);
  321 + qemu_put_8s(f, &s->gate);
  322 + qemu_put_be64s(f, &s->count_load_time);
  323 + if (s->irq_timer) {
  324 + qemu_put_be64s(f, &s->next_transition_time);
  325 + qemu_put_timer(f, s->irq_timer);
  326 + }
  327 + }
  328 +}
  329 +
  330 +static int pit_load(QEMUFile *f, void *opaque, int version_id)
  331 +{
  332 + PITChannelState *s;
  333 + int i;
  334 +
  335 + if (version_id != 1)
  336 + return -EINVAL;
  337 +
  338 + for(i = 0; i < 3; i++) {
  339 + s = &pit_channels[i];
  340 + qemu_get_be32s(f, &s->count);
  341 + qemu_get_be16s(f, &s->latched_count);
  342 + qemu_get_8s(f, &s->rw_state);
  343 + qemu_get_8s(f, &s->mode);
  344 + qemu_get_8s(f, &s->bcd);
  345 + qemu_get_8s(f, &s->gate);
  346 + qemu_get_be64s(f, &s->count_load_time);
  347 + if (s->irq_timer) {
  348 + qemu_get_be64s(f, &s->next_transition_time);
  349 + qemu_get_timer(f, s->irq_timer);
  350 + }
  351 + }
  352 + return 0;
  353 +}
  354 +
  355 +void pit_init(int base, int irq)
283 356 {
284 357 PITChannelState *s;
285 358 int i;
286 359  
287 360 for(i = 0;i < 3; i++) {
288 361 s = &pit_channels[i];
  362 + if (i == 0) {
  363 + /* the timer 0 is connected to an IRQ */
  364 + s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
  365 + s->irq = irq;
  366 + }
289 367 s->mode = 3;
290 368 s->gate = (i != 2);
291 369 pit_load_count(s, 0);
292 370 }
293 371  
  372 + register_savevm("i8254", base, 1, pit_save, pit_load, NULL);
  373 +
294 374 register_ioport_write(base, 4, 1, pit_ioport_write, NULL);
295 375 register_ioport_read(base, 3, 1, pit_ioport_read, NULL);
296 376 }
... ...
hw/i8259.c
  View file @b0a21b5
... ... @@ -122,7 +122,7 @@ static int pic_get_irq(PicState *s)
122 122  
123 123 /* raise irq to CPU if necessary. must be called every time the active
124 124 irq may change */
125   -void pic_update_irq(void)
  125 +static void pic_update_irq(void)
126 126 {
127 127 int irq2, irq;
128 128  
... ... @@ -160,7 +160,6 @@ void pic_update_irq(void)
160 160  
161 161 #ifdef DEBUG_IRQ_LATENCY
162 162 int64_t irq_time[16];
163   -int64_t cpu_get_ticks(void);
164 163 #endif
165 164 #if defined(DEBUG_PIC)
166 165 int irq_level[16];
... ... @@ -376,11 +375,62 @@ uint32_t pic_intack_read(CPUState *env)
376 375 return ret;
377 376 }
378 377  
  378 +static void pic_save(QEMUFile *f, void *opaque)
  379 +{
  380 + PicState *s = opaque;
  381 +
  382 + qemu_put_8s(f, &s->last_irr);
  383 + qemu_put_8s(f, &s->irr);
  384 + qemu_put_8s(f, &s->imr);
  385 + qemu_put_8s(f, &s->isr);
  386 + qemu_put_8s(f, &s->priority_add);
  387 + qemu_put_8s(f, &s->irq_base);
  388 + qemu_put_8s(f, &s->read_reg_select);
  389 + qemu_put_8s(f, &s->poll);
  390 + qemu_put_8s(f, &s->special_mask);
  391 + qemu_put_8s(f, &s->init_state);
  392 + qemu_put_8s(f, &s->auto_eoi);
  393 + qemu_put_8s(f, &s->rotate_on_auto_eoi);
  394 + qemu_put_8s(f, &s->special_fully_nested_mode);
  395 + qemu_put_8s(f, &s->init4);
  396 +}
  397 +
  398 +static int pic_load(QEMUFile *f, void *opaque, int version_id)
  399 +{
  400 + PicState *s = opaque;
  401 +
  402 + if (version_id != 1)
  403 + return -EINVAL;
  404 +
  405 + qemu_get_8s(f, &s->last_irr);
  406 + qemu_get_8s(f, &s->irr);
  407 + qemu_get_8s(f, &s->imr);
  408 + qemu_get_8s(f, &s->isr);
  409 + qemu_get_8s(f, &s->priority_add);
  410 + qemu_get_8s(f, &s->irq_base);
  411 + qemu_get_8s(f, &s->read_reg_select);
  412 + qemu_get_8s(f, &s->poll);
  413 + qemu_get_8s(f, &s->special_mask);
  414 + qemu_get_8s(f, &s->init_state);
  415 + qemu_get_8s(f, &s->auto_eoi);
  416 + qemu_get_8s(f, &s->rotate_on_auto_eoi);
  417 + qemu_get_8s(f, &s->special_fully_nested_mode);
  418 + qemu_get_8s(f, &s->init4);
  419 + return 0;
  420 +}
  421 +
  422 +/* XXX: add generic master/slave system */
  423 +static void pic_init1(int io_addr, PicState *s)
  424 +{
  425 + register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
  426 + register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
  427 +
  428 + register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
  429 +}
  430 +
379 431 void pic_init(void)
380 432 {
381   - register_ioport_write(0x20, 2, 1, pic_ioport_write, &pics[0]);
382   - register_ioport_read(0x20, 2, 1, pic_ioport_read, &pics[0]);
383   - register_ioport_write(0xa0, 2, 1, pic_ioport_write, &pics[1]);
384   - register_ioport_read(0xa0, 2, 1, pic_ioport_read, &pics[1]);
  433 + pic_init1(0x20, &pics[0]);
  434 + pic_init1(0xa0, &pics[1]);
385 435 }
386 436  
... ...
hw/ne2000.c
  View file @b0a21b5
... ... @@ -471,5 +471,5 @@ void ne2000_init(int base, int irq, NetDriverState *nd)
471 471  
472 472 ne2000_reset(s);
473 473  
474   - add_fd_read_handler(nd->fd, ne2000_can_receive, ne2000_receive, s);
  474 + qemu_add_fd_read_handler(nd->fd, ne2000_can_receive, ne2000_receive, s);
475 475 }
... ...
... ... @@ -58,50 +58,69 @@
58 58 int speaker_data_on;
59 59 int dummy_refresh_clock;
60 60 static fdctrl_t *floppy_controller;
  61 +static RTCState *rtc_state;
61 62  
62 63 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
63 64 {
64 65 }
65 66  
  67 +/* PC cmos mappings */
  68 +
66 69 #define REG_EQUIPMENT_BYTE 0x14
  70 +#define REG_IBM_CENTURY_BYTE 0x32
  71 +#define REG_IBM_PS2_CENTURY_BYTE 0x37
  72 +
  73 +
  74 +static inline int to_bcd(RTCState *s, int a)
  75 +{
  76 + return ((a / 10) << 4) | (a % 10);
  77 +}
67 78  
68 79 static void cmos_init(int ram_size, int boot_device)
69 80 {
70   - RTCState *s = &rtc_state;
  81 + RTCState *s = rtc_state;
71 82 int val;
72 83 int fd0, fd1, nb;
73   -
74   - /* various important CMOS locations needed by PC/Bochs bios */
  84 + time_t ti;
  85 + struct tm *tm;
  86 +
  87 + /* set the CMOS date */
  88 + time(&ti);
  89 + tm = gmtime(&ti);
  90 + rtc_set_date(s, tm);
  91 +
  92 + val = to_bcd(s, (tm->tm_year / 100) + 19);
  93 + rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
  94 + rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
75 95  
76   - s->cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
77   - s->cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */
  96 + /* various important CMOS locations needed by PC/Bochs bios */
78 97  
79 98 /* memory size */
80 99 val = (ram_size / 1024) - 1024;
81 100 if (val > 65535)
82 101 val = 65535;
83   - s->cmos_data[0x17] = val;
84   - s->cmos_data[0x18] = val >> 8;
85   - s->cmos_data[0x30] = val;
86   - s->cmos_data[0x31] = val >> 8;
  102 + rtc_set_memory(s, 0x17, val);
  103 + rtc_set_memory(s, 0x18, val >> 8);
  104 + rtc_set_memory(s, 0x30, val);
  105 + rtc_set_memory(s, 0x31, val >> 8);
87 106  
88 107 val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
89 108 if (val > 65535)
90 109 val = 65535;
91   - s->cmos_data[0x34] = val;
92   - s->cmos_data[0x35] = val >> 8;
  110 + rtc_set_memory(s, 0x34, val);
  111 + rtc_set_memory(s, 0x35, val >> 8);
93 112  
94 113 switch(boot_device) {
95 114 case 'a':
96 115 case 'b':
97   - s->cmos_data[0x3d] = 0x01; /* floppy boot */
  116 + rtc_set_memory(s, 0x3d, 0x01); /* floppy boot */
98 117 break;
99 118 default:
100 119 case 'c':
101   - s->cmos_data[0x3d] = 0x02; /* hard drive boot */
  120 + rtc_set_memory(s, 0x3d, 0x02); /* hard drive boot */
102 121 break;
103 122 case 'd':
104   - s->cmos_data[0x3d] = 0x03; /* CD-ROM boot */
  123 + rtc_set_memory(s, 0x3d, 0x03); /* CD-ROM boot */
105 124 break;
106 125 }
107 126  
... ... @@ -110,35 +129,38 @@ static void cmos_init(int ram_size, int boot_device)
110 129 fd0 = fdctrl_get_drive_type(floppy_controller, 0);
111 130 fd1 = fdctrl_get_drive_type(floppy_controller, 1);
112 131  
113   - s->cmos_data[0x10] = 0;
  132 + val = 0;
114 133 switch (fd0) {
115 134 case 0:
116 135 /* 1.44 Mb 3"5 drive */
117   - s->cmos_data[0x10] |= 0x40;
  136 + val |= 0x40;
118 137 break;
119 138 case 1:
120 139 /* 2.88 Mb 3"5 drive */
121   - s->cmos_data[0x10] |= 0x60;
  140 + val |= 0x60;
122 141 break;
123 142 case 2:
124 143 /* 1.2 Mb 5"5 drive */
125   - s->cmos_data[0x10] |= 0x20;
  144 + val |= 0x20;
126 145 break;
127 146 }
128 147 switch (fd1) {
129 148 case 0:
130 149 /* 1.44 Mb 3"5 drive */
131   - s->cmos_data[0x10] |= 0x04;
  150 + val |= 0x04;
132 151 break;
133 152 case 1:
134 153 /* 2.88 Mb 3"5 drive */
135   - s->cmos_data[0x10] |= 0x06;
  154 + val |= 0x06;
136 155 break;
137 156 case 2:
138 157 /* 1.2 Mb 5"5 drive */
139   - s->cmos_data[0x10] |= 0x02;
  158 + val |= 0x02;
140 159 break;
141 160 }
  161 + rtc_set_memory(s, 0x10, val);
  162 +
  163 + val = 0;
142 164 nb = 0;
143 165 if (fd0 < 3)
144 166 nb++;
... ... @@ -148,12 +170,16 @@ static void cmos_init(int ram_size, int boot_device)
148 170 case 0:
149 171 break;
150 172 case 1:
151   - s->cmos_data[REG_EQUIPMENT_BYTE] |= 0x01; /* 1 drive, ready for boot */
  173 + val |= 0x01; /* 1 drive, ready for boot */
152 174 break;
153 175 case 2:
154   - s->cmos_data[REG_EQUIPMENT_BYTE] |= 0x41; /* 2 drives, ready for boot */
  176 + val |= 0x41; /* 2 drives, ready for boot */
155 177 break;
156 178 }
  179 + val |= 0x02; /* FPU is there */
  180 + val |= 0x04; /* PS/2 mouse installed */
  181 + rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
  182 +
157 183 }
158 184  
159 185 static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val)
... ... @@ -165,7 +191,7 @@ static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val)
165 191 static uint32_t speaker_ioport_read(void *opaque, uint32_t addr)
166 192 {
167 193 int out;
168   - out = pit_get_out(&pit_channels[2]);
  194 + out = pit_get_out(&pit_channels[2], qemu_get_clock(vm_clock));
169 195 dummy_refresh_clock ^= 1;
170 196 return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) |
171 197 (dummy_refresh_clock << 4);
... ... @@ -345,12 +371,12 @@ void pc_init(int ram_size, int vga_ram_size, int boot_device,
345 371 vga_initialize(ds, phys_ram_base + ram_size, ram_size,
346 372 vga_ram_size);
347 373  
348   - rtc_init(0x70, 8);
  374 + rtc_state = rtc_init(0x70, 8);
349 375 register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
350 376 register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
351 377  
352 378 pic_init();
353   - pit_init(0x40);
  379 + pit_init(0x40, 0);
354 380  
355 381 fd = serial_open_device();
356 382 serial_init(0x3f8, 4, fd);
... ...
hw/serial.c
  View file @b0a21b5
... ... @@ -288,7 +288,7 @@ SerialState *serial_init(int base, int irq, int fd)
288 288 register_ioport_read(base, 8, 1, serial_ioport_read, s);
289 289  
290 290 if (fd != 0) {
291   - add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s);
  291 + qemu_add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s);
292 292 s->out_fd = fd;
293 293 } else {
294 294 serial_console = s;
... ...
hw/vga.c
  View file @b0a21b5
... ... @@ -1578,6 +1578,98 @@ static CPUWriteMemoryFunc *vga_mem_write[3] = {
1578 1578 vga_mem_writel,
1579 1579 };
1580 1580  
  1581 +static void vga_save(QEMUFile *f, void *opaque)
  1582 +{
  1583 + VGAState *s = opaque;
  1584 + int i;
  1585 +
  1586 + qemu_put_be32s(f, &s->latch);
  1587 + qemu_put_8s(f, &s->sr_index);
  1588 + qemu_put_buffer(f, s->sr, 8);
  1589 + qemu_put_8s(f, &s->gr_index);
  1590 + qemu_put_buffer(f, s->gr, 16);
  1591 + qemu_put_8s(f, &s->ar_index);
  1592 + qemu_put_buffer(f, s->ar, 21);
  1593 + qemu_put_be32s(f, &s->ar_flip_flop);
  1594 + qemu_put_8s(f, &s->cr_index);
  1595 + qemu_put_buffer(f, s->cr, 256);
  1596 + qemu_put_8s(f, &s->msr);
  1597 + qemu_put_8s(f, &s->fcr);
  1598 + qemu_put_8s(f, &s->st00);
  1599 + qemu_put_8s(f, &s->st01);
  1600 +
  1601 + qemu_put_8s(f, &s->dac_state);
  1602 + qemu_put_8s(f, &s->dac_sub_index);
  1603 + qemu_put_8s(f, &s->dac_read_index);
  1604 + qemu_put_8s(f, &s->dac_write_index);
  1605 + qemu_put_buffer(f, s->dac_cache, 3);
  1606 + qemu_put_buffer(f, s->palette, 768);
  1607 +
  1608 + qemu_put_be32s(f, &s->bank_offset);
  1609 +#ifdef CONFIG_BOCHS_VBE
  1610 + qemu_put_byte(f, 1);
  1611 + qemu_put_be16s(f, &s->vbe_index);
  1612 + for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
  1613 + qemu_put_be16s(f, &s->vbe_regs[i]);
  1614 + qemu_put_be32s(f, &s->vbe_start_addr);
  1615 + qemu_put_be32s(f, &s->vbe_line_offset);
  1616 + qemu_put_be32s(f, &s->vbe_bank_mask);
  1617 +#else
  1618 + qemu_put_byte(f, 0);
  1619 +#endif
  1620 +}
  1621 +
  1622 +static int vga_load(QEMUFile *f, void *opaque, int version_id)
  1623 +{
  1624 + VGAState *s = opaque;
  1625 + int is_vbe, i;
  1626 +
  1627 + if (version_id != 1)
  1628 + return -EINVAL;
  1629 +
  1630 + qemu_get_be32s(f, &s->latch);
  1631 + qemu_get_8s(f, &s->sr_index);
  1632 + qemu_get_buffer(f, s->sr, 8);
  1633 + qemu_get_8s(f, &s->gr_index);
  1634 + qemu_get_buffer(f, s->gr, 16);
  1635 + qemu_get_8s(f, &s->ar_index);
  1636 + qemu_get_buffer(f, s->ar, 21);
  1637 + qemu_get_be32s(f, &s->ar_flip_flop);
  1638 + qemu_get_8s(f, &s->cr_index);
  1639 + qemu_get_buffer(f, s->cr, 256);
  1640 + qemu_get_8s(f, &s->msr);
  1641 + qemu_get_8s(f, &s->fcr);
  1642 + qemu_get_8s(f, &s->st00);
  1643 + qemu_get_8s(f, &s->st01);
  1644 +
  1645 + qemu_get_8s(f, &s->dac_state);
  1646 + qemu_get_8s(f, &s->dac_sub_index);
  1647 + qemu_get_8s(f, &s->dac_read_index);
  1648 + qemu_get_8s(f, &s->dac_write_index);
  1649 + qemu_get_buffer(f, s->dac_cache, 3);
  1650 + qemu_get_buffer(f, s->palette, 768);
  1651 +
  1652 + qemu_get_be32s(f, &s->bank_offset);
  1653 + is_vbe = qemu_get_byte(f);
  1654 +#ifdef CONFIG_BOCHS_VBE
  1655 + if (!is_vbe)
  1656 + return -EINVAL;
  1657 + qemu_get_be16s(f, &s->vbe_index);
  1658 + for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
  1659 + qemu_get_be16s(f, &s->vbe_regs[i]);
  1660 + qemu_get_be32s(f, &s->vbe_start_addr);
  1661 + qemu_get_be32s(f, &s->vbe_line_offset);
  1662 + qemu_get_be32s(f, &s->vbe_bank_mask);
  1663 +#else
  1664 + if (is_vbe)
  1665 + return -EINVAL;
  1666 +#endif
  1667 +
  1668 + /* force refresh */
  1669 + s->graphic_mode = -1;
  1670 + return 0;
  1671 +}
  1672 +
1581 1673 int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
1582 1674 unsigned long vga_ram_offset, int vga_ram_size)
1583 1675 {
... ... @@ -1614,6 +1706,8 @@ int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
1614 1706 s->vram_size = vga_ram_size;
1615 1707 s->ds = ds;
1616 1708  
  1709 + register_savevm("vga", 0, 1, vga_save, vga_load, s);
  1710 +
1617 1711 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
1618 1712  
1619 1713 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
... ...