Commit b03d0971b3744cf5778264c9aedb4084f779c774
1 parent
04acd307
target-alpha: switch most load/store ops to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5255 c046a42c-6fe2-441c-8c8c-71466251a162
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2 changed files
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128 additions
and
27 deletions
target-alpha/op_mem.h
@@ -80,18 +80,11 @@ void OPPROTO glue(glue(op_st, name), MEMSUFFIX) (void) \ | @@ -80,18 +80,11 @@ void OPPROTO glue(glue(op_st, name), MEMSUFFIX) (void) \ | ||
80 | RETURN(); \ | 80 | RETURN(); \ |
81 | } | 81 | } |
82 | 82 | ||
83 | -ALPHA_LD_OP(bu, ldub); | ||
84 | -ALPHA_ST_OP(b, stb); | ||
85 | -ALPHA_LD_OP(wu, lduw); | ||
86 | -ALPHA_ST_OP(w, stw); | ||
87 | ALPHA_LD_OP(l, ldl); | 83 | ALPHA_LD_OP(l, ldl); |
88 | ALPHA_ST_OP(l, stl); | 84 | ALPHA_ST_OP(l, stl); |
89 | ALPHA_LD_OP(q, ldq); | 85 | ALPHA_LD_OP(q, ldq); |
90 | ALPHA_ST_OP(q, stq); | 86 | ALPHA_ST_OP(q, stq); |
91 | 87 | ||
92 | -ALPHA_LD_OP(q_u, ldq); | ||
93 | -ALPHA_ST_OP(q_u, stq); | ||
94 | - | ||
95 | ALPHA_LD_OP(l_l, ldl_l); | 88 | ALPHA_LD_OP(l_l, ldl_l); |
96 | ALPHA_LD_OP(q_l, ldq_l); | 89 | ALPHA_LD_OP(q_l, ldq_l); |
97 | ALPHA_ST_OP(l_c, stl_c); | 90 | ALPHA_ST_OP(l_c, stl_c); |
target-alpha/translate.c
@@ -209,16 +209,10 @@ static always_inline void gen_st##width (DisasContext *ctx) \ | @@ -209,16 +209,10 @@ static always_inline void gen_st##width (DisasContext *ctx) \ | ||
209 | (*gen_op_st##width[ctx->mem_idx])(); \ | 209 | (*gen_op_st##width[ctx->mem_idx])(); \ |
210 | } | 210 | } |
211 | 211 | ||
212 | -GEN_LD(bu); | ||
213 | -GEN_ST(b); | ||
214 | -GEN_LD(wu); | ||
215 | -GEN_ST(w); | ||
216 | GEN_LD(l); | 212 | GEN_LD(l); |
217 | GEN_ST(l); | 213 | GEN_ST(l); |
218 | GEN_LD(q); | 214 | GEN_LD(q); |
219 | GEN_ST(q); | 215 | GEN_ST(q); |
220 | -GEN_LD(q_u); | ||
221 | -GEN_ST(q_u); | ||
222 | GEN_LD(l_l); | 216 | GEN_LD(l_l); |
223 | GEN_ST(l_c); | 217 | GEN_ST(l_c); |
224 | GEN_LD(q_l); | 218 | GEN_LD(q_l); |
@@ -661,33 +655,103 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) | @@ -661,33 +655,103 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) | ||
661 | /* LDBU */ | 655 | /* LDBU */ |
662 | if (!(ctx->amask & AMASK_BWX)) | 656 | if (!(ctx->amask & AMASK_BWX)) |
663 | goto invalid_opc; | 657 | goto invalid_opc; |
664 | - gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0); | 658 | + if (likely(ra != 31)) { |
659 | + TCGv addr = tcg_temp_new(TCG_TYPE_I64); | ||
660 | + if (rb != 31) | ||
661 | + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); | ||
662 | + else | ||
663 | + tcg_gen_movi_i64(addr, disp16); | ||
664 | + tcg_gen_qemu_ld8u(cpu_ir[ra], addr, ctx->mem_idx); | ||
665 | + tcg_temp_free(addr); | ||
666 | + } | ||
665 | break; | 667 | break; |
666 | case 0x0B: | 668 | case 0x0B: |
667 | /* LDQ_U */ | 669 | /* LDQ_U */ |
668 | - gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1); | 670 | + if (likely(ra != 31)) { |
671 | + TCGv addr = tcg_temp_new(TCG_TYPE_I64); | ||
672 | + if (rb != 31) { | ||
673 | + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); | ||
674 | + tcg_gen_andi_i64(addr, addr, ~0x7); | ||
675 | + } else | ||
676 | + tcg_gen_movi_i64(addr, disp16 & ~0x7); | ||
677 | + tcg_gen_qemu_ld64(cpu_ir[ra], addr, ctx->mem_idx); | ||
678 | + tcg_temp_free(addr); | ||
679 | + } | ||
669 | break; | 680 | break; |
670 | case 0x0C: | 681 | case 0x0C: |
671 | /* LDWU */ | 682 | /* LDWU */ |
672 | if (!(ctx->amask & AMASK_BWX)) | 683 | if (!(ctx->amask & AMASK_BWX)) |
673 | goto invalid_opc; | 684 | goto invalid_opc; |
674 | - gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0); | 685 | + if (likely(ra != 31)) { |
686 | + TCGv addr = tcg_temp_new(TCG_TYPE_I64); | ||
687 | + if (rb != 31) | ||
688 | + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); | ||
689 | + else | ||
690 | + tcg_gen_movi_i64(addr, disp16); | ||
691 | + tcg_gen_qemu_ld16u(cpu_ir[ra], addr, ctx->mem_idx); | ||
692 | + tcg_temp_free(addr); | ||
693 | + } | ||
675 | break; | 694 | break; |
676 | case 0x0D: | 695 | case 0x0D: |
677 | /* STW */ | 696 | /* STW */ |
678 | - if (!(ctx->amask & AMASK_BWX)) | ||
679 | - goto invalid_opc; | ||
680 | - gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0); | 697 | + { |
698 | + TCGv addr; | ||
699 | + if (!(ctx->amask & AMASK_BWX)) | ||
700 | + goto invalid_opc; | ||
701 | + addr = tcg_temp_new(TCG_TYPE_I64); | ||
702 | + if (rb != 31) | ||
703 | + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); | ||
704 | + else | ||
705 | + tcg_gen_movi_i64(addr, disp16); | ||
706 | + if (ra != 31) | ||
707 | + tcg_gen_qemu_st16(cpu_ir[ra], addr, ctx->mem_idx); | ||
708 | + else { | ||
709 | + TCGv zero = tcg_const_i64(0); | ||
710 | + tcg_gen_qemu_st16(zero, addr, ctx->mem_idx); | ||
711 | + tcg_temp_free(zero); | ||
712 | + } | ||
713 | + tcg_temp_free(addr); | ||
714 | + } | ||
681 | break; | 715 | break; |
682 | case 0x0E: | 716 | case 0x0E: |
683 | /* STB */ | 717 | /* STB */ |
684 | - if (!(ctx->amask & AMASK_BWX)) | ||
685 | - goto invalid_opc; | ||
686 | - gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0); | 718 | + { |
719 | + TCGv addr; | ||
720 | + if (!(ctx->amask & AMASK_BWX)) | ||
721 | + goto invalid_opc; | ||
722 | + addr = tcg_temp_new(TCG_TYPE_I64); | ||
723 | + if (rb != 31) | ||
724 | + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); | ||
725 | + else | ||
726 | + tcg_gen_movi_i64(addr, disp16); | ||
727 | + if (ra != 31) | ||
728 | + tcg_gen_qemu_st8(cpu_ir[ra], addr, ctx->mem_idx); | ||
729 | + else { | ||
730 | + TCGv zero = tcg_const_i64(0); | ||
731 | + tcg_gen_qemu_st8(zero, addr, ctx->mem_idx); | ||
732 | + tcg_temp_free(zero); | ||
733 | + } | ||
734 | + tcg_temp_free(addr); | ||
735 | + } | ||
687 | break; | 736 | break; |
688 | case 0x0F: | 737 | case 0x0F: |
689 | /* STQ_U */ | 738 | /* STQ_U */ |
690 | - gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1); | 739 | + { |
740 | + TCGv addr = tcg_temp_new(TCG_TYPE_I64); | ||
741 | + if (rb != 31) { | ||
742 | + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); | ||
743 | + tcg_gen_andi_i64(addr, addr, ~0x7); | ||
744 | + } else | ||
745 | + tcg_gen_movi_i64(addr, disp16 & ~0x7); | ||
746 | + if (ra != 31) | ||
747 | + tcg_gen_qemu_st64(cpu_ir[ra], addr, ctx->mem_idx); | ||
748 | + else { | ||
749 | + TCGv zero = tcg_const_i64(0); | ||
750 | + tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); | ||
751 | + tcg_temp_free(zero); | ||
752 | + } | ||
753 | + tcg_temp_free(addr); | ||
754 | + } | ||
691 | break; | 755 | break; |
692 | case 0x10: | 756 | case 0x10: |
693 | switch (fn7) { | 757 | switch (fn7) { |
@@ -2125,11 +2189,27 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) | @@ -2125,11 +2189,27 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) | ||
2125 | break; | 2189 | break; |
2126 | case 0x28: | 2190 | case 0x28: |
2127 | /* LDL */ | 2191 | /* LDL */ |
2128 | - gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0); | 2192 | + if (likely(ra != 31)) { |
2193 | + TCGv addr = tcg_temp_new(TCG_TYPE_I64); | ||
2194 | + if (rb != 31) | ||
2195 | + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); | ||
2196 | + else | ||
2197 | + tcg_gen_movi_i64(addr, disp16); | ||
2198 | + tcg_gen_qemu_ld32s(cpu_ir[ra], addr, ctx->mem_idx); | ||
2199 | + tcg_temp_free(addr); | ||
2200 | + } | ||
2129 | break; | 2201 | break; |
2130 | case 0x29: | 2202 | case 0x29: |
2131 | /* LDQ */ | 2203 | /* LDQ */ |
2132 | - gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0); | 2204 | + if (likely(ra != 31)) { |
2205 | + TCGv addr = tcg_temp_new(TCG_TYPE_I64); | ||
2206 | + if (rb != 31) | ||
2207 | + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); | ||
2208 | + else | ||
2209 | + tcg_gen_movi_i64(addr, disp16); | ||
2210 | + tcg_gen_qemu_ld64(cpu_ir[ra], addr, ctx->mem_idx); | ||
2211 | + tcg_temp_free(addr); | ||
2212 | + } | ||
2133 | break; | 2213 | break; |
2134 | case 0x2A: | 2214 | case 0x2A: |
2135 | /* LDL_L */ | 2215 | /* LDL_L */ |
@@ -2141,11 +2221,39 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) | @@ -2141,11 +2221,39 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) | ||
2141 | break; | 2221 | break; |
2142 | case 0x2C: | 2222 | case 0x2C: |
2143 | /* STL */ | 2223 | /* STL */ |
2144 | - gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0); | 2224 | + { |
2225 | + TCGv addr = tcg_temp_new(TCG_TYPE_I64); | ||
2226 | + if (rb != 31) | ||
2227 | + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); | ||
2228 | + else | ||
2229 | + tcg_gen_movi_i64(addr, disp16); | ||
2230 | + if (ra != 31) | ||
2231 | + tcg_gen_qemu_st32(cpu_ir[ra], addr, ctx->mem_idx); | ||
2232 | + else { | ||
2233 | + TCGv zero = tcg_const_i64(0); | ||
2234 | + tcg_gen_qemu_st32(zero, addr, ctx->mem_idx); | ||
2235 | + tcg_temp_free(zero); | ||
2236 | + } | ||
2237 | + tcg_temp_free(addr); | ||
2238 | + } | ||
2145 | break; | 2239 | break; |
2146 | case 0x2D: | 2240 | case 0x2D: |
2147 | /* STQ */ | 2241 | /* STQ */ |
2148 | - gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0); | 2242 | + { |
2243 | + TCGv addr = tcg_temp_new(TCG_TYPE_I64); | ||
2244 | + if (rb != 31) | ||
2245 | + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); | ||
2246 | + else | ||
2247 | + tcg_gen_movi_i64(addr, disp16); | ||
2248 | + if (ra != 31) | ||
2249 | + tcg_gen_qemu_st64(cpu_ir[ra], addr, ctx->mem_idx); | ||
2250 | + else { | ||
2251 | + TCGv zero = tcg_const_i64(0); | ||
2252 | + tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); | ||
2253 | + tcg_temp_free(zero); | ||
2254 | + } | ||
2255 | + tcg_temp_free(addr); | ||
2256 | + } | ||
2149 | break; | 2257 | break; |
2150 | case 0x2E: | 2258 | case 0x2E: |
2151 | /* STL_C */ | 2259 | /* STL_C */ |