gwj / at91sam9263 · Commits

Commit aef445bd7e46d2d47701a03c5478da34b3d53c4c

Authored by pbrook
1 parent 6787f5fa

Merge common ISA access routines. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2159 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 6 changed files with 110 additions and 150 deletions
Makefile.target
  View file @aef445b
... ... @@ -289,7 +289,7 @@ ifeq ($(ARCH),alpha)
289 289 endif
290 290  
291 291 # must use static linking to avoid leaving stuff in virtual address space
292   -VL_OBJS=vl.o osdep.o readline.o monitor.o pci.o console.o loader.o
  292 +VL_OBJS=vl.o osdep.o readline.o monitor.o pci.o console.o loader.o isa_mmio.o
293 293 VL_OBJS+=block.o block-raw.o
294 294 VL_OBJS+=block-cow.o block-qcow.o aes.o block-vmdk.o block-cloop.o block-dmg.o block-bochs.o block-vpc.o block-vvfat.o block-qcow2.o
295 295 ifdef CONFIG_WIN32
... ...
hw/isa_mmio.c 0 → 100644
  View file @aef445b
  1 +/*
  2 + * Memory mapped access to ISA IO space.
  3 + *
  4 + * Copyright (c) 2006 Fabrice Bellard
  5 + *
  6 + * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 + * of this software and associated documentation files (the "Software"), to deal
  8 + * in the Software without restriction, including without limitation the rights
  9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 + * copies of the Software, and to permit persons to whom the Software is
  11 + * furnished to do so, subject to the following conditions:
  12 + *
  13 + * The above copyright notice and this permission notice shall be included in
  14 + * all copies or substantial portions of the Software.
  15 + *
  16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 + * THE SOFTWARE.
  23 + */
  24 +
  25 +#include "vl.h"
  26 +
  27 +static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
  28 + uint32_t val)
  29 +{
  30 + cpu_outb(NULL, addr & 0xffff, val);
  31 +}
  32 +
  33 +static void isa_mmio_writew (void *opaque, target_phys_addr_t addr,
  34 + uint32_t val)
  35 +{
  36 +#ifdef TARGET_WORDS_BIGENDIAN
  37 + val = bswap16(val);
  38 +#endif
  39 + cpu_outw(NULL, addr & 0xffff, val);
  40 +}
  41 +
  42 +static void isa_mmio_writel (void *opaque, target_phys_addr_t addr,
  43 + uint32_t val)
  44 +{
  45 +#ifdef TARGET_WORDS_BIGENDIAN
  46 + val = bswap32(val);
  47 +#endif
  48 + cpu_outl(NULL, addr & 0xffff, val);
  49 +}
  50 +
  51 +static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
  52 +{
  53 + uint32_t val;
  54 +
  55 + val = cpu_inb(NULL, addr & 0xffff);
  56 + return val;
  57 +}
  58 +
  59 +static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr)
  60 +{
  61 + uint32_t val;
  62 +
  63 + val = cpu_inw(NULL, addr & 0xffff);
  64 +#ifdef TARGET_WORDS_BIGENDIAN
  65 + val = bswap16(val);
  66 +#endif
  67 + return val;
  68 +}
  69 +
  70 +static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr)
  71 +{
  72 + uint32_t val;
  73 +
  74 + val = cpu_inl(NULL, addr & 0xffff);
  75 +#ifdef TARGET_WORDS_BIGENDIAN
  76 + val = bswap32(val);
  77 +#endif
  78 + return val;
  79 +}
  80 +
  81 +static CPUWriteMemoryFunc *isa_mmio_write[] = {
  82 + &isa_mmio_writeb,
  83 + &isa_mmio_writew,
  84 + &isa_mmio_writel,
  85 +};
  86 +
  87 +static CPUReadMemoryFunc *isa_mmio_read[] = {
  88 + &isa_mmio_readb,
  89 + &isa_mmio_readw,
  90 + &isa_mmio_readl,
  91 +};
  92 +
  93 +static int isa_mmio_iomemtype = 0;
  94 +
  95 +void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
  96 +{
  97 + if (!isa_mmio_iomemtype) {
  98 + isa_mmio_iomemtype = cpu_register_io_memory(0, isa_mmio_read,
  99 + isa_mmio_write, NULL);
  100 + }
  101 + cpu_register_physical_memory(base, size, isa_mmio_iomemtype);
  102 +}
... ...
hw/mips_r4k.c
  View file @aef445b
... ... @@ -107,88 +107,6 @@ void cpu_mips_clock_init (CPUState *env)
107 107 }
108 108  
109 109  
110   -static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
111   -{
112   -#if 0
113   - if (logfile)
114   - fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
115   -#endif
116   - cpu_outb(NULL, addr & 0xffff, value);
117   -}
118   -
119   -static uint32_t io_readb (void *opaque, target_phys_addr_t addr)
120   -{
121   - uint32_t ret = cpu_inb(NULL, addr & 0xffff);
122   -#if 0
123   - if (logfile)
124   - fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
125   -#endif
126   - return ret;
127   -}
128   -
129   -static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
130   -{
131   -#if 0
132   - if (logfile)
133   - fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
134   -#endif
135   -#ifdef TARGET_WORDS_BIGENDIAN
136   - value = bswap16(value);
137   -#endif
138   - cpu_outw(NULL, addr & 0xffff, value);
139   -}
140   -
141   -static uint32_t io_readw (void *opaque, target_phys_addr_t addr)
142   -{
143   - uint32_t ret = cpu_inw(NULL, addr & 0xffff);
144   -#ifdef TARGET_WORDS_BIGENDIAN
145   - ret = bswap16(ret);
146   -#endif
147   -#if 0
148   - if (logfile)
149   - fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
150   -#endif
151   - return ret;
152   -}
153   -
154   -static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
155   -{
156   -#if 0
157   - if (logfile)
158   - fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
159   -#endif
160   -#ifdef TARGET_WORDS_BIGENDIAN
161   - value = bswap32(value);
162   -#endif
163   - cpu_outl(NULL, addr & 0xffff, value);
164   -}
165   -
166   -static uint32_t io_readl (void *opaque, target_phys_addr_t addr)
167   -{
168   - uint32_t ret = cpu_inl(NULL, addr & 0xffff);
169   -
170   -#ifdef TARGET_WORDS_BIGENDIAN
171   - ret = bswap32(ret);
172   -#endif
173   -#if 0
174   - if (logfile)
175   - fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
176   -#endif
177   - return ret;
178   -}
179   -
180   -CPUWriteMemoryFunc *io_write[] = {
181   - &io_writeb,
182   - &io_writew,
183   - &io_writel,
184   -};
185   -
186   -CPUReadMemoryFunc *io_read[] = {
187   - &io_readb,
188   - &io_readw,
189   - &io_readl,
190   -};
191   -
192 110 void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
193 111 DisplayState *ds, const char **fd_filename, int snapshot,
194 112 const char *kernel_filename, const char *kernel_cmdline,
... ... @@ -197,7 +115,6 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
197 115 char buf[1024];
198 116 int64_t entry = 0;
199 117 unsigned long bios_offset;
200   - int io_memory;
201 118 int ret;
202 119 CPUState *env;
203 120 long kernel_size;
... ... @@ -263,8 +180,7 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
263 180 cpu_mips_irqctrl_init();
264 181  
265 182 /* Register 64 KB of ISA IO space at 0x14000000 */
266   - io_memory = cpu_register_io_memory(0, io_read, io_write, NULL);
267   - cpu_register_physical_memory(0x14000000, 0x00010000, io_memory);
  183 + isa_mmio_init(0x14000000, 0x00010000);
268 184 isa_mem_base = 0x10000000;
269 185  
270 186 isa_pic = pic_init(pic_irq_request, env);
... ...
hw/ppc.c
  View file @aef445b
... ... @@ -201,64 +201,6 @@ void cpu_ppc_reset (CPUState *env)
201 201 }
202 202 #endif
203 203  
204   -static void PPC_io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
205   -{
206   - cpu_outb(NULL, addr & 0xffff, value);
207   -}
208   -
209   -static uint32_t PPC_io_readb (void *opaque, target_phys_addr_t addr)
210   -{
211   - uint32_t ret = cpu_inb(NULL, addr & 0xffff);
212   - return ret;
213   -}
214   -
215   -static void PPC_io_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
216   -{
217   -#ifdef TARGET_WORDS_BIGENDIAN
218   - value = bswap16(value);
219   -#endif
220   - cpu_outw(NULL, addr & 0xffff, value);
221   -}
222   -
223   -static uint32_t PPC_io_readw (void *opaque, target_phys_addr_t addr)
224   -{
225   - uint32_t ret = cpu_inw(NULL, addr & 0xffff);
226   -#ifdef TARGET_WORDS_BIGENDIAN
227   - ret = bswap16(ret);
228   -#endif
229   - return ret;
230   -}
231   -
232   -static void PPC_io_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
233   -{
234   -#ifdef TARGET_WORDS_BIGENDIAN
235   - value = bswap32(value);
236   -#endif
237   - cpu_outl(NULL, addr & 0xffff, value);
238   -}
239   -
240   -static uint32_t PPC_io_readl (void *opaque, target_phys_addr_t addr)
241   -{
242   - uint32_t ret = cpu_inl(NULL, addr & 0xffff);
243   -
244   -#ifdef TARGET_WORDS_BIGENDIAN
245   - ret = bswap32(ret);
246   -#endif
247   - return ret;
248   -}
249   -
250   -CPUWriteMemoryFunc *PPC_io_write[] = {
251   - &PPC_io_writeb,
252   - &PPC_io_writew,
253   - &PPC_io_writel,
254   -};
255   -
256   -CPUReadMemoryFunc *PPC_io_read[] = {
257   - &PPC_io_readb,
258   - &PPC_io_readw,
259   - &PPC_io_readl,
260   -};
261   -
262 204 /*****************************************************************************/
263 205 /* Debug port */
264 206 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
... ...
hw/ppc_chrp.c
  View file @aef445b
... ... @@ -305,7 +305,7 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
305 305 SetIRQFunc *set_irq;
306 306 void *pic;
307 307 m48t59_t *nvram;
308   - int PPC_io_memory, unin_memory;
  308 + int unin_memory;
309 309 int linux_boot, i;
310 310 unsigned long bios_offset, vga_bios_offset;
311 311 uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
... ... @@ -417,9 +417,8 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
417 417 isa_mem_base = 0x80000000;
418 418  
419 419 /* Register 2 MB of ISA IO space */
420   - PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
421   - cpu_register_physical_memory(0xfe000000, 0x00200000, PPC_io_memory);
422   -
  420 + isa_mmio_init(0xfe000000, 0x00200000);
  421 +
423 422 /* init basic PC hardware */
424 423 pic = heathrow_pic_init(&heathrow_pic_mem_index);
425 424 set_irq = heathrow_pic_set_irq;
... ... @@ -463,8 +462,7 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
463 462 isa_mem_base = 0x80000000;
464 463  
465 464 /* Register 8 MB of ISA IO space */
466   - PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
467   - cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory);
  465 + isa_mmio_init(0xf2000000, 0x00800000);
468 466  
469 467 /* UniN init */
470 468 unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
... ...
... ... @@ -675,6 +675,8 @@ int register_ioport_write(int start, int length, int size,
675 675 IOPortWriteFunc *func, void *opaque);
676 676 void isa_unassign_ioport(int start, int length);
677 677  
  678 +void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
  679 +
678 680 /* PCI bus */
679 681  
680 682 extern target_phys_addr_t pci_mem_base;
... ...