gwj / at91sam9263 · Commits

Commit aeb3c85f59bc35371c76f285f0761f01245dc3cd

Authored by bellard
1 parent 1f04275e

Cirrus fixes 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@898 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 45 additions and 32 deletions
hw/cirrus_vga.c
  View file @aeb3c85
1 1 /*
2   - * QEMU Cirrus VGA Emulator.
  2 + * QEMU Cirrus CLGD 54xx VGA Emulator.
3 3 *
4 4 * Copyright (c) 2004 Fabrice Bellard
5   - * Copyright (c) 2004 Suzu
  5 + * Copyright (c) 2004 Makoto Suzuki (suzu)
6 6 *
7 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 8 * of this software and associated documentation files (the "Software"), to deal
... ... @@ -22,6 +22,10 @@
22 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 23 * THE SOFTWARE.
24 24 */
  25 +/*
  26 + * Reference: Finn Thogersons' VGADOC4b
  27 + * available at http://home.worldonline.dk/~finth/
  28 + */
25 29 #include "vl.h"
26 30 #include "vga_int.h"
27 31  
... ... @@ -478,8 +482,8 @@ cirrus_colorexpand_8(CirrusVGAState * s, uint8_t * dst,
478 482 unsigned bitmask;
479 483 int srcskipleft = 0;
480 484  
481   - colors[0] = s->gr[0x00];
482   - colors[1] = s->gr[0x01];
  485 + colors[0] = s->cirrus_shadow_gr0;
  486 + colors[1] = s->cirrus_shadow_gr1;
483 487  
484 488 bitmask = 0x80 >> srcskipleft;
485 489 bits = *src++;
... ... @@ -504,9 +508,9 @@ cirrus_colorexpand_16(CirrusVGAState * s, uint8_t * dst,
504 508 unsigned index;
505 509 int srcskipleft = 0;
506 510  
507   - colors[0][0] = s->gr[0x00];
  511 + colors[0][0] = s->cirrus_shadow_gr0;
508 512 colors[0][1] = s->gr[0x10];
509   - colors[1][0] = s->gr[0x01];
  513 + colors[1][0] = s->cirrus_shadow_gr1;
510 514 colors[1][1] = s->gr[0x11];
511 515  
512 516 bitmask = 0x80 >> srcskipleft;
... ... @@ -534,10 +538,10 @@ cirrus_colorexpand_24(CirrusVGAState * s, uint8_t * dst,
534 538 unsigned index;
535 539 int srcskipleft = 0;
536 540  
537   - colors[0][0] = s->gr[0x00];
  541 + colors[0][0] = s->cirrus_shadow_gr0;
538 542 colors[0][1] = s->gr[0x10];
539 543 colors[0][2] = s->gr[0x12];
540   - colors[1][0] = s->gr[0x01];
  544 + colors[1][0] = s->cirrus_shadow_gr1;
541 545 colors[1][1] = s->gr[0x11];
542 546 colors[1][2] = s->gr[0x13];
543 547  
... ... @@ -567,11 +571,11 @@ cirrus_colorexpand_32(CirrusVGAState * s, uint8_t * dst,
567 571 unsigned index;
568 572 int srcskipleft = 0;
569 573  
570   - colors[0][0] = s->gr[0x00];
  574 + colors[0][0] = s->cirrus_shadow_gr0;
571 575 colors[0][1] = s->gr[0x10];
572 576 colors[0][2] = s->gr[0x12];
573 577 colors[0][3] = s->gr[0x14];
574   - colors[1][0] = s->gr[0x01];
  578 + colors[1][0] = s->cirrus_shadow_gr1;
575 579 colors[1][1] = s->gr[0x11];
576 580 colors[1][2] = s->gr[0x13];
577 581 colors[1][3] = s->gr[0x15];
... ... @@ -1103,7 +1107,7 @@ static int cirrus_get_bpp(VGAState *s1)
1103 1107 }
1104 1108 } else {
1105 1109 /* VGA */
1106   - ret = 8;
  1110 + ret = 0;
1107 1111 }
1108 1112  
1109 1113 return ret;
... ... @@ -1172,16 +1176,6 @@ cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1172 1176 case 0x06: // Unlock Cirrus extensions
1173 1177 *reg_value = s->sr[reg_index];
1174 1178 break;
1175   - case 0x05: // ???
1176   - case 0x07: // Extended Sequencer Mode
1177   - case 0x08: // EEPROM Control
1178   - case 0x09: // Scratch Register 0
1179   - case 0x0a: // Scratch Register 1
1180   - case 0x0b: // VCLK 0
1181   - case 0x0c: // VCLK 1
1182   - case 0x0d: // VCLK 2
1183   - case 0x0e: // VCLK 3
1184   - case 0x0f: // DRAM Control
1185 1179 case 0x10:
1186 1180 case 0x30:
1187 1181 case 0x50:
... ... @@ -1190,6 +1184,8 @@ cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1190 1184 case 0xb0:
1191 1185 case 0xd0:
1192 1186 case 0xf0: // Graphics Cursor X
  1187 + *reg_value = s->sr[0x10];
  1188 + break;
1193 1189 case 0x11:
1194 1190 case 0x31:
1195 1191 case 0x51:
... ... @@ -1197,6 +1193,18 @@ cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1197 1193 case 0x91:
1198 1194 case 0xb1:
1199 1195 case 0xd1:
  1196 + *reg_value = s->sr[0x11];
  1197 + break;
  1198 + case 0x05: // ???
  1199 + case 0x07: // Extended Sequencer Mode
  1200 + case 0x08: // EEPROM Control
  1201 + case 0x09: // Scratch Register 0
  1202 + case 0x0a: // Scratch Register 1
  1203 + case 0x0b: // VCLK 0
  1204 + case 0x0c: // VCLK 1
  1205 + case 0x0d: // VCLK 2
  1206 + case 0x0e: // VCLK 3
  1207 + case 0x0f: // DRAM Control
1200 1208 case 0xf1: // Graphics Cursor Y
1201 1209 case 0x12: // Graphics Cursor Attribute
1202 1210 case 0x13: // Graphics Cursor Pattern Address
... ... @@ -1387,6 +1395,12 @@ static int
1387 1395 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1388 1396 {
1389 1397 switch (reg_index) {
  1398 + case 0x00: // Standard VGA, BGCOLOR 0x000000ff
  1399 + *reg_value = s->cirrus_shadow_gr0;
  1400 + return CIRRUS_HOOK_HANDLED;
  1401 + case 0x01: // Standard VGA, FGCOLOR 0x000000ff
  1402 + *reg_value = s->cirrus_shadow_gr1;
  1403 + return CIRRUS_HOOK_HANDLED;
1390 1404 case 0x02: // Standard VGA
1391 1405 case 0x03: // Standard VGA
1392 1406 case 0x04: // Standard VGA
... ... @@ -1416,10 +1430,10 @@ cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1416 1430 {
1417 1431 switch (reg_index) {
1418 1432 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1419   - s->gr[0x00] = reg_value;
  1433 + s->cirrus_shadow_gr0 = reg_value;
1420 1434 return CIRRUS_HOOK_NOT_HANDLED;
1421 1435 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1422   - s->gr[0x01] = reg_value;
  1436 + s->cirrus_shadow_gr1 = reg_value;
1423 1437 return CIRRUS_HOOK_NOT_HANDLED;
1424 1438 case 0x02: // Standard VGA
1425 1439 case 0x03: // Standard VGA
... ... @@ -1840,9 +1854,9 @@ static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1840 1854 dst = s->vram_ptr + offset;
1841 1855 for (x = 0; x < 8; x++) {
1842 1856 if (val & 0x80) {
1843   - *dst++ = s->gr[0x01];
  1857 + *dst++ = s->cirrus_shadow_gr1;
1844 1858 } else if (mode == 5) {
1845   - *dst++ = s->gr[0x00];
  1859 + *dst++ = s->cirrus_shadow_gr0;
1846 1860 }
1847 1861 val <<= 1;
1848 1862 }
... ... @@ -1862,10 +1876,10 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1862 1876 dst = s->vram_ptr + offset;
1863 1877 for (x = 0; x < 8; x++) {
1864 1878 if (val & 0x80) {
1865   - *dst++ = s->gr[0x01];
  1879 + *dst++ = s->cirrus_shadow_gr1;
1866 1880 *dst++ = s->gr[0x11];
1867 1881 } else if (mode == 5) {
1868   - *dst++ = s->gr[0x00];
  1882 + *dst++ = s->cirrus_shadow_gr0;
1869 1883 *dst++ = s->gr[0x10];
1870 1884 }
1871 1885 val <<= 1;
... ... @@ -1891,6 +1905,8 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1891 1905 return vga_mem_readb(s, addr);
1892 1906 }
1893 1907  
  1908 + addr &= 0x1ffff;
  1909 +
1894 1910 if (addr < 0x10000) {
1895 1911 /* XXX handle bitblt */
1896 1912 /* video memory */
... ... @@ -1965,6 +1981,8 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
1965 1981 return;
1966 1982 }
1967 1983  
  1984 + addr &= 0x1ffff;
  1985 +
1968 1986 if (addr < 0x10000) {
1969 1987 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
1970 1988 /* bitblt */
... ... @@ -2283,11 +2301,6 @@ static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2283 2301 #ifdef DEBUG_VGA_REG
2284 2302 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2285 2303 #endif
2286   -#ifdef DEBUG_S3
2287   - if (s->cr_index >= 0x20)
2288   - printf("S3: CR read index=0x%x val=0x%x\n",
2289   - s->cr_index, val);
2290   -#endif
2291 2304 break;
2292 2305 case 0x3ba:
2293 2306 case 0x3da:
... ...