gwj / at91sam9263 · Commits

Commit ae2dbf7fb04194c367c3352f716715bb569602ed

Authored by ths
1 parent 2382dc6b

Micro-optimize back-to-back store-load sequences. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3743 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 135 additions and 103 deletions
target-mips/translate.c
  View file @ae2dbf7
... ... @@ -543,6 +543,8 @@ typedef struct DisasContext {
543 543 uint32_t hflags, saved_hflags;
544 544 int bstate;
545 545 target_ulong btarget;
  546 + void *last_T0_store;
  547 + int last_T0_gpr;
546 548 } DisasContext;
547 549  
548 550 enum {
... ... @@ -572,12 +574,33 @@ do { \
572 574 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
573 575 } while (0)
574 576  
575   -#define GEN_LOAD_REG_TN(Tn, Rn) \
  577 +#define GEN_LOAD_REG_T0(Rn) \
576 578 do { \
577 579 if (Rn == 0) { \
578   - glue(gen_op_reset_, Tn)(); \
  580 + gen_op_reset_T0(); \
  581 + } else { \
  582 + if (ctx->glue(last_T0, _store) != gen_opc_ptr \
  583 + || ctx->glue(last_T0, _gpr) != Rn) { \
  584 + gen_op_load_gpr_T0(Rn); \
  585 + } \
  586 + } \
  587 +} while (0)
  588 +
  589 +#define GEN_LOAD_REG_T1(Rn) \
  590 +do { \
  591 + if (Rn == 0) { \
  592 + gen_op_reset_T1(); \
  593 + } else { \
  594 + gen_op_load_gpr_T1(Rn); \
  595 + } \
  596 +} while (0)
  597 +
  598 +#define GEN_LOAD_REG_T2(Rn) \
  599 +do { \
  600 + if (Rn == 0) { \
  601 + gen_op_reset_T2(); \
579 602 } else { \
580   - glue(gen_op_load_gpr_, Tn)(Rn); \
  603 + gen_op_load_gpr_T2(Rn); \
581 604 } \
582 605 } while (0)
583 606  
... ... @@ -612,13 +635,21 @@ do { \
612 635 } while (0)
613 636 #endif
614 637  
615   -#define GEN_STORE_TN_REG(Rn, Tn) \
  638 +#define GEN_STORE_T0_REG(Rn) \
616 639 do { \
617 640 if (Rn != 0) { \
618   - glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
  641 + glue(gen_op_store_T0,_gpr)(Rn); \
  642 + ctx->glue(last_T0,_store) = gen_opc_ptr; \
  643 + ctx->glue(last_T0,_gpr) = Rn; \
619 644 } \
620 645 } while (0)
621 646  
  647 +#define GEN_STORE_T1_REG(Rn) \
  648 +do { \
  649 + if (Rn != 0) \
  650 + glue(gen_op_store_T1,_gpr)(Rn); \
  651 +} while (0)
  652 +
622 653 #define GEN_STORE_TN_SRSREG(Rn, Tn) \
623 654 do { \
624 655 if (Rn != 0) { \
... ... @@ -855,126 +886,126 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
855 886 #if defined(TARGET_MIPS64)
856 887 case OPC_LWU:
857 888 op_ldst(lwu);
858   - GEN_STORE_TN_REG(rt, T0);
  889 + GEN_STORE_T0_REG(rt);
859 890 opn = "lwu";
860 891 break;
861 892 case OPC_LD:
862 893 op_ldst(ld);
863   - GEN_STORE_TN_REG(rt, T0);
  894 + GEN_STORE_T0_REG(rt);
864 895 opn = "ld";
865 896 break;
866 897 case OPC_LLD:
867 898 op_ldst(lld);
868   - GEN_STORE_TN_REG(rt, T0);
  899 + GEN_STORE_T0_REG(rt);
869 900 opn = "lld";
870 901 break;
871 902 case OPC_SD:
872   - GEN_LOAD_REG_TN(T1, rt);
  903 + GEN_LOAD_REG_T1(rt);
873 904 op_ldst(sd);
874 905 opn = "sd";
875 906 break;
876 907 case OPC_SCD:
877 908 save_cpu_state(ctx, 1);
878   - GEN_LOAD_REG_TN(T1, rt);
  909 + GEN_LOAD_REG_T1(rt);
879 910 op_ldst(scd);
880   - GEN_STORE_TN_REG(rt, T0);
  911 + GEN_STORE_T0_REG(rt);
881 912 opn = "scd";
882 913 break;
883 914 case OPC_LDL:
884   - GEN_LOAD_REG_TN(T1, rt);
  915 + GEN_LOAD_REG_T1(rt);
885 916 op_ldst(ldl);
886   - GEN_STORE_TN_REG(rt, T1);
  917 + GEN_STORE_T1_REG(rt);
887 918 opn = "ldl";
888 919 break;
889 920 case OPC_SDL:
890   - GEN_LOAD_REG_TN(T1, rt);
  921 + GEN_LOAD_REG_T1(rt);
891 922 op_ldst(sdl);
892 923 opn = "sdl";
893 924 break;
894 925 case OPC_LDR:
895   - GEN_LOAD_REG_TN(T1, rt);
  926 + GEN_LOAD_REG_T1(rt);
896 927 op_ldst(ldr);
897   - GEN_STORE_TN_REG(rt, T1);
  928 + GEN_STORE_T1_REG(rt);
898 929 opn = "ldr";
899 930 break;
900 931 case OPC_SDR:
901   - GEN_LOAD_REG_TN(T1, rt);
  932 + GEN_LOAD_REG_T1(rt);
902 933 op_ldst(sdr);
903 934 opn = "sdr";
904 935 break;
905 936 #endif
906 937 case OPC_LW:
907 938 op_ldst(lw);
908   - GEN_STORE_TN_REG(rt, T0);
  939 + GEN_STORE_T0_REG(rt);
909 940 opn = "lw";
910 941 break;
911 942 case OPC_SW:
912   - GEN_LOAD_REG_TN(T1, rt);
  943 + GEN_LOAD_REG_T1(rt);
913 944 op_ldst(sw);
914 945 opn = "sw";
915 946 break;
916 947 case OPC_LH:
917 948 op_ldst(lh);
918   - GEN_STORE_TN_REG(rt, T0);
  949 + GEN_STORE_T0_REG(rt);
919 950 opn = "lh";
920 951 break;
921 952 case OPC_SH:
922   - GEN_LOAD_REG_TN(T1, rt);
  953 + GEN_LOAD_REG_T1(rt);
923 954 op_ldst(sh);
924 955 opn = "sh";
925 956 break;
926 957 case OPC_LHU:
927 958 op_ldst(lhu);
928   - GEN_STORE_TN_REG(rt, T0);
  959 + GEN_STORE_T0_REG(rt);
929 960 opn = "lhu";
930 961 break;
931 962 case OPC_LB:
932 963 op_ldst(lb);
933   - GEN_STORE_TN_REG(rt, T0);
  964 + GEN_STORE_T0_REG(rt);
934 965 opn = "lb";
935 966 break;
936 967 case OPC_SB:
937   - GEN_LOAD_REG_TN(T1, rt);
  968 + GEN_LOAD_REG_T1(rt);
938 969 op_ldst(sb);
939 970 opn = "sb";
940 971 break;
941 972 case OPC_LBU:
942 973 op_ldst(lbu);
943   - GEN_STORE_TN_REG(rt, T0);
  974 + GEN_STORE_T0_REG(rt);
944 975 opn = "lbu";
945 976 break;
946 977 case OPC_LWL:
947   - GEN_LOAD_REG_TN(T1, rt);
  978 + GEN_LOAD_REG_T1(rt);
948 979 op_ldst(lwl);
949   - GEN_STORE_TN_REG(rt, T1);
  980 + GEN_STORE_T1_REG(rt);
950 981 opn = "lwl";
951 982 break;
952 983 case OPC_SWL:
953   - GEN_LOAD_REG_TN(T1, rt);
  984 + GEN_LOAD_REG_T1(rt);
954 985 op_ldst(swl);
955 986 opn = "swr";
956 987 break;
957 988 case OPC_LWR:
958   - GEN_LOAD_REG_TN(T1, rt);
  989 + GEN_LOAD_REG_T1(rt);
959 990 op_ldst(lwr);
960   - GEN_STORE_TN_REG(rt, T1);
  991 + GEN_STORE_T1_REG(rt);
961 992 opn = "lwr";
962 993 break;
963 994 case OPC_SWR:
964   - GEN_LOAD_REG_TN(T1, rt);
  995 + GEN_LOAD_REG_T1(rt);
965 996 op_ldst(swr);
966 997 opn = "swr";
967 998 break;
968 999 case OPC_LL:
969 1000 op_ldst(ll);
970   - GEN_STORE_TN_REG(rt, T0);
  1001 + GEN_STORE_T0_REG(rt);
971 1002 opn = "ll";
972 1003 break;
973 1004 case OPC_SC:
974 1005 save_cpu_state(ctx, 1);
975   - GEN_LOAD_REG_TN(T1, rt);
  1006 + GEN_LOAD_REG_T1(rt);
976 1007 op_ldst(sc);
977   - GEN_STORE_TN_REG(rt, T0);
  1008 + GEN_STORE_T0_REG(rt);
978 1009 opn = "sc";
979 1010 break;
980 1011 default:
... ... @@ -1059,7 +1090,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1059 1090 case OPC_ANDI:
1060 1091 case OPC_ORI:
1061 1092 case OPC_XORI:
1062   - GEN_LOAD_REG_TN(T0, rs);
  1093 + GEN_LOAD_REG_T0(rs);
1063 1094 GEN_LOAD_IMM_TN(T1, uimm);
1064 1095 break;
1065 1096 case OPC_LUI:
... ... @@ -1077,7 +1108,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1077 1108 case OPC_DSRL32:
1078 1109 #endif
1079 1110 uimm &= 0x1f;
1080   - GEN_LOAD_REG_TN(T0, rs);
  1111 + GEN_LOAD_REG_T0(rs);
1081 1112 GEN_LOAD_IMM_TN(T1, uimm);
1082 1113 break;
1083 1114 }
... ... @@ -1222,7 +1253,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1222 1253 generate_exception(ctx, EXCP_RI);
1223 1254 return;
1224 1255 }
1225   - GEN_STORE_TN_REG(rt, T0);
  1256 + GEN_STORE_T0_REG(rt);
1226 1257 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1227 1258 }
1228 1259  
... ... @@ -1239,14 +1270,14 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1239 1270 MIPS_DEBUG("NOP");
1240 1271 return;
1241 1272 }
1242   - GEN_LOAD_REG_TN(T0, rs);
  1273 + GEN_LOAD_REG_T0(rs);
1243 1274 /* Specialcase the conventional move operation. */
1244 1275 if (rt == 0 && (opc == OPC_ADDU || opc == OPC_DADDU
1245 1276 || opc == OPC_SUBU || opc == OPC_DSUBU)) {
1246   - GEN_STORE_TN_REG(rd, T0);
  1277 + GEN_STORE_T0_REG(rd);
1247 1278 return;
1248 1279 }
1249   - GEN_LOAD_REG_TN(T1, rt);
  1280 + GEN_LOAD_REG_T1(rt);
1250 1281 switch (opc) {
1251 1282 case OPC_ADD:
1252 1283 save_cpu_state(ctx, 1);
... ... @@ -1389,7 +1420,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1389 1420 generate_exception(ctx, EXCP_RI);
1390 1421 return;
1391 1422 }
1392   - GEN_STORE_TN_REG(rd, T0);
  1423 + GEN_STORE_T0_REG(rd);
1393 1424 print:
1394 1425 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1395 1426 }
... ... @@ -1407,21 +1438,21 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
1407 1438 switch (opc) {
1408 1439 case OPC_MFHI:
1409 1440 gen_op_load_HI(0);
1410   - GEN_STORE_TN_REG(reg, T0);
  1441 + GEN_STORE_T0_REG(reg);
1411 1442 opn = "mfhi";
1412 1443 break;
1413 1444 case OPC_MFLO:
1414 1445 gen_op_load_LO(0);
1415   - GEN_STORE_TN_REG(reg, T0);
  1446 + GEN_STORE_T0_REG(reg);
1416 1447 opn = "mflo";
1417 1448 break;
1418 1449 case OPC_MTHI:
1419   - GEN_LOAD_REG_TN(T0, reg);
  1450 + GEN_LOAD_REG_T0(reg);
1420 1451 gen_op_store_HI(0);
1421 1452 opn = "mthi";
1422 1453 break;
1423 1454 case OPC_MTLO:
1424   - GEN_LOAD_REG_TN(T0, reg);
  1455 + GEN_LOAD_REG_T0(reg);
1425 1456 gen_op_store_LO(0);
1426 1457 opn = "mtlo";
1427 1458 break;
... ... @@ -1438,8 +1469,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1438 1469 {
1439 1470 const char *opn = "mul/div";
1440 1471  
1441   - GEN_LOAD_REG_TN(T0, rs);
1442   - GEN_LOAD_REG_TN(T1, rt);
  1472 + GEN_LOAD_REG_T0(rs);
  1473 + GEN_LOAD_REG_T1(rt);
1443 1474 switch (opc) {
1444 1475 case OPC_DIV:
1445 1476 gen_op_div();
... ... @@ -1508,7 +1539,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
1508 1539 MIPS_DEBUG("NOP");
1509 1540 return;
1510 1541 }
1511   - GEN_LOAD_REG_TN(T0, rs);
  1542 + GEN_LOAD_REG_T0(rs);
1512 1543 switch (opc) {
1513 1544 case OPC_CLO:
1514 1545 gen_op_clo();
... ... @@ -1554,8 +1585,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
1554 1585 case OPC_TNE:
1555 1586 /* Compare two registers */
1556 1587 if (rs != rt) {
1557   - GEN_LOAD_REG_TN(T0, rs);
1558   - GEN_LOAD_REG_TN(T1, rt);
  1588 + GEN_LOAD_REG_T0(rs);
  1589 + GEN_LOAD_REG_T1(rt);
1559 1590 cond = 1;
1560 1591 }
1561 1592 break;
... ... @@ -1567,7 +1598,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
1567 1598 case OPC_TNEI:
1568 1599 /* Compare register to immediate */
1569 1600 if (rs != 0 || imm != 0) {
1570   - GEN_LOAD_REG_TN(T0, rs);
  1601 + GEN_LOAD_REG_T0(rs);
1571 1602 GEN_LOAD_IMM_TN(T1, (int32_t)imm);
1572 1603 cond = 1;
1573 1604 }
... ... @@ -1680,8 +1711,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1680 1711 case OPC_BNEL:
1681 1712 /* Compare two registers */
1682 1713 if (rs != rt) {
1683   - GEN_LOAD_REG_TN(T0, rs);
1684   - GEN_LOAD_REG_TN(T1, rt);
  1714 + GEN_LOAD_REG_T0(rs);
  1715 + GEN_LOAD_REG_T1(rt);
1685 1716 bcond = 1;
1686 1717 }
1687 1718 btarget = ctx->pc + 4 + offset;
... ... @@ -1720,7 +1751,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1720 1751 generate_exception(ctx, EXCP_RI);
1721 1752 return;
1722 1753 }
1723   - GEN_LOAD_REG_TN(T2, rs);
  1754 + GEN_LOAD_REG_T2(rs);
1724 1755 break;
1725 1756 default:
1726 1757 MIPS_INVAL("branch/jump");
... ... @@ -1896,7 +1927,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1896 1927 static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
1897 1928 int rs, int lsb, int msb)
1898 1929 {
1899   - GEN_LOAD_REG_TN(T1, rs);
  1930 + GEN_LOAD_REG_T1(rs);
1900 1931 switch (opc) {
1901 1932 case OPC_EXT:
1902 1933 if (lsb + msb > 31)
... ... @@ -1923,26 +1954,26 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
1923 1954 case OPC_INS:
1924 1955 if (lsb > msb)
1925 1956 goto fail;
1926   - GEN_LOAD_REG_TN(T0, rt);
  1957 + GEN_LOAD_REG_T0(rt);
1927 1958 gen_op_ins(lsb, msb - lsb + 1);
1928 1959 break;
1929 1960 #if defined(TARGET_MIPS64)
1930 1961 case OPC_DINSM:
1931 1962 if (lsb > msb)
1932 1963 goto fail;
1933   - GEN_LOAD_REG_TN(T0, rt);
  1964 + GEN_LOAD_REG_T0(rt);
1934 1965 gen_op_dins(lsb, msb - lsb + 1 + 32);
1935 1966 break;
1936 1967 case OPC_DINSU:
1937 1968 if (lsb > msb)
1938 1969 goto fail;
1939   - GEN_LOAD_REG_TN(T0, rt);
  1970 + GEN_LOAD_REG_T0(rt);
1940 1971 gen_op_dins(lsb + 32, msb - lsb + 1);
1941 1972 break;
1942 1973 case OPC_DINS:
1943 1974 if (lsb > msb)
1944 1975 goto fail;
1945   - GEN_LOAD_REG_TN(T0, rt);
  1976 + GEN_LOAD_REG_T0(rt);
1946 1977 gen_op_dins(lsb, msb - lsb + 1);
1947 1978 break;
1948 1979 #endif
... ... @@ -1952,7 +1983,7 @@ fail:
1952 1983 generate_exception(ctx, EXCP_RI);
1953 1984 return;
1954 1985 }
1955   - GEN_STORE_TN_REG(rt, T0);
  1986 + GEN_STORE_T0_REG(rt);
1956 1987 }
1957 1988  
1958 1989 /* CP0 (MMU and control) */
... ... @@ -4611,7 +4642,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
4611 4642 opn = "mfc0";
4612 4643 break;
4613 4644 case OPC_MTC0:
4614   - GEN_LOAD_REG_TN(T0, rt);
  4645 + GEN_LOAD_REG_T0(rt);
4615 4646 save_cpu_state(ctx, 1);
4616 4647 gen_mtc0(env, ctx, rd, ctx->opcode & 0x7);
4617 4648 opn = "mtc0";
... ... @@ -4629,7 +4660,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
4629 4660 break;
4630 4661 case OPC_DMTC0:
4631 4662 check_insn(env, ctx, ISA_MIPS3);
4632   - GEN_LOAD_REG_TN(T0, rt);
  4663 + GEN_LOAD_REG_T0(rt);
4633 4664 save_cpu_state(ctx, 1);
4634 4665 gen_dmtc0(env, ctx, rd, ctx->opcode & 0x7);
4635 4666 opn = "dmtc0";
... ... @@ -4648,7 +4679,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
4648 4679 break;
4649 4680 case OPC_MTTR:
4650 4681 check_insn(env, ctx, ASE_MT);
4651   - GEN_LOAD_REG_TN(T0, rt);
  4682 + GEN_LOAD_REG_T0(rt);
4652 4683 gen_mttr(env, ctx, rd, (ctx->opcode >> 5) & 1,
4653 4684 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
4654 4685 opn = "mttr";
... ... @@ -4789,33 +4820,33 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
4789 4820 case OPC_MFC1:
4790 4821 GEN_LOAD_FREG_FTN(WT0, fs);
4791 4822 gen_op_mfc1();
4792   - GEN_STORE_TN_REG(rt, T0);
  4823 + GEN_STORE_T0_REG(rt);
4793 4824 opn = "mfc1";
4794 4825 break;
4795 4826 case OPC_MTC1:
4796   - GEN_LOAD_REG_TN(T0, rt);
  4827 + GEN_LOAD_REG_T0(rt);
4797 4828 gen_op_mtc1();
4798 4829 GEN_STORE_FTN_FREG(fs, WT0);
4799 4830 opn = "mtc1";
4800 4831 break;
4801 4832 case OPC_CFC1:
4802 4833 gen_op_cfc1(fs);
4803   - GEN_STORE_TN_REG(rt, T0);
  4834 + GEN_STORE_T0_REG(rt);
4804 4835 opn = "cfc1";
4805 4836 break;
4806 4837 case OPC_CTC1:
4807   - GEN_LOAD_REG_TN(T0, rt);
  4838 + GEN_LOAD_REG_T0(rt);
4808 4839 gen_op_ctc1(fs);
4809 4840 opn = "ctc1";
4810 4841 break;
4811 4842 case OPC_DMFC1:
4812 4843 GEN_LOAD_FREG_FTN(DT0, fs);
4813 4844 gen_op_dmfc1();
4814   - GEN_STORE_TN_REG(rt, T0);
  4845 + GEN_STORE_T0_REG(rt);
4815 4846 opn = "dmfc1";
4816 4847 break;
4817 4848 case OPC_DMTC1:
4818   - GEN_LOAD_REG_TN(T0, rt);
  4849 + GEN_LOAD_REG_T0(rt);
4819 4850 gen_op_dmtc1();
4820 4851 GEN_STORE_FTN_FREG(fs, DT0);
4821 4852 opn = "dmtc1";
... ... @@ -4823,11 +4854,11 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
4823 4854 case OPC_MFHC1:
4824 4855 GEN_LOAD_FREG_FTN(WTH0, fs);
4825 4856 gen_op_mfhc1();
4826   - GEN_STORE_TN_REG(rt, T0);
  4857 + GEN_STORE_T0_REG(rt);
4827 4858 opn = "mfhc1";
4828 4859 break;
4829 4860 case OPC_MTHC1:
4830   - GEN_LOAD_REG_TN(T0, rt);
  4861 + GEN_LOAD_REG_T0(rt);
4831 4862 gen_op_mthc1();
4832 4863 GEN_STORE_FTN_FREG(fs, WTH0);
4833 4864 opn = "mthc1";
... ... @@ -4844,8 +4875,8 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
4844 4875 {
4845 4876 uint32_t ccbit;
4846 4877  
4847   - GEN_LOAD_REG_TN(T0, rd);
4848   - GEN_LOAD_REG_TN(T1, rs);
  4878 + GEN_LOAD_REG_T0(rd);
  4879 + GEN_LOAD_REG_T1(rs);
4849 4880 if (cc) {
4850 4881 ccbit = 1 << (24 + cc);
4851 4882 } else
... ... @@ -4854,7 +4885,7 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
4854 4885 gen_op_movf(ccbit);
4855 4886 else
4856 4887 gen_op_movt(ccbit);
4857   - GEN_STORE_TN_REG(rd, T0);
  4888 + GEN_STORE_T0_REG(rd);
4858 4889 }
4859 4890  
4860 4891 #define GEN_MOVCF(fmt) \
... ... @@ -5029,7 +5060,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5029 5060 opn = "floor.w.s";
5030 5061 break;
5031 5062 case FOP(17, 16):
5032   - GEN_LOAD_REG_TN(T0, ft);
  5063 + GEN_LOAD_REG_T0(ft);
5033 5064 GEN_LOAD_FREG_FTN(WT0, fs);
5034 5065 GEN_LOAD_FREG_FTN(WT2, fd);
5035 5066 gen_movcf_s(ctx, (ft >> 2) & 0x7, ft & 0x1);
... ... @@ -5037,7 +5068,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5037 5068 opn = "movcf.s";
5038 5069 break;
5039 5070 case FOP(18, 16):
5040   - GEN_LOAD_REG_TN(T0, ft);
  5071 + GEN_LOAD_REG_T0(ft);
5041 5072 GEN_LOAD_FREG_FTN(WT0, fs);
5042 5073 GEN_LOAD_FREG_FTN(WT2, fd);
5043 5074 gen_op_float_movz_s();
... ... @@ -5045,7 +5076,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5045 5076 opn = "movz.s";
5046 5077 break;
5047 5078 case FOP(19, 16):
5048   - GEN_LOAD_REG_TN(T0, ft);
  5079 + GEN_LOAD_REG_T0(ft);
5049 5080 GEN_LOAD_FREG_FTN(WT0, fs);
5050 5081 GEN_LOAD_FREG_FTN(WT2, fd);
5051 5082 gen_op_float_movn_s();
... ... @@ -5270,7 +5301,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5270 5301 opn = "floor.w.d";
5271 5302 break;
5272 5303 case FOP(17, 17):
5273   - GEN_LOAD_REG_TN(T0, ft);
  5304 + GEN_LOAD_REG_T0(ft);
5274 5305 GEN_LOAD_FREG_FTN(DT0, fs);
5275 5306 GEN_LOAD_FREG_FTN(DT2, fd);
5276 5307 gen_movcf_d(ctx, (ft >> 2) & 0x7, ft & 0x1);
... ... @@ -5278,7 +5309,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5278 5309 opn = "movcf.d";
5279 5310 break;
5280 5311 case FOP(18, 17):
5281   - GEN_LOAD_REG_TN(T0, ft);
  5312 + GEN_LOAD_REG_T0(ft);
5282 5313 GEN_LOAD_FREG_FTN(DT0, fs);
5283 5314 GEN_LOAD_FREG_FTN(DT2, fd);
5284 5315 gen_op_float_movz_d();
... ... @@ -5286,7 +5317,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5286 5317 opn = "movz.d";
5287 5318 break;
5288 5319 case FOP(19, 17):
5289   - GEN_LOAD_REG_TN(T0, ft);
  5320 + GEN_LOAD_REG_T0(ft);
5290 5321 GEN_LOAD_FREG_FTN(DT0, fs);
5291 5322 GEN_LOAD_FREG_FTN(DT2, fd);
5292 5323 gen_op_float_movn_d();
... ... @@ -5484,7 +5515,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5484 5515 break;
5485 5516 case FOP(17, 22):
5486 5517 check_cp1_64bitmode(ctx);
5487   - GEN_LOAD_REG_TN(T0, ft);
  5518 + GEN_LOAD_REG_T0(ft);
5488 5519 GEN_LOAD_FREG_FTN(WT0, fs);
5489 5520 GEN_LOAD_FREG_FTN(WTH0, fs);
5490 5521 GEN_LOAD_FREG_FTN(WT2, fd);
... ... @@ -5496,7 +5527,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5496 5527 break;
5497 5528 case FOP(18, 22):
5498 5529 check_cp1_64bitmode(ctx);
5499   - GEN_LOAD_REG_TN(T0, ft);
  5530 + GEN_LOAD_REG_T0(ft);
5500 5531 GEN_LOAD_FREG_FTN(WT0, fs);
5501 5532 GEN_LOAD_FREG_FTN(WTH0, fs);
5502 5533 GEN_LOAD_FREG_FTN(WT2, fd);
... ... @@ -5508,7 +5539,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
5508 5539 break;
5509 5540 case FOP(19, 22):
5510 5541 check_cp1_64bitmode(ctx);
5511   - GEN_LOAD_REG_TN(T0, ft);
  5542 + GEN_LOAD_REG_T0(ft);
5512 5543 GEN_LOAD_FREG_FTN(WT0, fs);
5513 5544 GEN_LOAD_FREG_FTN(WTH0, fs);
5514 5545 GEN_LOAD_FREG_FTN(WT2, fd);
... ... @@ -5695,12 +5726,12 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
5695 5726 if (index == 0)
5696 5727 gen_op_reset_T0();
5697 5728 else
5698   - GEN_LOAD_REG_TN(T0, index);
  5729 + GEN_LOAD_REG_T0(index);
5699 5730 } else if (index == 0) {
5700   - GEN_LOAD_REG_TN(T0, base);
  5731 + GEN_LOAD_REG_T0(base);
5701 5732 } else {
5702   - GEN_LOAD_REG_TN(T0, base);
5703   - GEN_LOAD_REG_TN(T1, index);
  5733 + GEN_LOAD_REG_T0(base);
  5734 + GEN_LOAD_REG_T1(index);
5704 5735 gen_op_addr_add();
5705 5736 }
5706 5737 /* Don't do NOP if destination is zero: we must perform the actual
... ... @@ -5757,7 +5788,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
5757 5788 check_cp1_64bitmode(ctx);
5758 5789 switch (opc) {
5759 5790 case OPC_ALNV_PS:
5760   - GEN_LOAD_REG_TN(T0, fr);
  5791 + GEN_LOAD_REG_T0(fr);
5761 5792 GEN_LOAD_FREG_FTN(DT0, fs);
5762 5793 GEN_LOAD_FREG_FTN(DT1, ft);
5763 5794 gen_op_float_alnv_ps();
... ... @@ -6081,15 +6112,15 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6081 6112 op2 = MASK_BSHFL(ctx->opcode);
6082 6113 switch (op2) {
6083 6114 case OPC_WSBH:
6084   - GEN_LOAD_REG_TN(T1, rt);
  6115 + GEN_LOAD_REG_T1(rt);
6085 6116 gen_op_wsbh();
6086 6117 break;
6087 6118 case OPC_SEB:
6088   - GEN_LOAD_REG_TN(T1, rt);
  6119 + GEN_LOAD_REG_T1(rt);
6089 6120 gen_op_seb();
6090 6121 break;
6091 6122 case OPC_SEH:
6092   - GEN_LOAD_REG_TN(T1, rt);
  6123 + GEN_LOAD_REG_T1(rt);
6093 6124 gen_op_seh();
6094 6125 break;
6095 6126 default: /* Invalid */
... ... @@ -6097,7 +6128,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6097 6128 generate_exception(ctx, EXCP_RI);
6098 6129 break;
6099 6130 }
6100   - GEN_STORE_TN_REG(rd, T0);
  6131 + GEN_STORE_T0_REG(rd);
6101 6132 break;
6102 6133 case OPC_RDHWR:
6103 6134 check_insn(env, ctx, ISA_MIPS32R2);
... ... @@ -6128,19 +6159,19 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6128 6159 generate_exception(ctx, EXCP_RI);
6129 6160 break;
6130 6161 }
6131   - GEN_STORE_TN_REG(rt, T0);
  6162 + GEN_STORE_T0_REG(rt);
6132 6163 break;
6133 6164 case OPC_FORK:
6134 6165 check_insn(env, ctx, ASE_MT);
6135   - GEN_LOAD_REG_TN(T0, rt);
6136   - GEN_LOAD_REG_TN(T1, rs);
  6166 + GEN_LOAD_REG_T0(rt);
  6167 + GEN_LOAD_REG_T1(rs);
6137 6168 gen_op_fork();
6138 6169 break;
6139 6170 case OPC_YIELD:
6140 6171 check_insn(env, ctx, ASE_MT);
6141   - GEN_LOAD_REG_TN(T0, rs);
  6172 + GEN_LOAD_REG_T0(rs);
6142 6173 gen_op_yield();
6143   - GEN_STORE_TN_REG(rd, T0);
  6174 + GEN_STORE_T0_REG(rd);
6144 6175 break;
6145 6176 #if defined(TARGET_MIPS64)
6146 6177 case OPC_DEXTM ... OPC_DEXT:
... ... @@ -6155,11 +6186,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6155 6186 op2 = MASK_DBSHFL(ctx->opcode);
6156 6187 switch (op2) {
6157 6188 case OPC_DSBH:
6158   - GEN_LOAD_REG_TN(T1, rt);
  6189 + GEN_LOAD_REG_T1(rt);
6159 6190 gen_op_dsbh();
6160 6191 break;
6161 6192 case OPC_DSHD:
6162   - GEN_LOAD_REG_TN(T1, rt);
  6193 + GEN_LOAD_REG_T1(rt);
6163 6194 gen_op_dshd();
6164 6195 break;
6165 6196 default: /* Invalid */
... ... @@ -6167,7 +6198,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6167 6198 generate_exception(ctx, EXCP_RI);
6168 6199 break;
6169 6200 }
6170   - GEN_STORE_TN_REG(rd, T0);
  6201 + GEN_STORE_T0_REG(rd);
6171 6202 break;
6172 6203 #endif
6173 6204 default: /* Invalid */
... ... @@ -6252,16 +6283,16 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6252 6283 generate_exception(ctx, EXCP_RI);
6253 6284 break;
6254 6285 }
6255   - GEN_STORE_TN_REG(rt, T0);
  6286 + GEN_STORE_T0_REG(rt);
6256 6287 break;
6257 6288 case OPC_RDPGPR:
6258 6289 check_insn(env, ctx, ISA_MIPS32R2);
6259 6290 GEN_LOAD_SRSREG_TN(T0, rt);
6260   - GEN_STORE_TN_REG(rd, T0);
  6291 + GEN_STORE_T0_REG(rd);
6261 6292 break;
6262 6293 case OPC_WRPGPR:
6263 6294 check_insn(env, ctx, ISA_MIPS32R2);
6264   - GEN_LOAD_REG_TN(T0, rt);
  6295 + GEN_LOAD_REG_T0(rt);
6265 6296 GEN_STORE_TN_SRSREG(rd, T0);
6266 6297 break;
6267 6298 default:
... ... @@ -6589,6 +6620,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
6589 6620 }
6590 6621 }
6591 6622 done_generating:
  6623 + ctx.last_T0_store = NULL;
6592 6624 *gen_opc_ptr = INDEX_op_end;
6593 6625 if (search_pc) {
6594 6626 j = gen_opc_ptr - gen_opc_buf;
... ...