gwj / at91sam9263 · Commits

Commit ae1c1a3d68c75ebc5487f123c73dcfff5844b02a

Authored by aurel32
1 parent afdf8109

target-ppc: add altivec cache instructions 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6275 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 27 additions and 0 deletions
target-ppc/translate.c
  View file @ae1c1a3
... ... @@ -4152,6 +4152,33 @@ GEN_HANDLER2(dcbz_970, &quot;dcbz&quot;, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4152 4152 tcg_temp_free(t0);
4153 4153 }
4154 4154  
  4155 +/* dst / dstt */
  4156 +GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
  4157 +{
  4158 + if (rA(ctx->opcode) == 0) {
  4159 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
  4160 + } else {
  4161 + /* interpreted as no-op */
  4162 + }
  4163 +}
  4164 +
  4165 +/* dstst /dststt */
  4166 +GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
  4167 +{
  4168 + if (rA(ctx->opcode) == 0) {
  4169 + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
  4170 + } else {
  4171 + /* interpreted as no-op */
  4172 + }
  4173 +
  4174 +}
  4175 +
  4176 +/* dss / dssall */
  4177 +GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
  4178 +{
  4179 + /* interpreted as no-op */
  4180 +}
  4181 +
4155 4182 /* icbi */
4156 4183 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4157 4184 {
... ...