Commit ad1a5b7853dbc510a9f6c9628ff623148d06c9d5

Authored by bellard
1 parent 6c3ee14f

rol/ror cc fix


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1845 c046a42c-6fe2-441c-8c8c-71466251a162
target-i386/ops_template_mem.h
@@ -73,8 +73,8 @@ void OPPROTO glue(glue(op_rol, MEM_SUFFIX), _T0_T1_cc)(void) @@ -73,8 +73,8 @@ void OPPROTO glue(glue(op_rol, MEM_SUFFIX), _T0_T1_cc)(void)
73 int count; 73 int count;
74 target_long src; 74 target_long src;
75 75
76 - count = T1 & SHIFT_MASK;  
77 - if (count) { 76 + if (T1 & SHIFT1_MASK) {
  77 + count = T1 & SHIFT_MASK;
78 src = T0; 78 src = T0;
79 T0 &= DATA_MASK; 79 T0 &= DATA_MASK;
80 T0 = (T0 << count) | (T0 >> (DATA_BITS - count)); 80 T0 = (T0 << count) | (T0 >> (DATA_BITS - count));
@@ -97,8 +97,8 @@ void OPPROTO glue(glue(op_ror, MEM_SUFFIX), _T0_T1_cc)(void) @@ -97,8 +97,8 @@ void OPPROTO glue(glue(op_ror, MEM_SUFFIX), _T0_T1_cc)(void)
97 int count; 97 int count;
98 target_long src; 98 target_long src;
99 99
100 - count = T1 & SHIFT_MASK;  
101 - if (count) { 100 + if (T1 & SHIFT1_MASK) {
  101 + count = T1 & SHIFT_MASK;
102 src = T0; 102 src = T0;
103 T0 &= DATA_MASK; 103 T0 &= DATA_MASK;
104 T0 = (T0 >> count) | (T0 << (DATA_BITS - count)); 104 T0 = (T0 >> count) | (T0 << (DATA_BITS - count));